Abstract: A method and apparatus is disclosed for providing highly linear resistance with high sheet values, and for implementing resistors in a conventional CMOS process when either drain or source must operate near the rail of a circuit. Accordingly, a five terminal distributed MOS resistor device includes a drain terminal, a source terminal, and a channel region disposed between the drain terminal and the source terminal. A bulk terminal is adjacent the channel region. A first gate terminal is adjacent the source terminal and a second gate terminal is adjacent the drain terminal. Lastly, a gate region of resistive material is disposed between the first gate terminal and the second gate terminal, wherein upon application of a voltage to the first gate terminal and the second gate terminal, a voltage drop across the gate region is equally distributed along a length of an electrical channel in the channel region.

Abstract: A pole and zero circuit for changing the position of a pole, or a zero, of an amplifier including a capacitor to change the position of the pole or zero for the amplifier, a first current path for the capacitor, a variable impedance device in the first current path to connect the capacitor to the amplifier, and a current source to control the impedance of the variable impedance device.

Abstract: The present invention relates to controlling load impedance during wireless communications to maintain amplifier linearity for transmissions, such as voice and high-speed data, having significantly different peak-to-average power ratios. At a desired output power, a first load impedance is selected for transmissions having a first peak-to-average power ratio and a second load impedance is selected for transmissions having a second peak-to-average power ratio, in order to ensure that appropriate amplifier linearity is achieved for both voice and high-speed data transmissions. Preferably, amplifier efficiency is optimized for transmissions having the first and second peak-to-average power ratios. Changing the effective load impedance may be effected by providing a first impedance network and switching a second impedance network in association with the first impedance network.

Abstract: Circuitry and methods for improved amplifiers with large bandwidth and constant gain-are provided. The combination of a synthetic inductive drain load and a bridged-T matching network provide amplifiers that can drive a substantial capacitive load with the above mentioned improvements over prior amplifiers. Additionally, circuits presented allow for improved rise time and insensitivity to temperature variations.

Abstract: An electrically tunable radio frequency (RF) amplifier includes a resonant circuit having a voltage variable capacitance as one of its elements. In one approach, a drain diffusion capacitance of one of the transistors within the amplifier is used as the voltage variable capacitance. A voltage adjustment unit is provided to adjust a bias voltage on the voltage variable capacitance to change the capacitance value thereof and thus modify the operating frequency range of the amplifier. In one embodiment, the voltage adjustment unit also provides a power supply noise blocking function.

Abstract: A transconductor tuning circuit for controlling transconductance of a transconductor. The tuning circuit includes a first MOS (Metal-Oxide Semiconductor) transistor. A source terminal of the first MOS transistor is connected to a power source. A gate terminal and a drain terminal of the first MOS transistor being connected to each other. A gate terminal and a drain terminal of a second MOS transistor being connected. A first input terminal of a first error amplifier is connected to the gate terminal of the first MOS transistor. A second input terminal of the first error amplifier is connected to the gate terminal of the second MOS transistor. The first error amplifier outputs an output signal in form of a bias signal for controlling tuning of the transconductor.

Abstract: A method and system to balance a signal through a plurality of parallel amplifier elements of an amplifier device. An input signal to the amplifier device is divided substantially equally among a plurality of parallel amplifier elements. A signal through each of the amplifier elements is measured. If any of the measured signals deviates by a predetermined threshold from a reference signal, an adjustment to an input parameter to a tuning circuit associated with the particular amplifier element is determined. The determined adjustment is applied to the particular a tuning circuit to appropriately adjust the output of the deviating amplifier element. The output of the plurality of amplifier elements is combined as the total output of the amplifier device.

Abstract: A circuit for tuning a transconductance amplifier includes a first transconductance amplifier outputting a first current from its output, a second transconductance amplifier outputting a second current from an output that is coupled to the output of the first transconductance amplifier, and a feedback loop. The feedback loop provides a control signal that varies with a difference between the first current and the second current and is used to adjust the transconductance of the second transconductance amplifier.

Abstract: The current passing in a main trans-conductor circuit is compared in analog domain with a reference current. If the passing current exceeds the reference current, another trans-conductor circuit may be switched on to cause the effective area of trans-conductor circuits to be increased. Using such a feature, the trans-conductance value may be maintained substantially constant without substantially increasing power.

Abstract: An apparatus comprising a common-base amplifier circuit and a control circuit. The amplifier circuit may be configured to generate an output signal having a transimpedance bandwidth in response to an input signal. The control circuit may be (i) coupled between the output signal and the input signal and (ii) configured to implement input signal control to provide input overload current capability.

Abstract: In an electronic inductor circuit, an operational amplifier drives the base of the electronic inductor transistor, and receives negative feedback from the emitter of the transistor. The transistor and operational amplifier combine to form a voltage-controlled current source (VCCS) with respect to the loop current. A voltage divider connected across the rectified Tip and Ring voltage (or another node of the circuit at an equivalent voltage) provides a DC reference to the positive input of the operational amplifier, so that the line current automatically increases with an increase in line voltage. A capacitor couples the transmit signal driver to the positive input of the operational amplifier. This electronic inductor circuit can be driven using a low voltage supply and provides sufficient linearity for high-speed modem applications.

Abstract: A high-frequency amplifier circuit for a UHF television tuner includes an FET having a first gate for inputting a UHF band television signal and a second gate for applying an AGC voltage which varies the gain. The second gate is grounded via a series circuit including a resistor and a DC-cutting capacitor. The impedance of the DC-cutting capacitor is sufficiently lower than the resistance of the resistor in the UHF band.

Abstract: A tuning circuit for compensating an inter-stage matching network included in an integrated multistage radio frequency (RF) amplifier includes one or more capacitors connected in shunt between ground and a voltage supply to the amplifier. The capacitors have values selected to effectively compensate the inductance from a pull-up inductor included in the inter-stage matching network to provide improved inter-stage matching when inductance and capacitance values of the inter-stage matching network deviate from their desired values due to parasitics and/or when other components, such as input-stage and output-stage transistors of the amplifiers deviate from their pre-fabrication simulation models.

Abstract: A apparatus for providing a waveform as a switched input into an output matching network of a standard class E amplifier. The apparatus includes a switch in communication with the input and the combining device receiving amplitude and phase information from the primary waveform. The combining device functions to combine the amplitude and phase information to create a control signal which is used to control the switch and create a secondary waveform for input to the matching network. In this way, an amplitude modulated waveform is amplified at high efficiency, enabling application of either all or part of the phase and/or amplitude modulation at the input of the amplifier.

Abstract: A pole and zero circuit for changing the position of a pole, or a zero, of an amplifier including a capacitor to change the position of the pole or zero for the amplifier, a first current path for the capacitor, a variable impedance device in the first current path to connect the capacitor to the amplifier, and a current source to control the impedance of the variable impedance device.

Abstract: A tunable impedance matching circuit is provided for tuning an active device, such as, e.g., a field effect transistor, in a RF power amplifier circuit. The matching circuit includes an adjustable length transmission line for electrically coupling a RF signal between an active device and its source and a load. The transmission line, which has a length approximately equal to a quarter of a wavelength of the fundamental frequency of a RF signal being amplified, is adjusted to achieve selected performance characteristic(s) of the amplifier, such as, e.g., input return loss.

Abstract: An electrically tunable radio frequency (RF) amplifier includes a resonant circuit having a voltage variable capacitance as one of its elements. In one approach, a drain diffusion capacitance of one of the transistors within the amplifier is used as the voltage variable capacitance. A voltage adjustment unit is provided to adjust a bias voltage on the voltage variable capacitance to change the capacitance value thereof and thus modify the operating frequency range of the amplifier. In one embodiment, the voltage adjustment unit also provides a power supply noise blocking function.

Abstract: A tunable differential amplifier includes an amplifier circuit, a current mirror, a dynamic current regulator, and a dynamic output common mode regulator. The current mirror is operably coupled to the amplifier circuit and controls the current flowing through each leg of the amplifier circuit. The current through the current mirror is established based on a regulated current provided by the dynamic current regulator and a common mode error current signal provided by the dynamic output common mode regulator. The common mode error signal is representative of an error between the desired output common mode of the amplifier circuit and the actual common mode of the output of the amplifier circuit. The regulated current is based on the common mode of the input of the amplifier circuit. As such, the biasing current and the common mode output of the differential amplifier is dynamically regulated.

Abstract: A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a variable resistor capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.

Abstract: A network line equalizer includes a transconductance-controlled, tunable single zero high-pass, filter that includes a single zero impedance circuit, and first and second MOS transistors that output differential currents based on differential input signals and the impedance of the single zero impedance circuit. The MOS transistors act as source followers to convert the differential input voltage signals to respective differential current signals. The single zero impedance circuit connects the first and second MOS transistors, and causes the first and second MOS transistors to output a corrected pair of differential signals based on the impedance. The impedance of the single zero IMPEDANCE circuit is implemented using CMOS transistors, enabling the impedance to be dynamically controlled by an external impedance controller.

Abstract: A method and apparatus for calibrating a Gm cell using a Gm replica cell. A digital to analog converter receives a Gm setting code and generates a reference current. The Gm replica cell adjusts the tuning voltage until the difference between a pair of drain currents is substantially equal to the reference current. Where this condition is satisfied, the proper tuning voltage has been acquired. This results in proper calibration for the tuning voltage, which then may be utilized by a Gm cell connected with the Gm replica cell.

Abstract: A switching Gm cell allowing a wide transconductance range with a limited voltage range. The Gm cell includes a plurality of Gm setting devices, the operation of which is controlled by a Gm setting code. The Gm setting code is inputted into a switching circuit which turns on and off at least one of said Gm setting devices. Thus, coarse adjustments of the overall transconductance of the cell may be adjusted by changing the Gm setting code and fine adjustments may be made by utilizing the conventional method of adjusting a tuning voltage.

Abstract: A tuning circuit for compensating an inter-stage matching network included in an integrated multistage radio frequency (RF) amplifier includes one or more capacitors connected in shunt between ground and a voltage supply to the amplifier. The capacitors have values selected to effectively compensate the inductance from a pull-up inductor included in the inter-stage matching network to provide improved inter-stage matching when inductance and capacitance values of the inter-stage matching network deviate from their desired values due to parasitics and/or when other components, such as input-stage and output-stage transistors of the amplifiers deviate from their pre-fabrication simulation models.

Abstract: A monolithic active frequency selection circuit includes an input presenting a frequency-dependent impedance and a first gain block configured to provide less than unity voltage gain, a high input impedance and a low output impedance. An output of the first amplifier is coupled to the frequency selection circuit input. The frequency selection circuit includes a first phase shifter that, in one aspect, is formed by a first capacitor coupled between the first port and a reference voltage. The frequency selection circuit also includes a second amplifier configured to provide greater than unity voltage gain. The second amplifier has an input coupled to the output of the first amplifier and an output coupled to the input of the first amplifier. The frequency selection circuit further includes a second phase shifter, which may be formed from a capacitor coupled between the output of the second amplifier and a reference voltage.

Abstract: RF amplifiers used in communications systems exhibit backward intermodulation caused by non-linear amplification. Backward intermodulation of the transmit signal and an external signal, which reaches the output of the amplifier through the antenna, results in an unwanted third-order intermodulation product that potentially interferes with the proper reception of the receive signal. The receive sensitivity of the communications system is adversely affected by this unwanted third-order intermodulation product. By mixing a second-order intermodulation component, caused by the same backward intermodulation, with the transmit signal, a compensation signal is created allowing the cancellation of the unwanted third-order intermodulation component.

Abstract: A two stage low noise amplifier (10) includes a first stage (12) and a second stage (14). The first stage (12) receives an input signal (VIN), performs single to differential conversion on the input signal (VIN), and generates an input differential signal (VA and VB) therefrom. A bias level of the input differential signal (VA and VB) may be adjusted to an optimal bias point of the second stage (14). The first stage (12) provides the input differential signal (VA and VB) to the second stage (14) And provides image rejection without any loss in amplifier gain. The second stage (14) performs image rejection on the input differential signal (VA and VB) and generates an output differential signal (V+ and V−) therefrom. The first stage (12) and stage (14) include a tuning circuit to adjust a center operating frequency of the amplifier (10). The first stage (12) and the second stage (14) receive control signals from a control bus (16) in order to adjust the center operating frequency.

Abstract: An RF power amplifier is provided for use with wireless transmission systems such as cellular phones. An RF power amplifier includes direct drive amplifier circuitry operating in a push-pull scheme. The RF power amplifier includes a pair of switching devices driven by a pair of mutually coupled inductive devices. The inductive devices may be magnetically or capacitively coupled together. The RF power amplifier may be formed on a single integrated circuit and include an on-chip bypass capacitor. The RF power amplifier may utilize a voltage regulator for providing a regulated voltage source. The RF power amplifier may be provided using a dual oxide gate device resulting in an improved amplifier. The RF power amplifier may be packaged using flip chip technology and multi-layer ceramic chip carrier technology.

Abstract: A spectroscopy system is provided having an automatic pole-zero error correction circuit. A gated integrator of the system integrates a shaped pulse and trailing edge of the shaped pulse for sampling by an analog-to-digital converter. A pair of samples are converted along the slope of each integrated shaped pulse passing through the system. The two samples are compared on a pulse by pulse basis. An algorithm generates a control word for affecting a change in a pole-zero network coupled along a shaping amplifier of the system. In response to the control word, an MDAC of the pole-zero network affects a change in the system to correct the pole-zero error. When the pole-zero error is eliminated or reaches an acceptable user level, the correction circuitry automatically shuts off.

Abstract: An amplifier circuit including at least one first input amplifier; at least one second amplifier cascode-assembled with the first amplifier; and at least one reactive impedance circuit, mounted in series with the second amplifier, the reactive impedance circuit being formed by two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit.

Abstract: A monolithic active frequency selection circuit includes an input presenting a frequency-dependent impedance and a first gain block configured to provide less than unity voltage gain, a high input impedance and a low output impedance. An output of the first amplifier is coupled to the frequency selection circuit input. The frequency selection circuit includes a first phase shifter that, in one aspect, is formed by a first capacitor coupled between the first port and a reference voltage. The frequency selection circuit also includes a second amplifier configured to provide greater than unity voltage gain. The second amplifier has an input coupled to the output of the first amplifier and an output coupled to the input of the first amplifier. The frequency selection circuit further includes a second phase shifter, which may be formed from a capacitor coupled between the output of the second amplifier and a reference voltage.

Abstract: A monolithic active frequency selection circuit includes an input presenting a frequency-dependent impedance and a first gain block configured to provide less than unity voltage gain, a high input impedance and a low output impedance. An output of the first amplifier is coupled to the frequency selection circuit input. The frequency selection circuit includes a first phase shifter that, in one aspect, is formed by a first capacitor coupled between the first port and a reference voltage. The frequency selection circuit also includes a second amplifier configured to provide greater than unity voltage gain. The second amplifier has an input coupled to the output of the first amplifier and an output coupled to the input of the first amplifier. The frequency selection circuit further includes a second phase shifter, which may be formed from a capacitor coupled between the output of the second amplifier and a reference voltage.

Abstract: An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node.

Abstract: A microwave amplifying circuit 1 has transistors 6, 8, and 10 and circuit sections 12, 14, 16, and 18. The circuit section 14 has one terminal electrically connected to a first current terminal of the transistor 6 and another terminal electrically connected to a control terminal of the transistor. The microwave amplifying circuit includes an impedance part 20a for supplying variable impedance between the terminals. The circuit section 16 has one terminal electrically connected to a first current terminal of the transistor 8 and another terminal electrically connected to a control terminal of the transistor 10. The circuit section 16 includes an impedance part 20b for providing variable impedance between the terminals.

Abstract: A bandwidth enhancement method by adding a peaking capacitor to a transimpedance amplifier for creating peaking effect is to add a peaking capacitor to a transimpedance amplifier for obtaining an extra pole that can alter circuit phase and enhance bandwidth of the transimpedance amplifier without changing the framework and DC gain of the original amplifier circuit.

Abstract: An automatic pole-zero (APZ) adjustment circuit for an ionizing radiation spectroscopy system. An output of a preamplifier is sampled to identify the decay time constant of the preamplifier output. A correction based upon the identified decay time constant is generated by a correction signal generator and applied through either an analog pole-zero adjustment network or a programmable digital shaping filter to accomplish pole-zero correction.

Abstract: Resonator comprising first and second balanced integrators (I1, I2) each composed with a balanced amplifier and having a non-inverting (in+) and an inverting (in−) input terminal, as well as a non-inverting (out+) and an inverting (out−) output terminal. First and second coupling circuits (Y1, Y2) are interconnected between the non-inverting output terminal (out+) of the first integrator (I1) and the non-inverting input terminal (in+) of the second integrator (I2) and between the inverting output terminal (out−) of the first integrator (I1) and the inverting input terminal (in-) of the second integrator (I2) respectively.

Abstract: An apparatus (Z) having controllable impedance is inserted from output (22) to ground (23) of an audio-signal amplifier(20). Typically, the apparatus comprises a diode-chain (50) having multiple steps (52, 53, and so on); its first step (52) is connected to one terminal (62) of the apparatus. A capacitor (82, 84, and so on) is connected from each step to a second terminal (61). The network formed by the diode-chain (50) and the capacitor network (80) is called a matrix (60C). To bypass audio frequencies away from the chopping effect of the diodes, an inductor (31) parallels the matrix. To prevent shorting of audio signals to ground, a larger capacitor (30) is in series with the inductor. An unstable voltage at output will see increasing capacitance as it gradually breaks over more and more diodes. The changing of capacitive impedance in relation to the amplitude of the unstable voltage is designed such that the unstable voltage cannot grow too large. More complex matrices further reduce voltage fluctuations.

Abstract: A two stage low noise amplifier (10) includes a first stage (12) and a second stage (14). The first stage (12) receives an input signal (VIN), performs single to differential conversion on the input signal (VIN), and generates an input differential signal (VA and VB) therefrom. A bias level of the input differential signal (VA and VB) may be adjusted to an optimal bias point of the second stage (14). The first stage (12) provides the input differential signal (VA and VB) to the second stage (14) without any loss in amplifier gain. The second stage (14) performs image rejection on the input differential signal (VA and VB) and generates an output differential signal (V+ and V−) therefrom. The first stage (12) and the second stage (14) include a tuning circuit to adjust a center operating frequency of the amplifier (10). The first stage (12) and the second stage (14) receive control signals from a control bus (16) in order to adjust the center operating frequency.

Abstract: A semiconductor integrated circuit device comprises a multiple-stage amplifier including a plurality of transistors. The multiple-stage amplifier has a first stage comprising a plurality of bipolar transistors each having a single emitter structure. The bipolar transistors are connected parallel to each other. The semiconductor integrated circuit device can easily be designed, is of a self-aligned structure, and has a single transistor size. The semiconductor integrated circuit device may be used as a low-noise, high-power-gain high-frequency amplifier.

Abstract: In this invention a single additional capacitor is added to a tuned cascode LNA which boosts the circuit Q and the gain of the amplifier. The added capacitor creates a negative real part of the impedance which when combined with the impedance of the LC tank circuit improves both the Q and the gain of the amplifier. The capacitor does not dissipate any power, and being a passive device the capacitor does not add additional noise to the circuit. With an improved gain there is a much improved signal to noise ratio. The higher Q allows the amplifier to provide some additional bandpass and reduce image reduction requirements in subsequent amplifier stages.

Abstract: The high frequency tuning amplifier for buffer has a tuning circuit consisting of a serial circuit of the first and second inductors connected between the output of transistor amplifying stage and the power source, a first capacitor connected in parallel to the serial circuit of first and second inductors, a serial circuit of the second and third capacitors connected in parallel to the second inductor and a switching element to which a band switch voltage is supplied, connected between the connecting point of the second and third capacitors and the reference voltage point. The tuning circuit is tuned to the high band frequency when the switching element is turned ON and to the low band frequency when the switching element is turned OFF.

Abstract: A signal processing apparatus includes an amplifier for processing an input signal and a variable voltage source. The variable voltage source is coupled to the amplifier substrate, and the input impedance of the amplifier is controlled by varying the voltage on the substrate body of the amplifier. In processing a radio frequency (RF) signal, the amplifier receives the RF signal, and by varying the voltage on the amplifier substrate, the input impedance of the amplifier is matched to the source impedance. The overall noise performance of the amplifier is improved by employing an automatic gain control system and a digital-to-analog converter in a feedback loop between the output port of the amplifier and the amplifier substrate.

Abstract: A power transistor with an integrated linearizer is provided in a package having only standard transistor terminals. The linearizer arranged between the base and collector of the transistor uses a Schottky diode as a nonlinear device that compensates for gain and phase deviations of the transistor. A collector voltage source that supplies power to the transistor provides bias to the diode. A DC blocking capacitor isolates an RF path between the input and output of the transistor from a diode biasing circuit to allow the collector voltage source to provide bias to the linearizer and the transistor separately. A tuning inductor is coupled in series with the DC blocking capacitor to offset the undesired phase rotation introduced by the capacitor. A DC biasing resistor is coupled between the diode and the collector of the transistor to set bias current supplied to the diode and isolate the collector voltage source from the RF path and ground.

Abstract: Power amplifiers having reactive networks (such as classes C, C-E, E and F) employ tunable reactive devices in their reactive networks, with the reactive devices respective reactance values capable of being adjusted by means of respective control signals. The tunable reactive devices are made from micro-electromechanical (MEM) devices capable of being integrated with the control circuitry needed to produce the control signals and other amplifier components on a common substrate. The reactive components have high Q values across their adjustment range, enabling the amplifier to produce an output with a low harmonic content over a wide range of input signal frequencies, and a frequency agile, high quality output. The invention can be realized on a number of foundry technologies.

Abstract: A current amplifier A1 includes two transistors Q1 and Q2 whose emitters are interconnected via a resistor R1. The input of the current amplifier is constituted by the emitter of the first transistor Q1, whose collector is connected to the output terminal of the amplifier A1 via a second resistor R2, and to the first resistor R1 via the main current path of the second transistor Q2. The current amplifier A1 has a simple structure and a low input impedance, as well as an easily controllable gain.

Abstract: In a tunable recursive filter implemented in a microwave monolithic integrated circuit (MMIC), a second-order recursive filter included two first order filters, having first and second transmission lines, respectively, connected in parallel. An amplifying unit having a cascode amplifier is arranged in a forward path shared by the two first-order filters. A combiner receives an input signal and a first and second feedback signals fed back through the first and second transmission lines, respectively, and combines such signals to output a combined signal. The amplifying unit amplifies the combined signal and outputs an amplified signal. A divider divides the amplified signal from the amplifying unit, outputs a first portion of the divided signal, and feeds back a second and third portion of the divided signal through the first and second transmission lines.

Abstract: In radio receivers, ceramic filters are used for filtering the received frequency band. The limitation of the frequency band in the higher frequency range leads to an asymmetrical crosstalk between the right and left audio channel after decoding in the stereo decoder. These transmission errors are compensated by an adjustable high-pass filter. This high-pass filter precedes the stereo decoder. High-pass filters using potentiometers cannot be integrated. Furthermore, ageing phenomena occur in potentiometers so that the transfer function changes. A high-pass filter with a variable capacitor can neither be integrated easily. Therefore, an arrangement is used in which, after a first amplification of the signal to be filtered, this signal is divided into two signal currents and the amplitude and phase of a sub-current are corrected. This corrected sub-current is added to the main current at a sum node. The sub-current is applied via a voltage divider unit to an amplifier stage having a plurality of inputs.

Abstract: A frequency tracking arrangement in which a frequency tracking circuit utilizes a continuously variable analogue first order all-pass filter circuit as a controllable phase-shift element in a closed-loop system which produces a control signal to control the phase shift circuit to introduce a 90.degree. phase shift of a received reference frequency signal when the circuit is tracking that reference frequency. The control signal may then be utilized to slave the cut-off frequency of a filter and/or the delay time introduced by a delay line.

Abstract: This invention is an electronic time constant tuning circuit that uses a frequency of a clock to tune the circuit time constant. A first transconductor is used to charge a capacitor to two different voltages, each for a separate portion of a clock period. A second transconductor is used to compare the two voltages and control them to be equal by controlling the transconductance of the first transconductor. When the two voltage are equal, the resulting transconductance and the capacitance of the capacitor form the circuit time constant. The circuit time constant can readily be changed by changing the frequency of the clock. The control signal generated by the second transconductor can be applied to other transconductors in a gm-C filter to adjust the cutoff frequency of the filter when the other transconductors have a similar structure to the first transconductor.

Abstract: A tuning amplifier 1 is provided with an oscillation circuit 10 incorporating an amplifier circuit 11 and a feedback circuit 12, an input circuit 14 which inputs signals to the oscillation circuit 10, and an automatic gain control (AGC) circuit 16 which controls the output amplitude of the oscillation circuit 10. When signals are inputted to the oscillation circuit 10 through the input circuit 14, such tuning that only signals having frequencies near the oscillation frequency of the oscillation circuit 10 are allowed to pass through is possible.