Abstract: An input stage for an instrumentation system may include a resistor coupled between an input terminal and a summing node, and an amplifier arranged to maintain the voltage at the summing node. In anther embodiment, an instrumentation input system may include an input stage to receive a signal to be measured, and a variable gain amplifier having an input coupled to an output of the input stage, wherein the variable gain amplifier comprises two or more gain stages. A variable gain amplifier may include an attenuator having an input and a series of tap points and a series of low-inertia switches to steer outputs from the attenuator to an output terminal.

Abstract: High impedance, high frequency nanoscale device electronics configured to interface with low impedance loads include an impedance transforming stage constructed of multiple nanoscale devices, such as carbon nanotube field-effect transistors. In an embodiment of the present invention, an impedance transforming output stage of a multistage amplifier is configured to drive a 50 ohm transmission line with unity voltage gain using multiple carbon nanotube field-effect transistors in parallel. In a further embodiment, a receiver provided for an electronically steered receive array is a monolithic, lumped-element system formed from nanoscale devices and configured to interface with the external electrical systems via a single transmission line.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: Cascaded amplifiers with a transformer-based bypass mode are described. In an exemplary design, an apparatus includes first and second amplifiers and a circuit. The first amplifier (e.g., a driver amplifier) provides amplification in a high gain mode and a bypass mode. The second amplifier (e.g., a power amplifier) provides amplification in the high gain mode. The circuit is coupled between the first and second amplifiers and includes a transformer having (i) a primary coil coupled to the first amplifier and (ii) a secondary coil that provides an output signal in the bypass mode. The primary coil may be a load inductor for the first amplifier. The circuit may further include a series combination of a capacitor and a switch coupled in parallel with the primary coil, a switch coupled in series with the secondary coil, and/or a capacitor coupled in parallel with the secondary coil.

Abstract: Transceivers with multiple gain stages that include open loop and closed loop amplifiers are subject to differential non-linearity (DNL) errors in their total gain versus gain index curve due to the gain step variability of the open loop amplifiers. The initial and time varying DNL can be reduced by a control loop that uses the relative gain step precision of the closed loop amplifiers and of passive attenuators to establish a control loop to reduce the DNL of the total gain.

Abstract: One exemplary signal amplification circuit used for processing an input signal includes an input stage, a plurality of output stages, and a selecting stage. The input stage has an input node for receiving the input signal and an output node for outputting an intermediate signal. The output stages are coupled to a plurality of output ports of the signal amplification circuit, respectively. Each of the output stages generates a corresponding processed signal to a corresponding output port according to a gain and a signal derived from the intermediate signal of the input stage when enabled. The selecting stage is arranged for selectively coupling the output node of the input stage to at least one of the output stages.

Abstract: In one embodiment, an apparatus includes a first amplification block configured to receive a signal. A second amplification block is configured to output the signal where the outputted signal is amplified. The isolation circuit allows reuse of a current flowing through the second amplification block by coupling the current to pass through the first amplification block. Also, the isolation circuit provides isolation between the first amplification block and the second amplification block to restrict the signal from flowing through the isolation circuit.

Abstract: A reconfigurable power amplifier includes at least one amplification circuit (E1, E2), and a circuit (6) for controlling the amplification circuit so as to adapt its operation according to an applied input signal (RFin). The circuit for controlling includes a circuit (4, 5) for modifying the compression point of the amplification circuit and for adapting the gain of the amplification circuit in such a manner as to increase the power added efficiency of the circuit for the modified compression point.

Abstract: An embodiment of an amplifier circuit includes a plurality of amplifiers connected between input and output terminals to form at least partially parallel amplification paths between the terminals. A first plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common first series-connected amplifier, and a second plurality of the amplification paths have different first amplifiers. Optionally, a third plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common last series-connected amplifier, and a fourth plurality of the amplification paths have different last amplifiers. Alternatively, a first plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common last series-connected amplifier, and a second plurality of the amplification paths have different last amplifiers.

Abstract: The RF power amplifier circuit including multiple amplification stages has a previous-stage amplifier, a next-stage amplifier and a controller. The previous-stage amplifier responds to an RF transmission input signal. The next-stage amplifier responds to an amplification signal output by the previous-stage amplifier. In response to an output-power-control voltage, the controller controls the former- and next-stage amplifiers in quiescent current and gain. In response to the output-power-control voltage, the quiescent current and gain of the previous-stage amplifier are continuously changed according to a first continuous function, whereas those of the next-stage amplifier are continuously changed according to a second continuous function. The second continuous function is higher than the first continuous function by at least one in degree. The RF power amplifier circuit brings about the effect that the drop of the power added efficiency in low and middle power modes is relieved.

Abstract: A differential amplifier stage and method for offset cancellation include an amplifier having an input and an output. An internal offset cancellation circuit has an input for receiving a control signal to control offset cancellation in the amplifier. The offset cancellation circuit is integrated with the amplifier but isolated from the input and the output of the amplifier, and, in accordance with its isolation, an impedance of the stage is unaffected by the offset cancellation circuit.

Abstract: A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus comprises a driver amplifier and a power amplifier. The apparatus may further include an inter-stage matching circuit tunable in discrete steps for matching impedances between the driver amplifier and the power amplifier. The tunable inter-stage matching circuit may include a bank of capacitors, each capacitor of the bank coupled in series with a switch for coupling the capacitor to a ground voltage.

Abstract: An amplifier module with multiple operating modes is described. In an exemplary design, an apparatus includes a plurality of amplifiers. The apparatus may also include a plurality of switches, each switch coupled to an output of an associated amplifier in the plurality of amplifiers and configured to provide an amplified signal in a first mode and bypass the associated amplifier and provide an associated bypass signal in a second mode. Further, the apparatus may include an output circuit including a plurality of matching circuits, each matching circuit coupled to an associated amplifier in the plurality of amplifiers and an associated switch in the plurality of switches.

Abstract: An amplification apparatus comprising first amplification circuitry having first shunt-peak circuitry and second amplification circuitry having second shunt-peak circuitry, wherein the amplification apparatus is arranged to provide an operational bandwidth over which the first and second amplification circuitry amplify signals, and wherein the second shunt-peak circuitry is arranged to use at least part of the first shunt-peak circuitry.

Abstract: A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e.g., a driver amplifier), a second active circuit (e.g., a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors.

Abstract: A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

Abstract: A system includes an input multi-level channelizer, an output multi-level channelizer, and more than one amplifiers connected between the input and output channelizers. The input and output channelizers cover an operating frequency band. Each level of the input multi-level channelizer comprises a plurality of input channels, which may be bandpass filters, and may be grouped into input sub-channelizers. Each successive level of the input multi-level channelizer is configured to divide the incoming signals into smaller frequency bands. Each level of the output multi-level channelizer comprises a plurality of output channels, which may be bandpass filters, and may be grouped into output sub-channelizers. Each successive level of the output multi-level channelizer is configured to combine the incoming signals into larger frequency bands. The signal output from the output multi-level channelizer represents a filtered version of the signal input into the input multi-level channelizer.

Abstract: An apparatus for an improved operational amplifier. The disclosed improved operational amplifier comprises an operational amplifier, a first feedback circuit, and one or more secondary feedback circuits. The operational amplifier include a plurality of serially coupled gain stages and is configured so that an output of each gain stage drives an input of a next gain stage and an output of a last gain stage drives a load external to the improved operational amplifier. The first feedback circuit is coupled between an output of a designated gain stage and an output of a previous gain stage to provide a first feedback to the previous gain stage. Each secondary feedback circuit provides an additional feedback to the output of the previous gain stage.

Abstract: An adjustable, segmented amplifier including (i) a first fixed stage configured to amplify an analog signal in accordance with a fixed amplification, and provide the analog signal amplified in accordance with the fixed amplification to a first common node. The adjustable, segmented amplifier further includes an adjustable stage comprising a plurality of independently selectable parallel amplifier segments, wherein the adjustable stage is configured to (i) amplify the analog signal provided to the first common node in accordance with an adjustable amplification that is adjustable depending upon a number of the independently selectable parallel amplifier segments having been selected to amplify the analog signal provided to the first common node, and (ii) provide the analog signal amplified in accordance with the fixed amplification and amplified in accordance with the adjustable amplification to the second common node.

Abstract: Techniques are disclosed for extending an amplifier's linear operating range by concatenating an amplifier exhibiting gain compression with a gain expansion stage. In an exemplary embodiment, a gain expansion stage incorporates a Class-B stage, a Class-AB stage, or a combination of the two. In an exemplary embodiment, both the gain compression stage and gain expansion stage are provided with a replica current biasing scheme to ensure stable biasing current over variations in temperature, process, and/or supply voltage. Further disclosed is an output voltage biasing scheme to set the DC output voltage to ensure maximum linear operating range.

Abstract: A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

Abstract: A multistage amplifying circuit includes a first amplifying circuit that either samples a first analog voltage input or amplifies a difference between the first analog voltage and a first digital voltage converted from the first analog voltage, in response to a control signal. A second amplifying circuit either samples a second analog voltage input or amplifies a difference between the second analog voltage and a second digital voltage converted from the second analog voltage, in response to the control signal. A common amplifier receives output voltages of the first amplifying circuit and the second amplifying circuit and either resets the output voltage of the first amplifying circuit and determines an output voltage by using the second amplifying circuit, or resets the output voltage of the second amplifying circuit and determines an output voltage by using the first amplifying circuit, in response to the control signal.

Abstract: CMOS power amplifiers (PAs) are disclosed having one or more integrated one-time programming (OTP) memories that are utilized to control at least in part operation of the CMOS PAs. The integrated OTP memories within the CMOS power amplifiers (PAs) allow adjustments, such as one-time factory trimming, of CMOS PA integrated circuits to optimize or improve performance. With this capability, for example, the tuning and biasing of stages within a multi-stage amplifier within a CMOS PA can be measured during factory test and adjusted by setting one or more bits in the OTP memories, as desired. Further, the operation of other circuitry within the PA can also be controlled at least in part with parameter settings stored in the OTP memories.

Abstract: A high-efficiency power amplifier is provided, including a drive amplifier and a final power amplifier, and further including a first digital pre-distortion (DPD) correction module and a second DPD correction module. The first DPD correction module is configured to pre-distort nonlinear characteristics of drive signals output by the drive amplifier, and the second DPD correction module is connected to the first DPD correction module in series, and is configured to pre-distort nonlinear characteristics of amplified signals output by the final power amplifier. Another high-efficiency power amplifier is also provided, including a drive amplifier and a final power amplifier, and further including a second multi-path control module, a fourth DPD correction module, and a second gating module. The overall efficiency of the high-efficiency power amplifier is increased by improving the working efficiency of the drive amplifier.

Abstract: An apparatus according to an embodiment of the present invention includes a conversion unit configured to generate electric charge, a first amplification unit configured to amplify a signal corresponding to an amount of the electric charge and output a first amplified signal, a second amplification unit configured to amplify the first amplified signal and output a second amplified signal, a current source shared by the first amplification unit and the second amplification unit, and a selection unit configured to bring the first amplification unit and the second amplification unit into an inactive state. The current source is shared by the first amplification unit and the second amplification unit. The number of current sources is therefore reduced. This leads to the reduction in power consumption.

Abstract: A minimal area, power efficient, high swing and monolithic ground centered headphone amplifier circuit operable on a low voltage. An input amplifier stage includes a first input terminal and a second input terminal and having a first gain. An output amplifier stage is coupled to an output of the input amplifier stage to provide an output signal and having a second gain. A feedback network coupled between the first input terminal and the output of the output amplifier stage. A level shifting unit coupled to the first input terminal and the feedback network. A charge pump coupled to the output amplifier stage to generate a negative supply voltage and to minimize a noise associated with the negative supply voltage using a loop gain of the amplifier, wherein the loop gain is a combination of the first gain, the second gain, and a gain of the feedback network.

Abstract: According to one embodiment, a variable attenuator is arranged in an input stage, a plurality of transistors are cascaded on the later part of this variable attenuator, temperature sensors are arranged in the vicinity of two or more of the plurality of transistors to detect temperatures, the amount of gain change of the plurality of transistors is calculated from the temperature detection results individually obtained by the temperature sensors, the variable attenuator is controlled in such a manner as to reduce the amount gain change so that the input signal level can be controlled, and thereby the gain that tends to vary in accordance with temperature changes can be stabilized.

Abstract: CMOS power amplifiers (PAs) are disclosed having one or more integrated one-time programming (OTP) memories that are utilized to control at least in part operation of the CMOS PAs. The integrated OTP memories within the CMOS power amplifiers (PAs) allow adjustments, such as one-time factory trimming, of CMOS PA integrated circuits to optimize or improve performance. With this capability, for example, the tuning and biasing of stages within a multi-stage amplifier within a CMOS PA can be measured during factory test and adjusted by setting one or more bits in the OTP memories, as desired. Further, the operation of other circuitry within the PA can also be controlled at least in part with parameter settings stored in the OTP memories.

Abstract: In a current steering D/A converter, a 1LSB current source 1 and a 2LSB current source 2 are binary code current sources for outputting currents with current values weighted by ½, and a 4LSB current source 3 is one of a large number of current sources designed as thermometer code current source with the same structure. In first circuits A1, A2 and A4 for respectively determining constant current values of the current sources 1 through 3, a plurality of MOS transistors with a channel length L3 and a channel width W3 are cascode-connected to one another with gate terminals thereof shared. In second circuits B1, B2 and B4 respectively used for setting high output impedance of the current sources 1 through 3, a plurality of MOS transistors with a channel length L4 and a channel width W4 are cascode-connected to one another with gate terminals thereof shared.

Abstract: The invention relates to a feedback network (60) for cascade amplifiers (200), which comprises an active stage (30) to feed signal back to a first internal node (65) at the output of the first amplifier stage (61) of the cascade. The invention further relates to a feedback network (60) which comprises said active feedback stage (30) with said first internal amplifier node (65) connection and a feedback resistor (10) connected from said cascade amplifier output port (out) to its input port (in).

Abstract: Data transmitter embodiments are provided which are particularly useful as interface devices for accurate and reliable transmittal of data from high-speed data system devices such as analog-to-digital converters. Transmitter embodiments have been found to provide excellent fidelity of data transfer at high data rates (e.g., 4 gigabits/second) while consuming only a portion of the power of many conventional transmitters and requiring only a portion of the layout area of these transmitters. Transmitter embodiments provide effective control of transmitter parameters such as matched impedances, data symmetry, common-mode level, data eye and current drain.

Abstract: Various amplifier configurations having increased bandwidth, linearity, dynamic range, and less distortion are shown and disclosed. To increase bandwidth in a transimpedance amplifier, a replica circuit is created to replicate a degeneration resistance, or the resistance or value that relates to a feedback resistance. From the replica circuit, the replicated values are mirrored and processed to control a FET switch which modifies a degeneration resistance. The FET switch control signal is related to the feedback resistance and modifies the degeneration resistance to thereby maintain the product of the feedback resistance and the degeneration resistance as a constant. In another embodiment, a second switch controlled by an automatic gain control signal is established between a first stage amplifier and a second stage amplifier to improve dynamic range and bandwidth without degrading other amplifier specifications.

Abstract: A power amplifier system includes a first power amplifier, a second harmonic generator, a phase shifter, and first and second adders. The first power amplifier amplifies a primary input signal. The second harmonic generator outputs a second harmonic by using a split part (signal) of the primary input signal as an input. The phase shifter adjusts a phase of the second harmonic. The first adder sums together a split signal of the primary input signal and an output of the phase shifter, thereby to produce an output. The second power amplifier uses the output of the first adder as an input. The second adder sums together an output of the first amplifier and an output of the second power amplifier, thereby to produce an output.

Abstract: Embodiments of a high-frequency millimeter-wave amplifier are generally described herein. The high-frequency millimeter-wave amplifier may be constructed on a substrate to operate at a frequency of at least 75 GHz. In some embodiments, the millimeter-wave amplifier may include at least first, second, third and fourth amplifier stages coupled in series. A single drain bias bond pad provided on the substrate to provide a drain bias voltage to the drains of the first, second, third and fourth amplifier stages. Drain bias lines may be electrically coupled to the single drain bias bond pad and extend at least partially alongside and between some of the amplifier stages. A signal path through the second amplifier stage extends in a direction opposite of signal paths through the first and third amplifier stages. In some embodiments, a 95 GHz amplifier is provided and configured occupy an area on the substrate of no greater than approximately four square millimeters.

Abstract: Because of variations in open loop gain and bandwidth in successive approximate register (SAR) analog-to-digital converters (ADCs), designing amplifiers with the desired characteristics is difficult. Here, a multipath amplifier is provided that accounts for the variations in open loop gain and bandwidth. Preferably, a number of cascaded amplifiers are provided that can auto-zero to account for offset voltages so as to allow the multipath amplifier to be stable over the desired open loop gains and bandwidths.

Abstract: There is provided a wide-band amplifier circuit with improved gain flatness. The wide-band amplifier circuit includes a first resonant load unit connected to an operating power terminal, providing a preset first load, and forming a preset first resonant point, a second resonant load unit connected to the operating power terminal, providing a preset second load, and forming a second resonant point set to a frequency different from the first resonant point; a first amplification unit receiving operating power via the first load of the first resonant load unit, having an amplification band characteristic determined according to the first resonant point of the first resonant load unit, and amplifying an input signal; and a second amplification unit receiving operating power via the second load, having an amplification band characteristic determined according to the second resonant point, and amplifying an input signal from the first amplification unit.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: There is provided a power amplifier that can increase power efficiency by preventing power consumption caused by DC components from an RF input signal. A power amplifier according to an aspect of the invention may include: an inverter amplification section amplifying an input signal according to an inverter method to thereby remove DC components from the input signal; an impedance matching section matching an impedance of a transmission path of the input signal amplified by the inverter amplification section; and an amplification section amplifying an impedance-matched signal from the impedance matching section according to a gain set beforehand.

Abstract: A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

Abstract: A system for a power transmitter may be provided. The system may include a first amplifier stage having at least a first transistor and a second transistor that are connected in a first cascode configuration; a second amplifier stage having at least a third transistor and a fourth transistor that are connected in a second cascode configuration, where the first transistor receives a system input of the power transmitter, where the second transistor is connected to the third transistor, and where the fourth transistor provides a system output of the power transmitter; and a feedback network that connects a first gate or base of the fourth transistor with a second gate or base of the second transistor.

Abstract: Provided is a signal amplification apparatus with advanced linearization, the signal amplification apparatus including: a driving unit having a structure of a cascode amplifier including a first active element and a second active element and outputting an amplification signal in which an input signal is amplified, to an output terminal; a third active element receiving a signal diverged between the first active element and the second active element while gate and drain terminals of the third active element are shorted; a fourth active element of which gate and drain terminals are connected to a source terminal of the third active element; and a fifth active element of which gate terminal is connected to the drain terminal of the fourth active element, outputting a non-linear signal having an opposite phase to the amplification signal to the output terminal so as to cancel a third-order inter-modulation distortion component included in the input signal.

Abstract: A minimal area, power efficient, high swing and monolitihic ground centered headphone amplifier circuit operable on a low voltage. An input amplifier stage includes a first input terminal and a second input terminal and having a first gain. An output amplifier stage is coupled to an output of the input amplifier stage to provide an output signal and having a second gain. A feedback network coupled between the first input terminal and the output of the output amplifier stage. A level shifting unit coupled to the first input terminal and the feedback network. A charge pump coupled to the output amplifier stage to generate a negative supply voltage and to minimize a noise associated with the negative supply voltage using a loop gain of the amplifier, wherein the loop gain is a combination of the first gain, the second gain, and a gain of the feedback network.

Abstract: A power amplifier includes: a semiconductor substrate; a preceding-stage amplifying device on the semiconductor substrate, amplifying an input signal; a following-stage amplifying device on the semiconductor substrate, amplifying an output signal of the preceding-stage amplifying device; and an inter-stage matching circuit connecting the preceding-stage amplifying device to the following-stage amplifying device. The preceding-stage amplifying device has a first field effect transistor; the following-stage amplifying device has a heterojunction bipolar transistor; and the inter-stage matching circuit has a capacitance galvanically separating the output terminal of the preceding-stage amplifying device from the input terminal of the following-stage amplifying device.

Abstract: An RF amplification device has amplification elements which amplify a radio frequency input signal in wireless radio communication. Transmission line transformers are coupled to one of an input electrode and an output electrode of the amplification elements and have a main line Lout arranged between the input and the output, and a sub line Lin1 arranged between an AC ground point and one of the input and the output and coupled to the main line Lout. By applying an operating voltage different from the ground voltage level to the AC ground point, the operating voltage is supplied to the output electrodes of the amplification elements via the sub line from the AC ground point. In realizing a high-performance load circuit in an RF amplification device, it is possible to avoid increase of a module height of an RF module.

Abstract: A two stage amplifier with an inter-stage matching network constituted of a first and a second transistor forming a differential first stage, a third and a fourth transistor forming a differential second stage, an on-chip connection path connecting the emitters of the first and second transistor to the emitters of the third and fourth transistors, a first transformation network and a second transformation network. A collector of the first transistor is operatively connected to a base of the third transistor by the first transformation network and a collector of the second transistor is operatively connected to a base of the fourth transistor by the second transformation network. At least one resistor is provided in the on-chip connection path to stabilize the input of the third and fourth transistors.

Abstract: A radio frequency power amplifier has first and second amplifier stages coupled in series, one of which is operated in class F and the other is operated in inverse class F; an envelope detector adapted to detect an envelope of the input signal; a power supply coupled to supply an electrical supply voltage to the first and second amplifier stages, wherein the electrical supply voltage is controlled to follow the envelope of the input signal. Such amplifier makes it possible to maintain class F and inverse class F operation, respectively, of the first and second amplifier stages independent on the input signal. Preferably, this is done by controlling the electrical supply voltage so that the saturation levels of the first and second amplifier stages follow the envelope of the input signal.

Abstract: This disclosure relates to maintaining constant gain within multi-stage amplifiers.

Abstract: A multi-stage amplification type class-AB operational amplifier disclosed includes an amplification stage having plural amplification sections formed in multiple stages, and a class-AB output stage having a bias section and an output section, in which an input signal input to the amplification stage is sequentially amplified by the plural amplification sections, and further amplified by the bias section and the output section of the class-AB output stage. A positive supply voltage applied to the amplification stage is different from a positive supply voltage applied to the class-AB output stage, and a negative supply voltage applied to the amplification stage is different from a negative supply voltage applied to the class-AB output stage.

Abstract: The present invention relates generally to an operational amplifier. In one embodiment, the present invention is an operational amplifier including a transimpedance input stage, the transimpedance input stage including a first stage connected to a first resistor and a second resistor, and an output stage connected to the transimpedance input stage.

Abstract: A power amplifier includes: a distortion compensating circuit that causes a bias circuit to have an output impedance so that a subsequent block bipolar transistor for signal amplification-use has a maximized saturated output power; and a distortion compensating circuit that causes a bias circuit to have an output impedance so that a distortion of an output power of the power amplifier 1 with respect to an input power is canceled by a distortion characteristic of an output power with respect to an input power of the subsequent block bipolar transistor for signal amplification-use which has a maximized saturated output power and a distortion characteristic of an output power with respect to an input power of the preceding block bipolar transistor for signal amplification-use. This makes it possible to provide a power amplifier that allows reduction in saturated output power brought by realization of a highly efficient low-distortion power amplifier.