Abstract: An external audio signal is input to an input terminal which is connected to the first terminal of a first resistor. The first terminal of a second resistor is connected to the second terminal of the first resistor. An operational amplifier is arranged such that its inverting input terminal is connected to the second terminal of the second resistor, and a reference voltage is applied to its non-inverting input terminal. A third resistor is arranged between the output terminal and the inverting input terminal of the operational amplifier. A first diode is arranged between the second terminal of the first resistor and a power supply terminal such that its cathode is on the power supply terminal side. Furthermore, a second diode is arranged between the second terminal of the first resistor and the ground such that its cathode is on the second terminal side of the first resistor.

Abstract: A circuit for single ended to differential conversion is disclosed. The circuit comprises a source for providing a single ended signal; and a transformer for receiving the single ended signal. The transformer includes first and second inductors. The first and second inductors are mutually coupled. When the operating frequency changes, a phase difference of currents flowing through the inductors changes, and therefore a phase difference between effective impedance of the first and second inductors changes to maintain a substantially 180 degree phase difference due to the mutual coupling.

Abstract: This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias conditions in cell array improves over the critical concern of punch-through issue when cell is migrating to the more advanced technology node of next generation. The invention adopts a novel preferable symmetrical 2T-string NOR flash cell. Each NAND or NAND like cell of this 2T-string NOR cell is to store 2 bits and is preferable to be made of N-channel device. The cell is preferable to use Fowler-Nordheim Tunneling scheme for both erase and program operations- The invention is to provide a novel 2T-string NOR flash cell structure made of N-channel device offering most flexible erase sizes in unit of byte, page, sector, block and chip with the least program and erase disturbances.

Abstract: Aspects of the present invention provide apparatuses and methods to provide slew rate enhancement during an initial stage of operation of an amplifier and processing of an input signal with low noise introduction during a subsequent amplification stage of operation. During the initial stage, a high bandwidth component of the amplifier can be engaged to provide slew rate enhancement of the overall amplifier. The adaptive slew rate enhancement can be based on a detected imbalance of an output of a low bandwidth component of the amplifier. Once a desired operating state of the amplifier is achieved, the high bandwidth component can be disengaged. The low bandwidth component can then solely operate on a received input signal during the amplification stage. The low bandwidth component can be low power and can introduce low levels of noise, thereby ensuring minimal noise introduction and corruption of the amplified output signal of the amplifier.

Abstract: A reconfigurable amplifier comprising a first operational amplifier having two inputs and an output. A second operational amplifier having two inputs and an output. A plurality of switches coupled to the two inputs and the output of the first operational amplifier and the two inputs and the output of the second operational amplifier, wherein a first configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as an inverting differential input amplifier, and wherein a second configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as a non-inverting differential input instrumentation amplifier.

Abstract: A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.

Abstract: Compensation methods and systems for voltage-feedback amplifiers provide improved dynamic performance (i.e., increased bandwidth and the elimination or alleviation of a slew limitation) at high gains by direct feedback of an AC signal (i.e., an intermediate voltage) to an amplifier input without being attenuated by feedback resistor network.

Abstract: Embodiments of the present invention provide a sample and hold amplifier that provides a preamplifier with a multi-stage zeroing architecture. The multi-stage architecture reduces effects of parasitic capacitance exponentially over prior attempts, which yields increased accuracy.

Abstract: A reference potential converter circuit comprises: a first resistor (resistance value R1) serving as a feedback resistor for an operational amplifier; a second resistor (resistance value R2) connected to the first resistor and a reference voltage; and a third resistor (reference value R3) and a fourth resistor (reference value R4) connected between a power supply and ground. A difference voltage between Vout and Vref is divided by an R1/R2 ratio and applied to an inverting input terminal of the operational amplifier. A power supply voltage is divided by an R3/R4 ratio and applied to a non-inverting input terminal of the operational amplifier. The R1/R2 ratio and the R3/R4 ratio are equal.

Abstract: A power amplifying circuit includes first and second operational amplifiers. The power amplifying circuit includes first to fourth feedback resistor. The power amplifying circuit includes a fully differential operational amplifier that is connected to the output terminal of the first operational amplifier at a non-inverting input terminal thereof, to the output terminal of the second operational amplifier at an inverting input terminal thereof, to a first signal output terminal at a non-inverting output terminal thereof, and to a second signal output terminal at an inverting output terminal thereof and maintains a constant differential gain. The power amplifying circuit includes a switching circuit. The power amplifying circuit includes first and second input resistors. The power amplifying circuit includes a midpoint potential controlling circuit that monitors a power supply voltage and controls the switching circuit.

Abstract: When a time difference is amplified by a time difference amplifier, slew rates of internal output voltages are changed according to a phase combination of digital input signals so that a time gain is determined by a ratio between the slew rates and the slew rates can be controlled from an outside. After a voltage is charged to the level of a power supply voltage in first and second charging capacitors, the charged voltage of the first charging capacitor is decreased with a first slew rate when a first digital input signal transitions, and both charged voltages of the first and second charging capacitors are decreased with a second slew rate when a second digital input signal transitions so that both first and second digital input signals are changed from initial phases, while being compared with a reference voltage to generate first and second digital output signals.

Abstract: The invention provides a laser light detection circuit that prevents a peak output occurring when the circuit switches between the operation stop mode and the operation mode so as to prevent the breakdown or malfunction of the next-connected circuit. A laser light detection circuit has a differential amplifier that amplifies and outputs a signal corresponding to the intensity of laser light, a drive transistor having a base to which the output of the differential amplifier is applied, a second constant-current source connected to the emitter of the drive transistor, an output transistor having a base connected to the emitter of the drive transistor, a bypass transistor connected between the emitter of the drive transistor and the ground, and a control circuit. The control circuit forms a bypass current route from the second constant-current source to the ground through the bypass transistor by turning on the bypass transistor when the circuit switches from the operation stop mode to the operation mode.

Abstract: A receiving apparatus in a wireless communication system includes: an antenna configured to receive a wireless frequency signal including a first frequency band signal and a second frequency band signal; a low noise amplifier (LNA) configured to amplify the wireless frequency signal, output the first frequency band signal as a differential phase signal, and output the second frequency band signal as a common phase signal; a differentiator configured to pass only the differential phase signal between the signals outputted from the LNA; and a combiner configured to pass only the common phase signal between the signals outputted from the LNA.

Abstract: A signal amplifier circuit for USB port includes a USB controller, an amplifier circuit, a USB port and a signal regulator circuit. The USB controller includes a super speed transmitter differential pair and a super speed receiver differential pair. The amplifier circuit includes two first input terminals, two second input terminals, two first output terminals, and two second output terminals. The USB port includes two first differential signal receiving terminals and two first differential signal transmitting terminals. The super speed transmitter differential pair and the super speed receiver differential pair are electrically connected to the first input terminals and the second output terminals. The first output terminals and the second input terminals are electrically connected to the first differential signal receiving terminals and the first differential signal transmitting terminals. The signal regulator circuit regulates amplitude and jitter of differential signals amplified by the amplifier circuit.

Abstract: An amplifier having an inverting input and a non-inverting input; a capacitor coupled to inverting input of the amplifier; an input voltage conveyance control circuit, having a first switch and a second switch, the first switch coupled to the capacitor, and the second switch coupled to the non-inverting input of the amplifier; a reference voltage conveyance control circuit having a third switch and a fourth switch, a shared node coupled between third switch and fourth switch, the fourth switch coupled to the non-inverting input of the amplifier; a fifth switch coupled to an output of the amplifier; a leakage control circuit having a sixth switch and seventh switch, the sixth switch coupled between the inverting amplifier input and the fifth switch, the seventh switch coupled to the sixth switch and the capacitor; and a first resistor coupled from the output of the amplifier to the first switch.

Abstract: A signal level conversion circuit 1 includes a first differential amplifier circuit 10 and a second differential amplifier circuit 20. The first differential amplifier circuit 10 multiplies a potential difference between a first input signal and a second input signal by G1 thereby providing an output signal. The second differential amplifier circuit 20 multiplies a potential difference between the output signal of the first differential amplifier circuit 10 and the second input signal by G2 thereby providing an output, where the two gains satisfy the relation of G1×G2<0 and 0<?(G1+1)×G2<2.

Abstract: A differential amplifier replicates the input stage and cross-connects the inputs, so that the input-to-output delay will be balanced in an averaged sense. The outputs of each of the two input stages are then summed after an open loop delay matched inversion has taken place. The result is a reduction in the duty cycle distortion of the receiver amplifier over process voltage and temperature (PVT) variation. This is enabled by the fact that a full swing CMOS delay cell can be made to have good delay matching over PVT, whereas the input stage to a differential amplifier may, depending on architecture, have poor delay matching because of impedance mismatches within the amplifier.

Abstract: A power amplifier device includes an input terminal for a RF input signal. The power amplifier device includes an output terminal a RF output signal. The power amplifier device includes a first power amplifier connected to the input terminal, amplifies the RF input signal with a first gain, and outputs a first amplified signal. The power amplifier device includes a second power amplifier that amplifies a signal on the basis of the first amplified signal and outputs a second amplified signal with a second gain. The power amplifier device includes a low-pass filter or a band-pass filter that filters the second amplified signal. The power amplifier device includes an amplitude comparator to compare the first amplitude of the first comparison signal generated from the RF input signal with the second amplitude of the second comparison signal generated from the filtered signal and to output an amplitude comparison signal.

Abstract: The invention relates to amplifiers and in particular, to a transimpedance amplifier for high rate applications. Disclosed is a two stage transimpedance amplifier having a first stage comprising an amplifier and a load and a second stage comprising an amplifier and a resistor. Negative feedback is provided through a feedback resistor. Only two voltage conversions occur which reduces phase distortion, as compared to three stage transimpedance amplifiers which perform 3 voltage conversions.

Abstract: An output circuit of a charge mode sensor includes a second resistor and an operational amplifier. The second resistor connects an output portion of the charge mode sensor and a ground. The operational amplifier is configured to output a detection signal that varies in accordance with an amount of charge kept in the charge mode sensor. The operational amplifier includes an inverting input portion, a non-inverting input portion, and an output portion. The inverting input portion is connected to the output portion of the charge mode sensor via a sensor cable. The non-inverting input portion is connected to a reference voltage. The output portion is connected to the inverting input portion via a first resistor.

Abstract: An amplifier is arranged to receive an input signal and provide an output signal in response, and includes a main amplifier core and an auxiliary circuit. The main amplifier core includes an input node, an output node and a sum node with the input node coupled to the input signal, and is arranged to provide an interior signal to the sum node and output the output signal at the output node in response to signals provided to the sum node. The auxiliary circuit is coupled between the input node and the sum node, and is arranged to match an impedance of the input node and provide a cancelling signal to the sum node in response to the input signal. An associated receiver is also disclosed.

Abstract: An error amplifier, a controller using the error amplifier, and a primary-side feedback controlled AC/DC converter using the controller are discussed. When the output voltage of the primary-side feedback controlled AC/DC converter according to present invention changes, the alternating current path enjoys a fast response and adjusts the output voltage quickly with a lower precision, avoiding large voltage fluctuate, then the direct current path functions slowly to reduce equivalent output error. In such a way, the output voltage precision is enhanced while the stability of the primary-side feedback controlled AC/DC converter is maintained.

Abstract: According to one embodiment, a light receiving circuit includes a light receiving element, an amplifier, and a first compensator. The light receiving element is configured to output an optical current by receiving an optical signal. The amplifier is configured to convert the optical current into a voltage and amplify the voltage. The first compensator is connected to the amplifier and configured to suppress a variation in an opposite direction from a voltage variation of the amplifier when the optical current increases.

Abstract: Described is an inductive compensating network coupled between the differential inputs of an operational amplifier circuit. The inductive compensating network includes at least one inductive element having an inductance value selected so as to provide proper compensation of the operational amplifier circuit. Also described is a feedback compensation scheme which adjusts loop characteristics by introducing zeros into a system with the addition of inductive or capacitive elements in a feedback path.

Abstract: A radio apparatus capable of correcting a direct current offset with high accuracy in a short time is provided. A radio apparatus according to an embodiment includes a first amplifier amplifying a signal inputted to an input terminal with amplification gain determined by a variable resistor to generate a first amplified signal, and a second amplifier amplifying the first amplified signal to generate a second amplified signal. Further, the radio apparatus includes a first correcting unit correcting a direct current offset of the first amplifier, and a second correcting unit correcting a direct current offset of the second amplifier.

Abstract: An operational amplifying device comprises an input stage and an output stage. The input stage receives and processes an input voltage to output an amplified voltage. The output stage is electrically connected to the input stage in series. The output stage comprises a first switch and a second switch. The first switch is configured to turn on for transferring the amplified voltage. The second switch is connected in parallel with the first switch and is configured to turn on for transferring the amplified voltage. The second switch is turned off when the first switch is turned on such that the amplified voltage is transferred through the first switch to the first resistor array for gamma correction.

Abstract: A differential amplifier comprises a first amplifier (A1) with a signal input (Inp) and a signal output (Out1) that is fed back to a first feedback input (In1) of the first amplifier (A1) and is also connected to a first output (outp) of the differential amplifier. Furthermore, a buffer circuit (Buff) is connected to the first output (outp). A nonlinear resistor circuit (Rnl1, Rnl2) is coupled via a first output node (Vmid1) with the first output (outp) and via a second output node (Vmid2) with the buffer circuit (Buff).

Abstract: A system and method for analyte measurement is provided. The system includes: a transimpedance amplifier including: at least one operational amplifier including a first input coupling to a reference voltage, a second input coupling to a sensor for sensing the analyte, and an output; and at least one passive circuit element having a first terminal and a second terminal, the first terminal of the at least one passive circuit element coupling to the second input of the at least one operational amplifier, and a circuit for adjusting a gain of the transimpedance amplifier for the measurement of the analyte.

Abstract: Techniques are disclosed for canceling an offset component (e.g., dc component or dc offset) in an amplifier circuit. For example, an apparatus comprises an amplifier circuit with an amplifier element and a feedback resistor network coupled between an output of the amplifier element and an input of the amplifier element. The apparatus also comprises a current source coupled to the feedback resistor network, the current source generating a current signal that generates a voltage in a first portion of the feedback resistor network that cancels an offset component present in an input signal received by the amplifier circuit. A second portion of the feedback resistor network may be adjustable so that a gain applied to the input signal is adjustable while the offset component is canceled from the input signal. One or more resistors in the feedback resistor network may be composed of the same or substantially similar material as one or more resistors associated with the current source.

Abstract: A chopper comprises a differential difference amplifier, a first switch, and a second switch. The differential difference amplifier comprises a first input stage and a second input stage. The first input stage comprises a non-inverting input terminal and an inverting input terminal. The second input stage comprises a non-inverting input terminal and an inverting input terminal. The first switch is operable to receive a first input voltage and a second input voltage and selectively transfer the first input voltage to one of the non-inverting input terminal of the first input stage and the non-inverting input terminal of the second input stage. The second switch is operable to receive a third input voltage and a fourth input voltage and selectively transfer the third input voltage to one of the inverting input terminal of the first input stage and the inverting input terminal of the second input stage.

Abstract: An input stage for an instrumentation system may include a resistor coupled between an input terminal and a summing node, and an amplifier arranged to maintain the voltage at the summing node. In anther embodiment, an instrumentation input system may include an input stage to receive a signal to be measured, and a variable gain amplifier having an input coupled to an output of the input stage, wherein the variable gain amplifier comprises two or more gain stages. A variable gain amplifier may include an attenuator having an input and a series of tap points and a series of low-inertia switches to steer outputs from the attenuator to an output terminal.

Abstract: A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain.

Abstract: An adjustable gain audio power amplifying circuit includes an input unit, an audio amplifying unit connected to the input unit, a gain adjusting unit connected to the audio amplifying unit, a controlling unit connected to the gain adjusting unit, a comparing unit connected between the gain adjusting unit and the controlling unit and an output unit connected to the audio amplifying unit. The comparing unit compares an outputted signal of the output unit with a common-mode reference voltage, outputs a gain adjustment controlling signal and sends the gain adjustment controlling signal into the controlling unit. When the outputted signal equals the common-mode reference voltage, the gain adjustment controlling signal turns over and then the controlling unit detects the turnover and sends a received gain adjustment signal into the gain adjusting unit. Based on the received gain adjustment signal, the gain adjusting unit controls gains of the adjustable gain audio power amplifying circuit.

Abstract: An apparatus for equalizing channels is provided, which is generally transparent to link training. The apparatus generally includes equalization paths formed by an input circuit, a crossbar, and an output circuit and a controller. Each equalization path is coupled to at least one of the channels, and a controller has a VGA loop, a crossbar loop, and a driver loop. The AGC loop receives a first reference voltage and provides a gain control signal to the input circuit, and the gain control network comprises a replica of at least one of the equalization paths. The crossbar loop receives a second reference voltage and provides a crossbar control signal to the crossbar. The driver loop receives a third reference voltage and provides a driver control signal for the output circuit.

Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, an amplifier includes a first adaptive level shifter (ALS), a second ALS, a first transconductance amplification circuit, a second transconductance amplification circuit, and a transimpedance amplification circuit. The first ALS and the second ALS are electrically coupled to the first and second transconductance amplification circuits to improve the input voltage range and common-mode rejection ratio (CMRR) of the amplifier. The transimpedance amplification block is electrically coupled to the first and second transconductance amplification blocks and generates an output voltage of the amplifier. The first ALS receives a differential input voltage, and the second ALS is configured to receive a feedback signal configured to change in relation to the output voltage signal.

Abstract: This application reduces the power of series combined transformers and of parallel combined transformers while maintaining efficiency. In one embodiment, a series combined transformer is provided with a switch between a first primary inductor and a second primary inductor, in order to provide at least two modes. In a high power mode, the switch is open and the series combined transformer operates normally. In a low power mode, the switch is closed, one amplifier from a first differential amplifier pair is shut down, one amplifier from a second differential pair is shut down, and the series combined transformer operates efficiently in a low power mode.

Abstract: A reconfigurable amplifier comprising a first operational amplifier having two inputs and an output. A second operational amplifier having two inputs and an output. A plurality of switches coupled to the two inputs and the output of the first operational amplifier and the two inputs and the output of the second operational amplifier, wherein a first configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as an inverting differential input amplifier, and wherein a second configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as a non-inverting differential input instrumentation amplifier.

Abstract: A multilevel class-D differential amplifier which can be operated in at least three modes includes a first power stage and a second power stage. In an idle mode, an output of the first power stage varies between a first voltage level and a second voltage level, wherein an output of the second power stage varies between the first voltage level and the second voltage level. In a PWM mode, the output of the first power stage varies between the first voltage level and the second voltage level, wherein the output of the second power stage varies between the first voltage level and the second voltage level. In a Multi-Level mode, the output of said first power stage varies between said second voltage level and a third voltage level, wherein said output of said second power stage is fixed at said first voltage level, and wherein said differential signal between said outputs of said power stages is pulse width modulated.

Abstract: An operational amplifier includes an input differential stage having one external input receiving an external input voltage and two outputs; and two output stages. A switch section is provided between inputs of the two output stages and the two outputs of the input differential stage, and is configured to alternately connect the two outputs of the input differential stage and inputs of a positive-only output stage of the two output stages; and the two outputs of the input differential stage and inputs of a negative-only output stage of the two output stages.

Abstract: An electronic circuit includes a band-gap reference circuit and a start-up circuit. The band-gap reference circuit includes an operational amplifier which has an output and first and second inputs. The band-gap reference circuit is configured to generate a predetermined reference voltage at the output of the operational amplifier after a start-up phase of the band-gap reference circuit. The start-up circuit includes at least one switch arranged to connect at least one current source to at least one of the inputs of the operational amplifier during the start-up phase, and to disconnect the at least one current source from the at least one of the inputs of the operational amplifier after the start-up phase.

Abstract: A voltage level shifter for a direct coupling of an external voltage source to a common mode of a circuit may include an amplifier, a voltage-controlled current source, a first and second resistors. A first input of the amplifier may be connected to the common mode. A second input of the amplifier may, via the first and second resistors, receive a voltage indicative of the external voltage source. The output of the amplifier may indicate a voltage difference between the first and second inputs. The voltage-controlled current source may be controlled by the voltage difference to supply a current to a common node of the first and second resistors so that the voltage difference between the first and second inputs may be minimized.

Abstract: According to example embodiments, an image sensor includes a charge sensing amplifier configured to amplify charges sensed by a sensing unit. The charge sensing amplifier includes an input terminal, an amplification terminal, an output terminal, a first capacitor connected between the input terminal and the amplification terminal, a first switch connected between the input terminal and the amplification terminal, a second capacitor connected between the amplification terminal and the output terminal, and a second switch connected between the output terminal and a reference voltage terminal.

Abstract: A trans-impedance amplifier (TIA) for a light-receiving circuit is disclosed where the TIA reduces the power consumption as suppressing the degradation of the signal quality in high frequency regions. The TIA comprises a primary core, a dummy core, and a differential amplifier that receives each output of two cores in the differential mode. Two cores have an arrangement substantially same to each other except that the power consumption thereof is smaller in the dummy core. Because the output impedance of two cores becomes substantially equal, the scattering parameter of the common mode to the differential mode at the output of the primary core becomes small enough.

Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, an amplifier includes a first adaptive level shifter (ALS), a second ALS, a first transconductance amplification circuit, a second transconductance amplification circuit, and a transimpedance amplification circuit. The first ALS and the second ALS are electrically coupled to the first and second transconductance amplification circuits to improve the input voltage range and common-mode rejection ratio (CMRR) of the amplifier. The transimpedance amplification block is electrically coupled to the first and second transconductance amplification blocks and generates an output voltage of the amplifier. The first ALS receives a differential input voltage, and the second ALS is configured to receive a feedback signal configured to change in relation to the output voltage signal.

Abstract: An vector modulator using a time delay and a phase shifter is disclosed, the vector modulator including a time delay (110) varying a phase of an input signal by time-delaying the input signal; a first coupler (120) converting the signal outputted in changed phase through the time delay to an I channel signal and a Q channel signal each having a 90° phase difference and outputting the I/Q channel signals; a first phase shifter (130) varying the phase of the I channel signal outputted from the first coupler within a predetermined phase range and outputting the phase-variable I channel signal; a second phase shifter (140) varying the Q channel signal outputted from the first coupler within a predetermined phase range and outputting the phase-variable Q channel signal; and a second coupler (150) coupling phase-variable I/Q channel signals and outputting the coupled signals.

Abstract: This disclosure describes at least one class AB amplifier output stage circuit arrangement that can operate at low supply voltages, with minimum current generated. Furthermore, at least one class AB amplifier stage circuit arrangement described herein reacts favorably to a supply voltage, that is, exhibits a good power supply rejection ratio. Moreover, this disclosure describes class AB amplifier output stage circuit arrangements that include a negative channel metal oxide semiconductor (NMOS) transistor current mirror arrangement and a positive channel metal oxide semiconductor (PMOS) transistor current mirror arrangement. In some implementations, a monitoring circuit may be coupled to a class AB amplifier output stage circuit arrangement to offset mismatch that may occur in the class AB amplifier output stage.

Abstract: A capacitive sensor system and method resistant to electromagnetic interference is disclosed. The system includes a capacitive core, differential amplifier with inverting and non-inverting inputs, capacitive paths, and chopping system. Core can include inputs and outputs coupled to variable capacitors, and common nodes coupling variable capacitors. Capacitive paths couple core outputs to amplifier inputs. When chopping system is high, one polarity voltage is applied to core inputs, a first core output is coupled to the inverting input and a second core output is coupled to the non-inverting input. When the chopping system is low, opposite polarity voltage is applied to core inputs, and core output to amplifier input couplings are flipped. Capacitive paths can include bond wires. Chopping system can be varied between high and low at frequencies that smear noise away from a frequency band of interest, or that smear noise substantially evenly across a wide frequency range.

Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network. computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

Abstract: Apparatus and methods reduce the likelihood of amplifier saturation due to propagated DC offsets, and reduce the recover from saturated stated when such saturation occurs. Advantageously, these attributes are beneficial for monitoring of bioelectric signals. A circuit uses an instrumentation amplifier connected as a high pass filter to attenuate large DC offsets and amplify small signals. The circuit can include an instrumentation amplifier electrically coupled with a first feedback circuit including at least one resistor and a second feedback circuit including an op-amp. The feedback circuit can also include a low-pass filter. The op-amp in the second feedback circuit can be configured as a non-inverting amplifier, an inverting amplifier, and/or an integrator circuit. Alternatively, the circuit can include an instrumentation amplifier with one feedback circuit including at least one resistor, and a coupling capacitor electrically coupled with a reference voltage.

Abstract: This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias conditions in cell array improves over the critical concern of punch-through issue when cell is migrating to the more advanced technology node of next generation. The invention adopts a novel preferable symmetrical 2T-string NOR flash cell. Each NAND or NAND like cell of this 2T-string NOR cell is to store 2 bits and is preferable to be made of N-channel device. The cell is preferable to use Fowler-Nordheim Tunneling scheme for both erase and program operations- The invention is to provide a novel 2T-string NOR flash cell structure made of N-channel device offering most flexible erase sizes in unit of byte, page, sector, block and chip with the least program and erase disturbances.