Abstract: An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used as a rough frequency reference to determine, for an externally-provided frequency reference signal, which of a finite number of discrete frequencies is currently received. The VCO has a frequency range which varies less, as a percentage, than the ratio between possible reference frequency values. Consequently, the VCO is used as a frequency reference to measure the frequency reference signal. An internal signal is generated to indicate to remaining circuitry which of the possible reference frequencies is actually being provided, without requiring use of any dedicated input pins to receive a select signal. An integrated circuit device may be configured for different modes of operation as a function of which reference frequency is provided to the device.

Abstract: A modification of the synchronous oscillator is described, having regenerative positive feedback. The circuit includes an amplifier, a high-Q tank circuit, and a conventional synchronous oscillator feedback network. An additional feedback path provides a negative impedance conversion effect.

Abstract: A method and apparatus are provided for reducing a startup interval of a temperature controlled crystal oscillator chip. The method includes the steps of connecting an operating circuit of the temperature controlled crystal oscillator chip into a first configuration to reduce the startup interval following application of power and reconnecting the operating circuit into a second configuration after a predetermined time period.

Abstract: A gated oscillator is provided for digital circuits. The gated oscillator is achieved by the unconventional use of controlling the operating point of a Van der Pol oscillator. Oscillations are achieved by Van der Pol self-oscillation behavior.

Abstract: A noise elimination circuit which can eliminate all noise of a reset signal of a microprocessor or an input signal effective in a specific logic level comprises: a ring oscillator unit for receiving first and second signals and generating a pulse signal according to the first signal, and stopping generation of the pulse signal when the first and the second signals have a first potential level; and a frequency division unit for receiving an output signal of the ring oscillator unit and then, N times frequency-dividing to generate the signal to the second signal, and being reset by the first signal.

Abstract: A real-time clock circuit for saving real time information during removal of a battery is presented. The battery provides power to the clock circuit during a steady-state mode. The clock circuit includes an oscillator assembly for generating a periodic waveform. A counter accumulates real time information in response to the periodic waveform. An energy storage device is coupled to the counter to supply energy to the counter while the battery is removed. A switch is coupled between the battery and the energy storage device to prevent the energy storage device from supplying energy to components other than the counter during removal of the battery. The switch provides a path for energy to flow from the battery to the energy storage device, thereby charging the energy storage device.

Abstract: A microcontroller is disclosed that includes a crystal oscillator circuit that is programmable to provide multiple different levels of startup current. In the present embodiment, the crystal oscillator circuit includes logic devices for receiving programming indicating one of a plurality of different startup current levels and a resistor chain. The logic devices are coupled to the resistor chain for controlling the resistance of the oscillator circuit such that, upon receiving programming indicating a particular startup current level, the crystal oscillator circuit generates a corresponding startup current. In addition, the crystal oscillator circuit includes provision for selecting one of a plurality of different levels of capacitance. Furthermore, the crystal oscillator circuit includes a pass gate that includes circuitry for assuring predetermined startup conditions are met. A feedback loop that includes an amplifier provides for steady-state operations that have low power consumption.

Abstract: Resuming the operation of a phase locked loop (PLL) that has entered a hang up status. The output of the PLL is examined to determine whether the output is stuck at either high or low logical value. The PLL is initialized if the output is stuck. Once initialized, the PLL may resume generating a desired output clock signal.

Abstract: An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.

Abstract: In a semiconductor integrated circuit, a selector 1 selects a signal FB at the input thereof by giving a proper level to a signal EN. By setting two-phase scan clocks SC1, SC2 of F/F 2,4 so that F/F 2,4 are set to the through state, a signal can be passed from F/F 2 to F/F 4 under a through state in the above circuit. Further, there can be fabricated a critical path-ring oscillator which is self-oscillated in the critical path by negatively feeding back the output of F/F 4 to F/F 2 through the signal FB. The logic in the ring is required to be an inverted logic. In a test other than a speed screening test or at the normal operation time, a proper level is given to the signal EN so that the selector 1 is switched to select the input side, thereby cutting a negative feedback path through which the output of F/F 4 is negatively fed back to F/F2.

Abstract: A digitally controlled oscillator includes an adjustable signal generating circuit adapted to generate an oscillation signal. A feedback loop receives the oscillation signal from the adjustable signal generating circuit. The feedback loop detects error in the oscillation signal and produces an error signal based on the error. The control logic circuit receives the error signal from the feedback loop and maintains the oscillation signal within a predetermined error range. Also, a state device that is connected to the adjustable signal generating circuit maintains a previous operating state of the adjustable signal generating circuit when the digitally controlled oscillator is temporarily powered down.

Abstract: The problem of undesired power consumption in an oscillator during “stop” periods of a device is addressed by providing the oscillator in apparatus external to the device, the apparatus including a current sensor sensing current in a line between the apparatus and the device, the line communicating an oscillator “clock” signal. If the device enters a “stop” state the current flow during certain half-cycles of the oscillation is relatively low compared to the current flow in the “no-stop” state. In response to the relatively low current, the apparatus halts oscillation. Later, when the device exits the “stop” state, current flow increases in the line, and the apparatus resumes oscillation, thereby resuming the communication of the clock signal to the device.

Abstract: A ring oscillator, such as a bipolar ring oscillator with enhanced, fast startup and shutdown includes a series of a plurality of inverting differential stages connected in a loop. The plurality of inverting differential stages includes a first multiplexer stage. The first multiplexer stage includes a first signal input, a second signal input and a select input. An oscillator feedback signal is applied to the first signal input of the first multiplexer stage. A startup circuit is coupled to the first multiplexer stage. The startup circuit includes a differential signal coupled to the second signal input of the first multiplexer stage for starting the bipolar ring oscillator. The startup circuit applies a full differential switching voltage signal to the second signal input of the first multiplexer stage to guarantee start of the bipolar ring oscillator after one delay of the series of the plurality of inverting differential stages connected in the loop.

Abstract: The invention relates to a controlling equipment for properly maintaining a length of a period where an oscillator is to operate and also relates to a radio equipment incorporating such a controlling equipment. The oscillator is to supply a predetermined signal to a circuit that intermittently operates. A length of time, which is between a first instant and a second instant when the oscillator and the circuit are to initiate operation, respectively, is varied in accordance with a length of time from an initiation of operation of the oscillator to an output signal of the oscillator satisfying a predetermined condition. In an equipment or a system to which the invention is applied, it is possible to flexibly adapt to deviation or fluctuation in its characteristics and to reduce the power consumption.

Abstract: A network of localizers determines relative locations in three-dimensional space to within 1 cm by measuring propagation times of pseudorandom sequences of electromagnetic impulses. The propagation time is determined from a correlator which provides an analog pseudo-autocorrelation function sampled at discrete time bins. The correlator has a number of integrators, each integrator providing a signal proportional to the time integral of the product of the expected pulse sequence delayed by one of the discrete time bins, and the non-delayed received antenna signal. Using pattern recognition the arrival time of the received signal can be determined to within a time much smaller than the separation between bins. Because operation of standard CMOS circuitry generates noise over a large frequency range, only low-noise circuitry operates during transmission and reception. A stage in the low-frequency clock uses low-noise circuitry during transmissions and receptions, and standard circuitry at other times.

Abstract: The invention relates to a microwave pulse generator for generating microwave pulses with a pulse duration in the nanosecond range. The microwave pulse generator includes a pulse generator for generating control pulses of a constant pulse duration and a microwave oscillator generating microwave oscillations. The microwave oscillator includes a transistor amplifier, to which a frequency-determining resonant circuit and an ohmic device for reducing the resonant Q-value are connected in such a way that a control pulse of the pulse generator applied to an input terminal of the transistor amplifier causes the microwave oscillator to produce a microwave oscillation that can be tapped at an output terminal of the microwave oscillator, wherein the microwave oscillation follows at least approximately the temporal course of the control pulse.

Abstract: The invention provides an oscillator and a control method for controlling the oscillator which reliably oscillates even when the oscillator is driven at a low voltage. An oscillator repeats a startup operation and a suspension of the startup operation by turning on and off a switch with half a period of a Schmitt trigger oscillator circuit, until a piezoelectric oscillator circuit is put into a normal oscillation state. The oscillator thus creates a number of opportunities of transient response allowing the oscillation amplitude of the piezoelectric oscillator circuit to grow, and reliably oscillates.

Abstract: A switch-type oscillating circuit includes a first oscillating circuit for outputting an oscillation signal having a first frequency, which includes a first oscillation transistor and a first switch circuit for turning on and off the first oscillation transistor; a second oscillating circuit for outputting an oscillation signal having a second frequency, which includes a second oscillation transistor and a second switch circuit for turning on and off the second oscillation transistor; and a coupling circuit disposed between the output end of the first oscillating circuit and the output end of the second oscillating circuit, and the input end of a common circuit.

Abstract: A reference-frequency-signal switching circuit includes an internal reference-frequency-signal oscillator for generating an internal reference-frequency signal, a reference-frequency-signal input terminal to which an external reference-frequency signal is input, a reference-frequency-signal output terminal, and a reference-frequency-signal output switching section.

Abstract: An electronic horn for mimicking a multi-frequency tone includes a wave signal generator for generating an input signal and a complex signal generator for generating a complex signal across a transducer to mimic the sound and sound intensity of an electromechanical horn. The complex signal generator produces a complex output signal which may derive from a plurality of product signals, each product signal being derived by processing the input signal. A first product signal drives the transducer through a full bridge motor driver circuit and a second product signal is converted to a control signal by the signal processor circuit. The control signal is used to control the full bridge motor driver circuit to drive the transducer.

Abstract: A clock circuit includes an oscillator having a biasing node that causes the oscillator to enter a low-power state. The clock circuit also includes a kick-start circuit and a first mechanism. The kick-start circuit operates to provide an excitation to the oscillator, where the excitation enables the oscillator to start its oscillation. The first mechanism is configured to inhibit kick-start based on certain conditions, such as when the oscillator reaches a particular level capable of sustaining oscillation by itself or when the oscillator is already running.

Abstract: A method for synchronizing multiple subsystems using one voltage-controlled oscillator. The method includes transmitting a phase and frequency aligned output of a voltage-controlled oscillator to each subsystem within a digital system. A first subsystem of the multiple subsystems generates a first internal clock and outputs a synchronization signal to each of the other subsystems. The synchronization signal has a marker that defines a known point in time of the first internal clock. The other subsystems sample the synchronization signal using the output signal of the voltage controller oscillator to determine a starting indicator that indicates the known point in time of the first internal clock. Upon detection of the marker in the synchronization signal, the other subsystems starts a second internal clock that is synchronized with the first internal clock.

Abstract: A first inverter is provided with a feedback resistor for biasing the inverter to a linear operating range and an AC feedback path for causing oscillations to occur. A controlled current source, responsive to a control signal Vc supplied thereto and coupled to an input of the inverter supplies a current in a first sense thereto for enabling the oscillations and supplies a current in a second sense thereto for inhibiting the oscillations. The controlled current source comprises a second inverter for amplifying the control signal Vc to a logic level substantially greater than that of the first inverter and a current limiting resistor coupled in series with the second inverter for limiting current flow to and from the input of the first inverter.

Abstract: A PLL circuit detects oscillation halt of a voltage control oscillator, generates an oscillation control signal for automatically oscillating the voltage control oscillator based upon the detected signal, and automatically restores the voltage control oscillator to a normal oscillation state by the use of the generated signal. The voltage control oscillator is structured by a ring oscillator in which a plurality of differential amplifiers are connected in a ring form. A plurality of oscillation control means are arranged for the respective inputs of the differential amplifiers so as to set the ring oscillator into an oscillationable state when the voltage control oscillator halts. The oscillation control means is controlled by the oscillating control signal.

Abstract: A programmable multi-scheme clocking circuit supports multiple applications. In one implementation, the clocking circuit includes multiple clock sources such as a crystal oscillator, a RC oscillator, an internal oscillator, and an external clock. Each of the clock sources can be enabled by a respective control signal. A multiplexer couples to the clock sources and provides a clock signal from one of the clock sources as the output clock signal. External support circuitry (e.g., external tank circuits) for some of the clock sources (e.g., the crystal oscillator and the RC oscillator) can be coupled to the clocking circuit through one or more device pins. The pins to support the crystal oscillator, the RC oscillator, and the external clock signal are shared so that no additional device pins are required.

Abstract: In plural oscillation systems each of which can be described by the van der Pol equation, each oscillation system is reciprocally connected with at least one oscillation system other than the own oscillation system by a coupling factor to realize automatically the phenomenon of synchronization of the respective oscillation systems to enable spontaneous tuning of the entire system. A self-excited oscillation of an oscillation system prescribed by a van der Pol equation is controlled on/off by varying an applied voltage as a variable.

Abstract: A phase locked loop circuit includes a reset signal generating circuit for generating a reference clock signal and a reset signal from an input clock signal. A phase locked loop section generates an output clock signal based on the reference clock signal such that a phase of the output clock signal is locked in that of the reference clock signal. Also, the phase locked loop section is reset in response to the reset signal such that the phase of the output clock signal is locked in an initial value.

Abstract: A voltage compensated oscillator circuit having a resistor capacitor (RC) circuit for setting a frequency of oscillation for the oscillator circuit. A switching circuit with hysterisis is coupled to the RC circuit for providing upper and lower threshold limits. The upper and lower threshold limits being used for controlling the direction of switching of the oscillator circuit. By adjusting the upper and lower threshold limits, one may compensate for voltage signal fluctuations so that the frequency of oscillation will not change due to power supply voltage fluctuations.

Abstract: A low power oscillator having fast start-up times. The low power fast starting oscillator uses an oscillator circuit having an input and an output for generating a signal of a desired frequency. A start-up detect circuit is coupled to the output of the oscillator circuit for detecting when the oscillator circuit has reached steady state operation and for generating a start-up circuit output signal which adjusts the gain of the oscillator circuit when steady state operation has been reached by the oscillator circuit. A noise generator is coupled to the input of the oscillator circuit and to the start-up detect circuit for inputting a noise pulse into the oscillator circuit. The noise pulse is used for biasing the input of the oscillator circuit to approximately an optimal bias voltage level. The noise generator is further used for sending an enable start-up detect signal to the start-up detect circuit to activate the start-up detect circuit.

Abstract: There is disclosed an oscillator circuit comprising the first load capacitor with one electrode there of being connected with an input side of a CMOS inverter within a quartz oscillator circuit, and the second load capacitor with one electrode there of being connected with the output side of the inverter, wherein the inverter is coupled to a lower potential side via a current-limiting device, and the other electrodes of the first and second load capacitors are coupled to a lower potential side via the above-described current-limiting device. Thus, variations in the power-supply voltages synchronized with oscillation are reduced with realization of lower current consumption.

Abstract: The present invention provides a reliable method for oscillating an oscillator having an oscillator output without fail. The method includes steps of detecting whether the oscillator is regularly oscillating, and releasing the oscillator to oscillate when the oscillator is regularly oscillating, and holding the oscillator from oscillating until an enough control voltage is built-up therefor when the oscillator is not regularly oscillating. The present invention also provides a start up circuit for an oscillator having an oscillator output having a first state in a first instance and a second state in a second instance.

Abstract: Oscillating circuitry built in integrated circuitry (1) comprises a ring oscillator (31) for generating a first clock, an external oscillator (40) capable of generating a second clock in either one of two oscillating modes which is determined according to an external circuit (12 and 13, or 6 through 8) connected to terminals (2 and 3) thereof, and an internal clock selection circuit (41) which delivers the first clock as an internal clock to the integrated circuitry (1) just after the integrated circuitry (1) is activated or reset, stops the delivery of the first clock and simultaneously furnishes a signal held at a logic high level as the internal clock in response to a control signal for instructing a selection of the second clock, and then determines whether or not the external oscillator (40) is generating the second clock properly, and which furnishes the second clock as the internal clock when it determines that the external oscillator (40) is generating the second clock properly.

Abstract: A crystal-stabilized integrated-circuit oscillator which uses a filtered analog coupling to automatically disable the bias current to an auxiliary gain after startup. Positive feedback is used to ensure that the switchover is completed once it starts. Thus the device sizes and biases of the primary gain stage can be selected for very low-power operation, while assuring that the oscillator will always start-up whenever poser is valid.

Abstract: A data decoding circuit of the present invention can regenerate a bit synchronization signal from a data received by using a code such as a split-phase code and Manchester code in which a binary value can be detected through a transition of voltage at a central area of a bit cell and transform the received data into a serial binary data. The data decoding circuit includes an edge detection section for detecting a transition point in the received data; a pulse generating section for generating a phase comparing timing signal having a pulse width of substantially 1/(4.times.fs) when fs is a data transfer frequency and a received data regenerating signal having a pulse width of substantially 1(2.times.

Abstract: An oscillator circuit, having an inverter with input and output terminals interconnected through a feedback resistance, operates in two modes. In a first mode, the input and output terminals are coupled to an external crystal resonator. In a second mode, an external clock signal is supplied to the input terminal. In the second mode, the input terminal is disconnected from the output terminal, and in addition, the output-drive capacity of the inverter is reduced, or the output terminal of the inverter is held at a fixed potential.

Abstract: A system and method for ensuring a substantially constant oscillator frequency that is substantially independent of the operating temperature and is substantially independent of variations of the supply voltage level where the oscillator is an on-chip oscillator without requiring significantly additional logic, e.g., not requiring the use of multiple comparators and enabling post packaging modifications of the oscillator frequency. The present invention utilizes one or more paired resistors as part of the RC oscillator where each of the one or more pairs are matched according to their temperature coefficient. That is, each pair includes a resistor with a positive temperature coefficient and a resistor with a corresponding negative temperature coefficient. In addition, the present invention enables post packaging modifications to the resistors based upon one or more program signals that can modify the resistance by forming a short circuit around one or more resistor pairs.

Abstract: Methods and apparatus for controlling operation of a low frequency oscillator upon reset of a microcomputer to achieve faster start-up time are described. In one aspect, the present invention is directed to a microcomputer having an oscillator input port, an oscillator output port, and an oscillator control port, and an oscillator coupled to the microcomputer oscillator output, input, and control ports. The microcomputer is programmed to control the output on the oscillator control port so that upon reset, the output transitions from a low state to a high state in accordance with a preselected frequency for a preselected period of time. More particularly, and in one exemplary embodiment, the microcomputer controls the output on the oscillator control port upon reset so that for a preselected cycle, the output is high for approximately about one-half cycle, low for approximately about one-half cycle, and then high for approximately about one-half cycle.

Abstract: An oscillator in which the transconductance of an amplification transistor (T0) is limited through a measurement of the potential at the input electrode (G0) of the amplification transistor (T0) by means of a differential pair (T1, T2) for safeguarding the starting of the oscillator.

Abstract: Crystal oscillator circuitry provides a very fast start-up function requiring less than 100 mS. The crystal oscillator circuitry enters a stop mode when a control signal transitions from a first logic level to a second logic level thereby causing a crystal to stop oscillating. In order to initiate the fast start-up function, a pulse is provided to the gate of a transistor which is electrically connected between a first node and a second node, thus causing the voltage of the first node to move towards the voltage level of the second node and the second node to move towards the voltage level of the first node. Upon initiation of the start-up function, the energy at the crystal of the crystal oscillator circuitry is at least four times higher than the energy required in a steady state mode. The crystal oscillator circuitry has a VT (threshold voltage) independent high feedback resistance which provides stable oscillation frequency over a wide range of Vcc supply voltage.

Abstract: The present invention provides a semiconductor device wherein the oscillation of a clock signal oscillation circuit is halted by control carried out by a CPU when a clock-signal switching circuit selects either a clock signal generated by a CR oscillation circuit or a clock signal generated by an oscillator-driven oscillation circuit. A frequency divider divides the frequency of a clock signal generated by the clock signal oscillation circuit, supplying a clock signal with a divided frequency to the clock-signal switching circuit.

Abstract: A high stability clock oscillator circuit that has no inductors in the oscillator circuit itself. In the preferred embodiment neither the collector, the base, nor the emitter of the transistor is grounded and the oscillator output is taken from the collector of the transistor. In an alternate embodiment the collector is AC grounded and the output is taken across a load resistor coupled between the emitter of the transistor and ground. The resulting oscillator is a high stability oscillator that can be used as a dock oscillator in high frequency circuits.

Abstract: A high frequency pulse-time modulation signal generator employs first and second microwave or laser oscillators which are mutually locked uniquely either in a symmetric mode or an antisymmetric mode by means of an electronic phase shifter. The output signals from the oscillators are combined to generate pulse-time modulated output pulses through application of a control voltage to the electronic phase shifter which switches the mutual locking of the oscillators back and forth between the symmetric and antisymmetric modes. In a microwave embodiment, a hybrid-tee, such as a magic-tee, is employed to combine the oscillator output signals, while in the optical or laser embodiment, a half-silvered mirror is employed to combine the oscillator output signals. When the oscillators are locked in the symmetric mode, the hybrid-tee generates an output pulse, and when the oscillators are locked in the antisymmetric mode, the hybrid-tee generates a zero level output.

Abstract: Complex and multi-cycle microwave pulse waveforms are generated by the transient discharge of an induction charged transmission line using only one fast switch. An essential feature of the transmission line circuit is the distinction between the ground planes of the bias circuit and the microwave circuit. This distinction permits spatial variation of the charge induced on the transmission line over sections of ground plane biased at different potentials. Rapid discharge of the biased ground plane sections produces a complex or multiple cycle voltage wave on the transmission line which results in multicycle microwave pulse generation. The transient discharge is initiated by a fast switch located in the microwave ground plane. The similarity between some operating characteristics of the herein described device and the traditional Frozen Wave Generator (FWG) justify naming the new device and Induction Charged Frozen Wave Generator (ICFWG).

Abstract: An electrical signal generator for generating an output signal of predetermined frequency has an oscillator of predetermined frequency operable to produce a first signal of said frequency, which is fed to an amplifier which amplifies the power level of the first signal to produce a first higher power signal. A switch/controller circuit both switches on and off the feed of the first signal from the oscillator to the amplifier and controls the amplifier. The first higher power signal is fed to an output. The oscillator may produce a first signal and an inverted first signal, with the amplifier amplifying the first signal and the inverted first signal, and with both the first higher power signal and the inverted first higher power signal being fed to the output.

Abstract: An oscillating circuit body 10 includes a first two-input NAND gate, a feedback resistor, a resonator and capacitors. One input terminal of the NAND gate functions as a control terminal to which is applied a first control signal to perform on-off control of oscillation operation of the circuit body. An output terminal of the circuit body is connected to an input terminal of a second two-input NAND gate via two inverters. The other input terminal of the second NAND gate is connected to a control terminal to which a second control signal is applied. The second NAND gate is used for masking the oscillatory output in response to the second control signal for a predetermined period, and the output from the second NAND gate is provided as a final clock output.

Abstract: Both differential and single-ended band-switchable VCOs are described. The single-ended version of the voltage controlled oscillator in its most basic form includes a load, two transistors, two delay elements, and a switchable current source. The first transistor includes a collector, an emitter and a base coupled to the load to form an output terminal for providing an oscillator output signal. The first delay element is connected between the collector and the base of the first transistor. The second transistor includes a collector, an emitter and a base connected to the base of the first transistor. The second delay element is connected between the collector of the first transistor and the collector of the second transistor.

Abstract: A signal of a locking detector of a synthesizer indicates in a first state that a loop is locked, and in a second state that the loop is unlocked. The synthesizer may be temporarily deactivated by switching off the operating voltage of a voltage controlled oscillator by means of a switching signal. The alarm circuit of the synthesizer includes a first detector, a state of the output of which changes with a delay, in response to the change of the signal of the detector conveyed to the detector, and a second detector, the state of the output of which changes with a delay, in response to the change of the switching signal conveyed to the detector, and a device generating the alarm signal. The device provides the output signal of the alarm circuit in response to the output signals of the detectors. By selecting appropriate delay-times for the detector, it is possible to achieve the intended operation.

Abstract: An optically controlled MESFET semiconductor oscillator assembly having a MESFET semiconductor which, when voltage biased by a pulsed dc voltage, oscillates at a free running frequency; an optical signal delivery system, such as a light intensity modulator connected to optical fibers; and other oscillator circuitry including a pulse generator. In operation, the pulsed free running oscillation of the MESFET semiconductor can be injection locked to the intensity modulated optical signal delivered via the optical signal delivery system.

Abstract: An oscillator circuit (143) comprises a master phase-locked loop (PLL) circuit (202) that receives as input a first reference frequency signal (136) and generates a first clock signal (210) in response to an oscillator control signal (212). The oscillator circuit (143) includes a frequency sensitive slave circuit (206) having at least one frequency sensitive element (322) that is responsive to a tracking control signal (214) to generate a second clock signal (216). A tracking control circuit (204) is responsive to the oscillator control signal (212) for generating the tracking control signal (214). The tracking control signal (214) serves as a bias signal, and is connected to the frequency sensitive slave circuit (206) for achieving a fast power up sequence of the oscillator circuit (143).

Abstract: A data retiming system for retiming incoming data and eliminating jitter is described. The data retiming system includes a local clock; a phase aligner for receiving the incoming data and producing a recovered clock from the incoming data, and then producing retimed incoming data by retiming the incoming data with the recovered clock; and a buffer memory for removing jitter from the retimed incoming data by storing the retimed incoming data to the buffer memory in accordance with the recovered clock and reading the stored data from the buffer memory in accordance with the local clock. The data retiming system provides reliable operation even at very high data rates. A freezeable voltage-controlled oscillator for producing a clock signal in accordance with a freeze signal and a frequency control signal is also disclosed. Using current steering techniques, the freezeable voltage-controlled oscillator is able to freeze its output very quickly.