Abstract: A MEMS device includes a substrate, a cavity formed above the substrate, a first vibrator contained in the cavity, and a second vibrator contained in the cavity and having a natural frequency different from that of the first vibrator. The first vibrator and the second vibrator are preferably arranged along a long side of the cavity having a rectangular shape in plan view.

Abstract: Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.

Abstract: An apparatus, and an associated method, for synthesizing a discrete-valued oscillating signal. Input parameters are provided that are determinative of the frequency, gain, and phase characteristics of the resultant, oscillating signal. The discrete-valued, oscillating signal is combinable with another signal to form a mixed signal of a desired frequency, gain, and phase characteristic using a single complex multiplication operation.

Abstract: This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information.

Abstract: A receiver is provided. The receiver includes a differential amplifier amplifying differential input signals input to input terminals and outputting differential output signals through output terminals and an oscillator connected to the output terminals of the differential amplifier. The differential amplifier and the oscillator operate alternatively in response to an enable signal.

Abstract: A VCO device is described that has pre-compensation. Digitally switchable compensation capacitors are selectively activated to adjust operation of the VCO to mitigate undesirable operational effects. In some example embodiments, the digitally switchable compensation capacitors of the VCO are adjusted to compensate for the effects of activating (from a quiescent state) an output buffer driven by the VCO.

Abstract: A fast settling frequency synthesizer is disclosed. The particular capacitor to frequency relationship in the band of operation is first determined. The calculation can be performed by determining the capacitor to frequency relationship at two points and calculating the slope. Once these parameters are known, then, for any change in frequency due to a channel hop, the appropriate capacitor value can be determined.

Abstract: The invention provides a dual-mode voltage-controlled oscillator (DMVCO), a frequency synthesizer and a wireless receiving device, and pertains to the technical field of integrated circuit of radio frequency wireless receiver. The DMVCO and the frequency synthesizer can operate in a wideband mode and a quadrature mode. When operating in the quadrature mode, a quadrature signal is provided for a Single Sideband Mixer of the frequency synthesizer by a quadrature coupling of a first voltage-controlled oscillator unit and a second voltage-controlled oscillator unit in the DMVCO in the overlapped frequency band so that the frequency synthesizer can cover a higher output frequency band. Therefore, the tuning range of the DMVCO of the invention is wide, and the frequency synthesizer using the DMVCO is low in power consumption, simple in structure and has good frequency spur performance.

Abstract: In a dual-hand capable voltage-controlled oscillator (VCO) device at least two voltage-controlled oscillator units (VCO1, VCO2) are coupled via a reactive component (A) and each said at least one voltage-controlled oscillator unit (VCO1, VCO2) further being connected to at least a respective external switching device (B1, B2) adapted to control an operating frequency of the (VCO) device.

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract: An oscillator includes: a plurality of MEMS vibrators formed on a substrate; and an oscillator configuration circuit connected to the plurality of MEMS vibrators, wherein the plurality of MEMS vibrators each have a beam structure, and the respective beam structures are different, whereby their resonant frequencies are different.

Abstract: In one embodiment, an apparatus includes a first circuit of a digitally controlled oscillator (DCO). The first circuit has a loss component. A second circuit is coupled to the first circuit and configured to transform a positive impedance into a negative impedance in series with a negative resistance. The negative impedance includes an adjustable reactive component used to adjust a frequency of an output signal of the DCO. An equivalent reactance seen by the first circuit is less than a reactance of the adjustable reactive component.

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract: A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor are respectively coupled to the second electrode of the first capacitor and the second electrode of the second capacitor. Two channel electrodes of a second transistor are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes of the first, second, and third transistors are responsive to a tuning signal, and an inductor is coupled between the first electrodes of the first and second capacitors.

Abstract: A first exemplary aspect of an embodiment of the present invention is a phase-locked loop circuit including: a voltage-current converter that converts a control voltage into a control current, the control voltage generated according to a phase difference between an input pulse signal and a feedback pulse signal fed back from an output side of a current controlled oscillator; the current controlled oscillator that generates an output pulse signal having a frequency according to the control current; a current detection unit that detects the control current; and a frequency range switch that switches a frequency range of the output pulse signal according to the detected control current.

Abstract: Provided is a transformer-based oscillator which is suited to oscillate frequencies in multiple bands. An oscillator includes a transformer resonance unit and a plurality of complementary transistors. The transformer resonance unit includes a primary coil and a secondary coil corresponding to the primary coil. The plurality of complementary transistors have gates and drains between which both ends of the transformer resonance unit are respectively connected. Thus, the oscillator may operate in a differential mode or common mode according to the phase of the transformer resonance unit. Also, a complementary transistor constituting a multiband oscillation loop may be independently connected to both ends of the transformer resonance unit, and an oscillation loop of at least one band may be selected out of a multiband oscillation loop using a switch unit. Thus, the oscillator may be suited to oscillate resonance frequencies in multiple bands.

Abstract: A communications system includes a radio frequency (RF) element (104) for transforming an input RF signal into at least one of a first conditioned RF input signal associated with a first frequency range and a second conditioned RF input signal associated with a second frequency range higher than the first frequency range. The system also includes a local oscillator (LO) circuit (106) for generating at least a first LO signal, the LO circuit having an operating frequency range spanning at least a portion of a first inclusive frequency range defined by a lowest frequency of the first frequency range and a highest frequency of the second frequency range. The system further includes a mixer (108) for generating a first intermediate frequency (IF) signal based on one of the first and the second RF input signals and the first LO signal, and an IF element (110) for conditioning the first IF signal.

Abstract: An oscillator output is controlled from an external voltage control terminal using an interpolative divider as a frequency modulator. The oscillator includes a reference clock generator, analog to digital converter, and an interpolative divider. Nominal output frequency is determined by the frequency of the reference clock and the nominal divide value of the interpolative divider. The divide value is changed according to the voltage control input value which is converted to a digital value via an analog to digital converter. Multiple interpolative dividers may be coupled to the single reference clock generator and each have a voltage control input and analog to digital converter.

Abstract: According to an embodiment, a digitally controlled oscillator outputs an oscillation signal having an oscillation frequency according to an oscillator tuning word. The digitally controlled oscillator includes a control unit and an oscillator. The control unit divides the oscillator tuning word of N bits into upper (N?A) (A?1 and N>A) bits and lower A bits, converts the upper (N?A) bits into a first code to perform Binary control of (N?A) bits and converts the lower A bits into a second code to perform Unary control of (2^(A+1)?2) bits, and outputs the conversion results, and the oscillator outputs oscillation signals having oscillation frequencies according to the first and second codes output from the control unit.

Abstract: A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.

Abstract: A transfer apparatus includes a receiver to receive an input signal and to extract a clock signal from the input signal, an input signal interruption detector to detect whether an input signal is input, an oscillator, and a frequency setter to set an oscillation frequency of the oscillator such that a difference between the oscillation frequency of the oscillator and a frequency of a frequency division signal into which a clock signal extracted from the input signal is frequency-divided falls out of a passband width of a filter when the input signal interruption detector detects the input of the input signal.

Abstract: A wideband digitally-controlled oscillator (DCO) is provided. The wideband DCO includes an active element which is driven by a first digital control signal; a single inductor which is connected to the active element in parallel, and comprises fixed inductance; and a plurality of capacitors which are connected to the single inductor in parallel, and vary operating frequency by being selectively turned on or off by a second digital control signal. Accordingly, the wideband DCO capable of operating in a wideband frequency range using a single inductor is provided, and if the wideband DCO is implemented using a single integrated circuit (IC) chip, the size of chip is reduced as the single inductor is used.

Abstract: A system and method for effectively utilizing a dual-mode phase-locked loop to support a data transmission procedure includes a voltage controlled oscillator that generates a receiver clock signal in response to VCO input control signals. A binary phase detector generates a BPD output signal during a BPD mode by comparing input data and the receiver clock signal. In addition, a lock-assist circuit generates a PFD output signal during a PFD mode by comparing a reference signal and a divided receiver clock signal. A loop filter performs a BPD transfer function to generate a VCO input control signal from the BPD output signal during the BPD mode. The same loop filter also performs a PFD transfer function to generate the VCO input control signal from the PFD output signal during the PFD mode.

Abstract: Techniques for calibrating digitally controlled oscillators (DCOS) are disclosed. In one aspect of the disclosure, an initial set of control codes for operating the DCO with a coarse frequency tuning bank with multiple overlapping coarse frequency tuning segments (LTBs) and one fine main frequency tuning bank (MTB) is determined. A range of output frequencies produced from the initial set is identified. Instances of overlap are identified in the frequency range between consecutive LTB segments. An offset in the MTB is added that corresponds to the overlap instance between consecutive LTBs to establish a revised set. The revised control codes are utilized to tune the DCO over the desired frequency range.

Abstract: The present invention relates to a frequency modulation device and a switching mode power supply using the frequency modulation device. To prevent electro-magnetic interference (EMI), it is required to slightly vary a switching operation frequency in an SMPS operation. In some embodiments, at least one first signal having a predetermined cycle is generated, a second signal corresponding to a level of a first signal is generated at a turn-off time of a switch, a first reference voltage having at least two different levels is generated according to the second signal, and an oscillator signal for increasing along a first slope during a first period and decreasing along a second slope during a second period between the first reference voltage and a second reference voltage having a level that is different from the first reference voltage is generated.

Abstract: A method is provided for selecting an operating band of a voltage-controlled oscillator (“VCO”) of a phase locked loop (“PLL”) for which the lock frequency is closest to a center of the frequency range of the operating band. In such method, steps can be performed to determine the maximum and minimum frequencies of the operating band and the center frequency between them. From the center frequency of the operating band and the lock frequency within such operating band, a difference value can then be determined. The operating bands of the PLL can be tested until an operating band having the smallest difference value is determined. The VCO can then be set to such operating band in order for the lock frequency to be closest to the center frequency of the operating band.

Abstract: A phase locked loop (“PLL”) includes a voltage controlled oscillator (“VCO”) operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating the VCO.

Abstract: A dual-band wideband local oscillation signal generator includes an oscillation unit, a division unit, a poly phase filter (PPF), a switch unit, and a single side band (SSB) mixer. The oscillation unit is configured to generate a positive in-phase (IP) signal, a negative in-phase (IN) signal, a negative quadrature-phase (QN) signal, and a positive quadrature-phase (QP) signal. The division unit is configured to divide frequencies of the IP signal and the IN signal and generate an RF signal. The PPF is configured to receive the IP signal and the IN signals inputted to the division unit, and generate an LO IP signal, an LO IN signal, an LO QP signal, and an LO QN signal. The switch unit is configured to receive the generated LO signals and select a high band frequency signal or a low band frequency signal.

Abstract: A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.

Abstract: A VCO in a phase-locked loop (PLL) is arranged to receive low-pass data via a first input and high-pass data at a second input. The first input is coupled to a first set of varactors in the VCO. The second input is coupled to a second set of varactors in the VCO. The controller sets the input voltage at the first input and directs a charge pump to operate in a tri-state mode that opens the feedback loop of the PLL. The controller applies different voltages via the second input and measures the change in output frequency. A present gain of the VCO is determined from the ratio of the change in frequency and the change in voltage at the second input.

Abstract: An oscillator is provided which comprises an array of capacitances. At least some capacitances in the array have different capacitance values.

Abstract: A resonator of a VCO includes a fine tuning main varactor circuit, an auxiliary varactor circuit, and a coarse tuning capacitor bank circuit coupled in parallel with an inductance. The main varactor circuit includes a plurality of circuit portions that can be separately disabled. Within each circuit portion is a multiplexing circuit that supplies a selectable one of either a fine tuning control signal (FTAVCS) or a temperature compensation control signal (TCAVCS) onto a varactor control node within the circuit portion. If the circuit portion is enabled then the FTAVCS is supplied onto the control node so that the circuit portion is used for fine tuning. If the circuit portion is disabled then the TCAVCS is supplied onto the control node so that the circuit portion is used to combat VCO frequency drift as a function of temperature. How the voltage of the TCAVCS varies with temperature is digitally programmable.

Abstract: A phase-locked loop that supports a large frequency drift capability, yet maintains a low Kvco, and does not introduce noise or discontinuities in the frequency of the generated phase-locked loop output signal. The phase-locked loop may include a VCO with an LC tank circuit, the capacitance of which may be adjusted in incremental units. By gradually adjusting a control signal applied to a selected VCO LC tank circuit frequency adjustment control line, e.g., in a continuous ramped function, or time-averaged ramped function, from LOW-to-HIGH or from HIGH-to-LOW, over a period of time that is greater than the response time of the phase-locked loop, a frequency range supported by the VCO may be shifted to either a higher frequency range or a lower frequency range, as needed, to accommodate environmentally induced frequency drift in the VCO, without introducing noise or discontinuities in the frequency of the generated phase-locked loop output signal.

Abstract: Methods and apparatus for self testing a multiband voltage controlled oscillator (VCO) are disclosed. A tuning voltage of the VCO is adjusted where the output of the VCO does not affect the input to the VCO. Frequency bands in the VCO are selected. Output frequencies of the VCO are measured.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: An oscillator may include a crystal resonator, an inverter coupled in parallel with the crystal resonator, a first switched capacitor coupled to a first terminal of the crystal resonator, a second switched capacitor coupled to a second terminal of the crystal resonator, a control module configured to output a periodic dithering signal, the periodic dithering signal having a first pulse width based on a desired frequency of oscillation for the oscillator, and a delay module configured to communicate a first periodic enable signal to enable the first switched capacitor and a second periodic enable signal to enable the second switched capacitor. At least one of the first periodic enable signal and the second periodic enable signal may have a second pulse width greater than the first pulse width. The second periodic enable signal may be phase delayed relative to the first periodic enable signal by a non-zero delay.

Abstract: A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator.

Abstract: A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.

Abstract: A high-frequency generator circuit comprises a signal generating circuit, a delay unit, a selector, a synthesizer circuit, and a controller. The signal generating circuit generates a signal having the same frequency as an output signal. The delay unit includes a plurality of delay circuits, and delays the signal generated by the signal generating circuit. The selector selects an output signal of the delay circuits. The synthesizer circuit synthesizes the signal selected by the selector, and outputs the output signal. The controller controls the selector based on data for setting a waveform of the output signal and a control signal for setting at least amplitude, phase and frequency of the output signal.

Abstract: Aspects of a method and system for varactor linearization are provided. In this regard, a relationship between control voltage and capacitance of a variable capacitor may be controlled utilizing a plurality of bias voltages communicatively coupled to a corresponding plurality of bias terminals of said variable capacitor. The variable capacitor may comprise a plurality of two-terminal unit varactors and a first terminal of each unit varactor may be coupled to an RF terminal of the variable capacitor, a second terminal of one of the unit varactors may be coupled to the control voltage, and a second terminal of each of the remaining unit varactors may be coupled to one of the bias voltages. The bias voltages may be generated via a resistor ladder and/or via the resistive nature of a portion of semiconductor substrate. The bias voltages may linearize the relationship between the control voltage and the capacitance.

Abstract: A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

Abstract: Provided are a multi-output oscillator using a single oscillator, and a method of generating multiple outputs. The multi-output oscillator includes: an oscillator outputting the single frequency; a multiplier multiplying the single frequency to output a first frequency; a first frequency divider dividing the single frequency by a first division factor; a first mixer outputting a second frequency by mixing an output of the first frequency divider and an output of the multiplier; a second frequency divider dividing the single frequency by a second division factor; a second mixer mixing the output of the second frequency divider and the output of the first mixer to output a third frequency; and a third mixer mixing the output of the second frequency divider and the output of the multiplier to output a fourth frequency.

Abstract: An automatic frequency calibration circuit and an automatic frequency calibration method for a fractional-N frequency synthesizer are provided. In a calibration mode, a state machine adjusts a fractional part and an integer part of a division ratio of a frequency divider unit according to a required precision. A first and a second frequency detecting units detect a reference frequency and an output frequency of the frequency divider unit, respectively. A judging interval unit defines at least one judging period in a total comparison time. A comparator compares the outputs of the first and the second frequency detecting units and outputs a comparison result at the judging period. Wherein, the state machine changes the capacitor configuration of a voltage-controlled oscillator when the comparison result shows that the reference frequency does not match the output frequency of the frequency divider unit.

Abstract: A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.

Abstract: A phase locked loop apparatus includes an oscillator, a variable capacitance device, a selectable capacitance device, and a capacitance controller that is configured to provide a control signal to the selectable capacitance device. The selectable capacitance device is connected to the oscillator and is responsive to the control signal such that the selectable capacitance device has a first capacitance at a first control signal value and a second capacitance at a second control signal value. The capacitance controller only selects either the first capacitance or the second capacitance by providing a control signal that has the first control signal value to select the first capacitance and having the second control signal value to select the second capacitance.

Abstract: Provided is a ring oscillator having an extended range of oscillation frequency by varactors coupled to delay cells even in a simple structure. The wide frequency range results from simply varying an oscillation frequency by control signals applied to the varactors. Since additional switches connected to the delay cells contribute to increase or decrease of the oscillation frequency range, the ring oscillator can conveniently be employed in various types of oscillation systems.

Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

Abstract: A voltage controlled oscillator includes first and second variable capacitance circuits 120 and 130, and first and second capacitance switch circuits 140 and 150. A control voltage Vt is fixedly applied to the first variable capacitance circuit 120, and control signals Fsel2 and Fsel3 are fixedly applied to the first and second capacitance switch circuits 140 and 150, respectively. When both of the control signals Fsel2 and Fsel3 are at a low level, the control signal Fsel1 is applied to the second variable capacitance circuit 130. When the control signals Fsel2 and Fsel3 are both not at the low level, the control voltage Vt is applied to the second variable capacitance circuit 130. As a result of this control, a high-frequency variable range is divided into two variable ranges, one based on upper frequencies and the other based on lower frequencies. This enables suppression of a frequency sensitivity without narrowing the high-frequency variable range.

Abstract: A wideband frequency generator has two or more oscillators for different frequency bands, disposed on the same die within a flip chip package. Coupling between inductors of the two oscillators is reduced by placing one inductor on the die and the other inductor on the package, separating the inductors by a solder bump diameter. The loosely coupled inductors allow manipulation of the LC tank circuit of one of the oscillators to increase the bandwidth of the other oscillator, and vice versa. Preventing undesirable mode of oscillation in one of the oscillators may be achieved by loading the LC tank circuit of the other oscillator with a large capacitance, such as the entire capacitance of the coarse tuning bank of the other oscillator. Preventing the undesirable mode may also be achieved by decreasing the quality factor of the other oscillator's LC tank and thereby increasing the losses in the tank circuit.

Abstract: Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide LC tank circuits having an inductance and a capacitance. In addition, the circuits include a flicker noise reducing switch that is operable to selectively incorporate the capacitance such that an output of the circuit operates at a frequency based on a combination of the inductance and the capacitance.