Abstract: In various embodiments, the invention provides a frequency controller and a temperature compensator for frequency control and selection in a clock generator and/or a timing and frequency reference. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals.

Abstract: The present invention is an oscillator including: first transistors outputting oscillation signals of different oscillation frequencies to collectors; a common node to which outputs of emitters of the first transistors are connected and input; a feedback circuit feeding an output of the common node to bases of the first transistors; and isolation circuits that are respectively provided between the emitters of the first transistors and the common node and cut off high frequency components from the common node.

Abstract: Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator.

Abstract: A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a swallow type frequency divider, and a switching bank LC tuning voltage-controlled oscillator having wide-band and low phase noise characteristics. The multimode prescaler operates in five modes and divides a signal up to 12 GHz. The wide-band frequency synthesizer can be used in various fields such as WLAN/HYPERLAN/DSRC/UWB systems that operate in the frequency range from 2 GHz to 9 GHz.

Abstract: The present invention provides a clock circuit to produce a Reference Clock Signal used to latch data between first bit stream(s) and second bit stream(s), wherein the number and bit rate of the first bit stream(s) and the second bit stream(s) differ. The VCO generates one of a number of inputs to a PLL within the clock circuit. At a minimum, these inputs include a first bit stream data clock. Additionally, these inputs may further include a Loop Timing Clock Signal, an External Reference Clock Signal, and/or a Reverse Clock Signal for the PLL. The input provided by the VCO make up a VCO Output Signal wherein a filtering circuit that circuit includes a capacitor and a resistor reduces noise contained within the VCO Output Signal.

Abstract: An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Abstract: In a communication semiconductor integrated circuit device, an oscillator of a PLL circuit can operate in a plurality of frequency bands. With a control voltage (Vc) of the oscillator fixed to a predetermined value (VDC), an oscillation frequency of the oscillator is measured for each band to be stored in a storage. When the PLL operates, a setting value to specify a band is compared with the measured frequency values stored in the storage. As a result of the comparison, a band to be actually used by the oscillator is determined.

Abstract: A novel circuit for obtaining the bandwidth of a phase-locked loop circuit is disclosed. The circuit adjusts a phase of a signal (reference or generated), causing the phase-locked loop circuit to adjust the frequency of its voltage-controlled oscillator as it recovers a phase lock. The circuit times the duration of the recovery stage, from which the loop bandwidth may be obtained. Adjustments to the programmable portions of the phase-locked loop may then be made in accordance with design specifications.

Abstract: A system in one embodiment includes a voltage controlled oscillator; at least two varactors coupled to a tank node, each of the varactors being of a different physical size, the tank node being coupled to the voltage controlled oscillator; and switches for selectively turning the varactors on and off, wherein switching a first of the varactors from off to on and a second of the varactors from on to off creates a capacitance step of less than about 10 fF thereby tuning the voltage controlled oscillator from a first state to a second state.

Abstract: A voltage-controlled oscillator (VCO) of ring-connected stages, where each stage in the VCO has a first set of differential inverters biased by variable bias voltages, and a second set of differential inverters biased by fixed bias voltages. The differential inverters in each stage are connected in parallel with each other. Each set of differential inverters in a stage may contain only one differential inverter. The variable bias voltages are provided by charge pumps and associated circuits as used in well-known self-biasing schemes for phase locked loops. The fixed bias voltages are provided by a biasing circuit, matched to the circuits associated with the charge pumps, but where a fixed control voltage is applied to provide the fixed bias voltages.

Abstract: The invention, which relates to a method and an arrangement for interference compensation in a phase-locked loop comprising a voltage-controlled frequency generator, wherein the frequency generator is tuned to a nominal frequency by a tuning voltage Vtune and whose actual frequency is compared with a reference frequency by means of a frequency comparison and is re-adjusted if a deviation is detected via the frequency comparison, in which case, in the event of interference, the tuning voltage Vtune is changed by an interference voltage Vstör that depends on the interference event, and thus a frequency deviating from the nominal frequency is generated, which deviating frequency is corrected again by the phase locked loop, is based on the object to provide a method and an arrangement for interference compensation in a phase-locked loop comprising a voltage-controlled frequency generator, with which a deviation from a predefined nominal frequency is avoided if known interference events occur.

Abstract: An apparatus for compensating for variations in loop gain of a phase locked loop as a function of frequency, comprising a correction calculator for introducing a loop gain correction as a function of target frequency of a oscillator controlled by the phase locked loop.

Abstract: A fully integrated, programmable mixed-signal radio transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the radio transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC includes a tunable resonant circuit that includes a transmission line having an inductance, a plurality of switchable capacitors configured to be switched into and out of the tunable resonant circuit in response to a first control signal, and at least one variable capacitor that can be varied in response to a second control signal, wherein a center resonant frequency of the resonant circuit is electronically tunable responsive to the first and second control signals that control a first capacitance value of the plurality of switchable capacitors and a second capacitance value of the at least one variable capacitor.

Abstract: Variable capacitance circuitry includes a fine tuning bank and a medium tuning bank. The fine tuning bank includes a plurality of varactors of progressively increasing size (e.g., width). Only one of these varactors is turned on at any one time. The medium tuning bank includes a plurality of similarly sized varactor circuits. These are turned on selectively in thermometer fashion (e.g., more are turned on (or off) as more (or less) overall capacitance is needed). The medium tuning bank increment is matched to the fine tuning bank range, so that when the fine tuning bank reaches an end of its range, another medium increment can be added or subtracted while the fine tuning bank is reset to the other end of its range. A uniform progression of small, incremental, capacitance changes is therefore provided over the relatively wide tuning range of the medium bank.

Abstract: An integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha-?) and an integral loop gain control having a programmable loop gain coefficient (rho-?).

Abstract: The invention is directed to a resonant circuit having a frequency-determining element which has at least one switchable frequency-changing element connected in parallel therewith. The frequency-changing element has two series-connected transistors whose control connections are connected to a node that receives a fixed potential. First connections of the two series-connected transistors are connected to one another and also to a control input for a control signal for switching the frequency-changing element of the resonant circuit. The invention keeps the control voltage for the two transistors at a higher potential than the threshold voltage for the transistors. This reduces a parasitic capacitance in the two transistors during operation.

Abstract: Systems involving temperature compensation of voltage controlled oscillators are provided. In this regard, a representative system incorporates: a voltage controlled oscillator (VCO) having a tuning port and a phase-locked loop (PLL); and a temperature dependent voltage source. The VCO selectively exhibits one of a coarse tuning mode in which the temperature dependent voltage source is electrically connected to the VCO tuning port, and a locked mode in which the temperature dependent voltage source is not electrically connected to the VCO tuning port such that the PLL controls the frequency of the VCO.

Abstract: In various embodiments, the invention provides a frequency controller to control and provide a stable resonant frequency of a clock generator and/or a timing and frequency reference. Such stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted.

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract: The invention comprises a phase locked loop that has an input adapted to receive a reference frequency. A phase detector is connected directly to the input, a charge pump is connected directly to the phase detector, and a loop filter is connected directly to the charge pump. Also, a voltage controlled oscillator is connected directly to the loop filter, and is adapted to perform frequency band selection. A band selection circuit is connected to the voltage controlled oscillator.

Abstract: A calibration circuit for voltage-controlled oscillator (VCO) includes a calibration bias generator, a VCO, a detection unit, a micro control unit, an adjuster unit, a phase-locked loop (PLL) unit, a control voltage detection unit, and a control switch set. The calibration bias generator outputs a first control voltage. The VCO outputs an oscillation frequency according to the first control voltage. The detection unit detects the oscillation frequency and outputs the detection result signal to the micro control unit. The micro control unit outputs an adjust signal according to the detection result signal. The adjuster unit receives the adjust signal voltage and adjusts the oscillation frequency output from the VCO according to the adjust signal voltage. The PLL unit outputs a second control voltage to the VCO. The control voltage detection unit outputs voltage-detection signal to the micro control unit, which outputs the adjust signal according to the voltage-detection signal.

Abstract: An RF IC in which a PLL circuit including a loop filter is incorporated into a semiconductor chip is achieved without increasing power consumption or chip size. The RF IC includes a VCO capable of switching oscillation frequency bands, a variable frequency divider, a phase comparator, and a loop filter, which are contained in the PLL loop. A discrimination circuit discriminates a lead or lag in a phase of an output signal from the variable frequency divider against a reference signal and an automatic band selecting circuit generates a signal for switching the frequency bands of the VCO based on output from the discrimination circuit. While switching the frequency bands of the VCO by means of bisection algorithm, the RF IC detects an optimum frequency band, and adds offset to it to determine a final usable frequency band.

Abstract: An oscillator includes a first resonator circuit, a second resonator circuit coupled to the first resonator circuit and a reconfigurable network having a transconductance and coupled to at least one of the resonator circuits. Reconfiguration of the reconfigurable network with respect to the transconductance allows selection of one of multiple oscillation modes of the oscillator.

Abstract: A modulation circuit includes a microelectronic electromechanical system (MEMS) based resonant structure having a resonant frequency, an excitation input and an output. A control module is coupled to the excitation input of the MEMS based resonant structure. The control module modifies resonant characteristics of the MEMS based resonant structure to modulate the resonant frequency of the MEMS based resonant structure to produce a modulated signal at the output.

Abstract: A method and a voltage-controlled oscillator provide an output signal with a frequency within one of a plurality of frequency bands, while reducing or eliminating temperature-induced band-switching or other drifts in operating frequency. The band-switching is reduced or eliminated by providing a circuit that adjusts a tuning sensitivity according to a calibration performed under test conditions. For example, such a voltage-controlled oscillator may include (a) a digitally controlled variable current source for providing a first control current to select one of the frequency bands for the voltage-controlled oscillator; (b) a variable transconductance circuit providing a second control current to compensate a variation in operating frequency; and (c) a control circuit for varying the frequency of the output signal in accordance with the first and second control signals.

Abstract: An integratable circuit arrangement is provided having a circuit unit, controllable by means of at least one control voltage, to provide a high-frequency output signal dependent on the at least one control voltage. According to the invention, (a) a clocked DC converter is provided, which is formed to provide at least one control voltage, depending on a control signal applied at its clock input, and (b) the circuit arrangement is formed to supply the clock input with a control signal, dependent on the high-frequency output signal.

Abstract: Disclosed is a dual-band voltage-controlled oscillator using bias switching and output-buffer multiplexing. The dual-band voltage-controlled oscillator includes a power supply unit for supplying a source voltage; plural voltage-controlled oscillation units for outputting different oscillation frequencies according to controls of a certain tuning voltage; plural bias units for generating driving voltages for driving the voltage-controlled oscillation units and supplying the driving voltages to the voltage-controlled oscillation units; and plural buffers for selectively outputting oscillation frequencies of the plural voltage-controlled oscillation units. The present invention implements the dual-band voltage-controlled oscillator through bias switching and output-buffer multiplexing, which brings an advantage of elimination of interference between output frequencies to enhance phase noise characteristics.

Abstract: An oscillator circuit can generate a periodic signal, and a frequency adjustment circuit can adjust the frequency of the periodic signal. The periodic signal may include phase jitter. In one aspect of the invention, the phase jitter may be mitigated by connecting other circuitry to the oscillator circuit and allowing the other circuitry to draw current. In one embodiment, the other circuitry is connected in parallel with the oscillator circuit. In one embodiment, the other circuitry is configured to draw greater current to mitigate more phase jitter and to draw less current to mitigate less phase jitter. In one embodiment, a greater portion of the other circuitry is connected to the oscillator circuit for higher frequencies and a lesser portion of the other circuitry is connected to the oscillator circuit for lower frequencies.

Abstract: A novel testing mechanism operative to test large capacitor arrays such as those used in a digitally controlled crystal oscillator (DCXO). The invention is adapted for use in DCXO circuits that employ dynamic element matching in their array decoding circuits. The invention combines the use of DEM during regular operation of the DCXO with a testing technique that greatly reduces the number of tests required. The invention tests the capacitors in the array on a row by row, wherein all the capacitors in a row are tested lumped together and treated as a single entity, which results in significantly reduced testing time. This permits the measurement of significantly higher frequency deviations due to the larger capacitances associated with an entire row of capacitors being tested.

Abstract: A phase locked loop circuit comprises a voltage controlled oscillator with a control input to which a variable control voltage is applied and a phase-frequency discriminator with an output connected to a loop filter to produce the control voltage. To provide the phase locked loop circuit with a low loop gain and a wide frequency pulling range, a plurality of discrete capacitors is associated with the voltage controlled oscillator. A switch array selectively activates and deactivates each of the capacitors in the voltage controlled oscillator. Each number of currently activated capacitors determines one out of a plurality of partial ranges of frequencies through which the oscillator can be tuned by a variation of the control voltage in a range between predetermined upper and lower control voltage limits. A total frequency range through which the oscillator can be tuned is divided thus into a plurality of partial frequency ranges each defined by a different number of activated capacitors.

Abstract: A loop filter for use in a frequency synthesizer provides improved spurious performance using switched capacitors. The loop filter includes a first switched capacitor having a first capacitance value and which is operable to charge to a first voltage corresponding to a current pulse indicative of a difference in phase or frequency between a reference signal and a feedback signal. The loop filter further includes a second switched capacitor having a second capacitance value and which is operable to charge to a second voltage from the first voltage and produce a control voltage based upon the second voltage. The loop filter has a bandwidth determined by a ratio of the second capacitance value to the first capacitance value.

Abstract: A method for controlling loop bandwidth of a phase locked loop is described. The method includes setting the loop bandwidth to a value, calculating at least one of a phase error and a frequency change that occur subsequent to any setting or adjusting of loop bandwidth, and adjusting the loop bandwidth based on at least one of the phase error and the frequency change.

Abstract: In a PLL frequency synthesizer outputting signals with different frequencies: voltage-controlled oscillators output the signals and have the oscillation frequencies controlled according to control voltages; a first switch selects one of the signals; a frequency divider generates a frequency-divided signal of the selected signal by use of a changeable frequency-division ratio; a phase comparator generates the phase difference between the frequency-divided signal and a reference signal; a second switch selects one of paths connected to low-pass filters; each low-pass filter is provided for one of the voltage-controlled oscillators, has a changeable time constant, and converts the phase difference into one of the control voltages; and a controller cyclically controls the first and second switches and the frequency divider so that the voltage-controlled oscillators continuously output the signals, and changes the changeable time constant of each low-pass filter after all of the signals become stable.

Abstract: A voltage-controlled oscillator includes (i) a first variable-capacity element, (ii) a resonance circuit whose resonance frequency changes in accordance with a control voltage applied to the first variable-capacity element, (iii) a second variable-capacity element connected in parallel with the first variable-capacity element, (iv) resonance frequency range switching means which switches the variation range of the resonance frequency of the resonance circuit by switching the capacity of the second variable-capacity element, and (v) a resonance frequency correction circuit which corrects the resonance frequency in such a manner as to prevent the ratio between resonance frequencies before and after the switching of the variation range from depending on the control voltage.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: In accordance with one aspect of the present invention, there is provided a method of calibrating an oscillator within a radio-frequency identification (RFID) circuit for use in an RFID tag. The oscillator has an oscillation frequency. A calibration value is stored within a non-volatile memory associated with the RFID circuit. The oscillator is calibrated in accordance with the calibration value. The storing of the calibration value includes recovering a reference frequency from a test signal supplied to the RFID circuit, calculating the calibration value to correspond to a difference between the recovered reference frequency and the oscillator frequency, and writing the calibration value to the non-volatile memory.

Abstract: An oscillator includes a plurality of varactor cells to receive a control signal to control a frequency of the oscillator. Each of the varactor cells includes a switch that includes a first terninal to receive the control signal and a second terminal such that the switch operates to control a capacitance of the varactor cell in response to a voltage between the first and second terminals. The oscillator includes a bias circuit to provide a different bias voltage to each second terminal and an amplifier that is coupled to the varactor cells to generate an oscillating signal.

Abstract: In various embodiments, the invention provides a discrete clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages.

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages.

Abstract: An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.

Abstract: An all-digital phase locked loop system for generating an oscillator output signal under control of a digital reference input. The system comprises a digitally controlled oscillator, a digital loop filter for generating a multiple bit digital control signal for the digitally controlled oscillator, a sigma-delta modulator for generating an additional 1-bit digital control signal for the digitally controlled oscillator, a digital divider dividing the oscillator output signal and providing a digital divided signal, and a digital adder with a first, additive input to which the digital reference input is applied and a second, subtractive input to which the digital divided signal is applied. The digital adder provides a digital output, the most significant bits of which are applied to an input of the digital loop filter and the least significant bits of which are applied to an input of the sigma-delta modulator. In the preferred embodiment, the sigma-delta modulator is of a two-stage MASH configuration.

Abstract: An automatic switching phase-locked loop (PLL) is disclosed, including a phase detector, a charge pump generating a pump current, a band selector receiving a control voltage to produce a band selection signal and a voltage setting signal based the control voltage, a loop filter generating the control voltage corresponding to the pump current and setting the control voltage based on the voltage setting signal, and a multi-band voltage control oscillator (VCO) coupled to the control voltage and the band selection signal, selecting one of a plurality of operating bands based on the band selection signal, and providing an output signal of a frequency within the selected operating band based on the control voltage.

Abstract: Tuning a radio oscillator frequency to a reference frequency is disclosed. A radio oscillator is set using a predetermined value loaded into an adjustment bit array. A highest selected bit is selected to be used in locating a final tuned value for the adjustment bit array. The final tuned value is determined by successively setting a selected bit starting with the highest selected bit in the adjustment bit array. And, the selected bit value in the final tuned value is determined using a measurement of the radio oscillator frequency and its relation to a reference frequency.

Abstract: When two oscillation signals are output from a common terminal through switching, to reduce attenuation of the oscillation signals, a dual-band oscillator includes a first oscillating transistor for generating an oscillation signal in a first frequency band; a first inductor for supplying power to a collector of the first oscillating transistor; a first switching element for switching the first oscillating transistor; a second oscillating transistor for generating an oscillation signal in a second frequency band; a second inductor for supplying power to a collector of the second oscillating transistor; a second switching element for switching the second oscillating transistor; and an output terminal for outputting the oscillation signal in the first frequency band or in the second frequency band. The first switching element is disposed between the first inductor and the output terminal, and the second switching element is disposed between the second inductor and the output terminal.

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages.

Abstract: In various embodiments, the invention provides a discrete clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages.

Abstract: A variable capacitance network is disclosed, comprising a plurality of capacitance arms connected in parallel with each other between first and second terminals of the network. Each capacitance arm has a varactor and a series capacitor in series with the varactor A control input applies a common control signal to the junctions between the varactors and their associated series capacitors, to allow for simultaneous control of each varactor.

Abstract: A variable capacitance network is disclosed, comprising a plurality of capacitance arms connected in parallel with each other between first and second terminals of the network. Each capacitance arm has a varactor and a series capacitor in series with the varactor A control input applies a common control signal to the junctions between the varactors and their associated series capacitors, to allow for simultaneous control of each varactor.

Abstract: A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.