Abstract: In a phase-lock-loop circuit a frequency detector measures a frequency error between an oscillatory signal and a synchronizing signal in alternate horizontal line periods for generating a frequency error indicative signal. The frequency error indicative signal is applied to an oscillator for correcting the frequency error in other alternate horizontal line periods in a manner to prevent frequency error measurement and correction from occurring in the same horizontal line period.

Abstract: A control circuit for use with a phase locked loop in a digital video receiver. The digital receiver accepts a serial digital input signal which can comprise composite or component video signals. The phase locked loop comprises a phase detector, a loop filter, and a voltage controlled oscillator (VCO) and includes a divide-by-two modulus divider coupled to the output of the VCO. The VCO has an oscillation frequency control port and the divider has a frequency select port. The control circuit includes an automatic fine tuning and frequency sweeping stage which is coupled to the output of the loop filter and the oscillation frequency control port. The tuning and frequency stage provides temperature drift correction for the VCO. In addition, the tuning and frequency stage "sweeps" the oscillation frequency of the VCO to aid in "locking" the phase locked loop to the phase or frequency of the input signal. Once locked, timing signals and digital data can be extracted from the input signal.

Abstract: PLL apparatus for generating an oscillatory signal phase locked to a component of a further signal comprises a variable oscillator for generating the oscillatory signal and a source of the further signal. A phase detector responsive to the oscillatory signal and to the component of the further signal, provides a phase error signal which is coupled to the variable oscillator via a limiter. Circuit means are provided for controlling the limiting level of the limiter. The dual limiting substantially improves the loop noise tolerance and reduces the loop sensitivity to occasional phase reversals of the component of the further signal. Additional enhancements to loop stability and noise immunity are provided by an unlock detector which detects and totalizes phase rotations in a selected area of a phase plane and by a phase wrap detector which maintains a lock indication during phase angle wrapping.

Abstract: A pilot signal detection circuit receives a supply of a pilot signal produced by frequency-modulation of a predetermined third frequency carrier signal by a first discrimination signal of a first frequency and a second discrimination signal of a second frequency, and makes a discrimination between the first discrimination signal and the second discrimination signal by whether a signal detected is of the first frequency or of the second frequency. The pilot signal detection circuit is constituted by first and second multiplying and filtering stages. The first multiplying and filtering stage includes first and second multipliers and first and second low-pass filters. The first and second multipliers multiply the pilot signal respectively with the first reference signal and the second reference signal, and produce respectively first and second multiplied signals.

Abstract: A phase locked loop (PLL) chain for locking audio sampling to serial digital component video timing has a deserializer that recovers a video sample clock signal from a serial digital video signal, the deserializer including a wide bandwidth PLL. A tracking filter in the form of a narrow bandwidth PLL having a low pass filter function reduces the jitter in the video sample clock signal to produce a stable reference clock signal. The stable reference clock signal is input to an audio sample clock generator to produce a stable audio sample clock signal for extracting audio data from the serial digital video signal.

Abstract: An oscillator, constructed partially within the confines of a monolithic integrated circuit, includes a differential-input, differential-output, differential amplifier within the monolithic integrated circuit. First and second resistive potential dividers located within the monolithic integrated circuit respectively divide the potentials appearing at the first and second output terminals of the differential amplifier in a predetermined ratio for respective application to the first and second input terminals of the differential amplifier, thereby respectively completing first and second direct-coupled regenerative feedback connections. An inductor located outside the monolithic integrated circuit is connected between the first and second input terminals of the differential amplifier and is anti-resonated by one or more capacitors, which may be located inside or outside the monolithic integrated circuit.

Abstract: A digital radio receiver generates coherent signals for synchronous detection without use of a phase-locked loop by employing an adaptive notch filter to cancel the desired signal. The cancelling signal is employed as the coherent signal for synchronous detection. The invention obtains faster locking to the desired signal, a wider capture range, and more efficient software coding in a digital signal processing receiver.

Abstract: This specification concerns signal processing apparatus for processing line synchronization pulses in a line synchronization signal that define an analog video signal line period. The apparatus comprises a phase locked loop (40) for generating a clock signal of a frequency that is a multiple of the line synchronization signal frequency. The phase locked loop (40) comprises a counter (100) for dividing the clock signal by said multiple. The apparatus further comprises logic (110,50) for resetting the counter (100) upon detection of a spurious pulse introducing a time interval into the line synchronization signal of less than the line period of the video signal. The apparatus is particularly useful in image processing systems for digitizing analog video signals that have been replayed via a conventional, domestic video tape player, and therefore may comprise spurious line sync pulses introduced by playback head skip.

Abstract: A phase-lock-loop circuit for generating a clock signal at a frequency higher than a horizontal frequency of a video signal includes a phase detector. The phase detector includes a flip-flop that is set when a horizontal sync pulse occurs. An output of a counter that provides frequency division is decoded for resetting the flip-flop in each horizontal period. Other than for the flip-flop, and for the counting stages of the counter, only combinational logic components are used for producing a phase error indicative signal that is coupled via a low-pass filter to a control input of an oscillator of the phase-lock-loop circuit.

Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: A digital FM stereo decoder uses the phase characteristics of linear phase FIR filters, together with a trignometric operation, to generate a 38 kHz subcarrier signal from a 19 kHz pilot. The subcarrier signal is mixed with the input composite signal from which the pilot has been removed to shift its L-R component to baseband; the linear phase FIR filters also maintain phase coherence between the subcarrier and the composite signals. A low distortion output is obtained without the use of a phase locked loop for the regeneration of the subcarrier signal.

Abstract: A digital radio receiver generates coherent signals for synchronous detection without use of a phase-locked loop by employing an adaptive notch filter to cancel the desired signal. The cancelling signal is employed as the coherent signal for synchronous detection. The invention obtains faster locking to the desired signal, a wider capture range, and more efficient software coding in a digital signal processing receiver.

Abstract: A horizontal sweep control synchronization circuit fixes the phase relationship between a horizontal synch pulse signal and a flyback signal by utilizing a first phase-lock-loop to fix the phase relationship between an oscillator signal, generated by the first loop, and the synch pulse signal, and a second loop to fix the phase relationship between the flyback signal and the oscillator signal. The first loop locks an edge of the synch pulse signal to the center of the oscillator signal, thereby allowing the synch pulse signal to remain locked to the oscillator signal during vertical retrace. The synchronization circuit only utilizes a single ramp forming circuit, thereby eliminating the jitter associated with multiple ramp forming circuits.

Abstract: A phase control circuit for controlling the relative phase of periodic components of two logic signals having the same frequency, and one of which periodic components has a pulse-duty factor different from 50:50, said circuit includes a signal source which provides a control signal for regulating the relative phase of the periodic components of said logic signals. The control signal has a first value for phase relationships in a predetermined range of values and a second value for phase relationships outside said range of values. A phase lock detector detects the lock status of the periodic components of the logic signals. Another signal source provides a third logic signal having a periodic component having the same frequency as the periodic component of each of the two logic signals and a pulse width substantially wider than that of the two logic signals.

Abstract: A television receiver is subject to certain operational conditions which result in poor, unreliable or unusable separated sync pulse signals. During such conditions the use of unsuitable sync signals for synchronization and the like is inhibited to prevent mis-triggering or spurious synchronization. A television receiver contains circuitry for extracting a sync signal, a voltage controlled oscillator (VCO) for generating a scanning signal, and a comparator comparing the scanning signal to the separated sync signal. A microprocessor is used to verify the separate sync signal for invalid or unusable signals and has an output activated during such conditions. The phase comparator has a current output coupled to a integrating capacitor or LPF which develops a varying positive or negative voltage to raise or lower the frequency of the VCO for scanning in phase with the separated sync.

Abstract: In a clock generator circuit, a zero hold circuit produces from a fixed clock signal a zero hold clock signal which is in phase with an external sync signal. A phase comparator circuit produces phase difference data indicating the phase difference between the external sync signal and an internal sync signal. A counter cleared by the external sync signal counts pulses of the zero hold clock signal to obtain count data. A memory receiving the phase difference data and the count data as its address input produces the internal sync signal when the count data is smaller than the number of pulses in one cycle of the external sync signal having no time-base variations, and a phase control signal determined by the phase difference data and the count data. A phase shifter shifts the phase of the zero hold clock according to the phase control signal to obtain a modified clock signal synchronized with the external sync signal.

Abstract: An oscillator control system includes a phase-locked loop having a programmable frequency divider operative within the loop. A switch is further included within the phase-locked loop to permit the loop to be open or closed in response to an input signal. A counter accumulates oscillator clock signal counts between each successive rising edge portion of the applied sync signal. A pair of shift registers sequentially store successive clock signal counts for the current and previous sync signal intervals. The output counts are compared for consistency by producing a difference signal therebetween which is utilized to control the phase-locked loop switch and close it once the consistency of sync signal has been established. The output counts of the shift registers are combined and used to provide a scaling factor which sets the frequency division of the programmable frequency divider within the phase-locked loop and properly scales the oscillator frequency to the sync signal frequency.

Abstract: A digital circuit arrangement for transforming an input digital picture signal onto a reference horizontal synchronizing signal raster derived from the system clock, which input digital picture signal is present at a system clock rate not locked with the input digital picture signal, which includes a correction memory (1), an interpolator/decimator (2), and a control member for the purpose of a transformation which is as insensitive to interference as possible.

Abstract: A circuit for detecting a square wave television signal in a television receiver includes an oscillator for generating the square wave signal and a phase locked loop (PLL) for synchronizing the square wave signal with the syn pulses of the televsion receiver. The circuit also includes an integrator for switching the output signal of the PLL to a frequency stable square wave signal when the syn pulses are absent and a Schmitt trigger for closing the PPL when a threshold value is reached. With the invention, the syn signals are sensed and a first switchable constant current source increases the output voltage of the integrator for a predetermined period of time when syn pulses are present during the first half of the square wave signal and discharges the integrator when syn signals are absent from the second half of the square wave signal.

Abstract: An adaptive oscillator control system for use in television receivers or monitors includes a phase locked loop together with a static phase error correction system which responds to long term error signals of significant magnitude within the phase locked loop to adjust the free-running frequency of the oscillator. An oscillator range control includes a processor having a plurality of established oscillator frequency ranges which are identified by oscillator range code numbers. A measuring counter and clock circuit cooperate to count the number of clock signals occurring during the horizontal sync reference signal period to establish a frequency reference number. A first frequency approximation is provided based upon the oscillator range code number or a known standard scan frequency. A frequency detector examines the oscillator output and provides a second frequency approximation to adjust the oscillator frequency until it falls within the appropriate frequency range.

Abstract: A multiple frequency scan oscillator control system includes a phase locked loop operative upon a scan oscillator to provide phase and frequency synchronization thereof to a periodic reference signal. A static phase error correction is operative to provide adjustment of the free-running or static frequency of the scan oscillator. An error amplifier includes a pair of intercoupled differential amplifier configurations one having a constant current source and the other having a frequency dependent current source which responds to a frequency dependent bias current to alter amplifier gain. A threshold detection circuit includes a differential amplifier pair coupled to a pair of switching circuits for establishing a threshold action in response to system error voltage to indicate large magnitude error voltages and signal the need for free-running frequency adjustment of the oscillator.

Abstract: A PLL system having a variable oscillator and apparatus for generating both phase and frequency error signals for controlling the variable oscillator, includes apparatus, responsive to the polarity of the frequency error signal, to selectively disconnect the frequency error signal from the variable oscillator when the PLL system approaches phase lock.

Abstract: An oscillation frequency control circuit which, while activating normal operation mode, initially computes a frequency control data corresponding to horizontal synchronizing signal by applying an interpolation on the basis of the frequency control data read from a memory and the frequency of horizontal synchronizing signal supplied to a display unit, and then, based on the computed result, automatically and internally controls the oscillation frequency of a horizontal oscillation circuit in accordance with the frequency of input horizontal synchronizing signal.

Abstract: An adaptive oscillator control system for use in television receivers or monitors includes a phase locked loop together with a static phase error correction system which responds to long term error signals of significant magnitude within the phase locked loop. An oscillator range control includes a processor establishing a plurality of oscillator frequency ranges identified by oscillator range code numbers. First and second frequency approximations are provided using the oscillator range code number. A confidence circuit examines the consistency of oscillator frequency maintenance within the appropriate frequency range and upon establishing the desired confidence level enables the phase locked loop to provide synchronization. Thereafter, a lock detector responds to the occurrence of frequency and phase lock by the phase lock loop to enable the static phase error corrector and deactivate the oscillator range control system.

Abstract: A static phase error responsive oscillator control includes a phase detector coupled to a source of horizontal synchronizing pulses, a low pass filter, an error amplifier, a voltage controlled oscillator having a frequency equal to a multiple of the horizontal scan frequency, and a corresponding frequency divider. A threshold detector responds to error signals in excess of predetermined upper and lower thresholds to indicate large magnitude frequency corrections. An averaging circuit determines the long term character of the large magnitude corrections to alter the free-running or static frequency of the oscillator. Once the free-running frequency is corrected, static phase error is substantially reduced or eliminated.

Abstract: A voltage controlled reference oscillator with a high Q and narrow tunability bandwidth produces an output oscillator frequency which is frequency divided by four alternative constants to produce four different clock frequencies for four different digital video standards, D1 component at 270 MHz, NTSC D2 composite at 143 MHz, PAL D2 composite at 177 MHz, and a proposed new composite video standard that is to operate at a 360 MHz clock rate. Automatic identification of which serial digital video is present is accomplished by having the clock generator produce a clock signal at the frequency required by one of the video formats while a phase lock loop attempts to lock onto the incoming signals at that frequency. If no lock occurs within a predetermined time interval, the clock generator is made to produce a clock signal at the frequency required by a different one of the video formats and the phase lock is attempted again. This is repeated until a lock is attained.

Abstract: A phase looped oscillating circuit includes a signal comparing device which can compare a plurality of different input signals with each other and emit a signal based on this comparison. The signal comparing device emits a control signal to a level converting device, a signal converting device is operatively connected to the level converting device. A signal from the converting device is received by an oscillating device and an oscillating signal is fed back to the signal comparing device via a divider. To compensate for fluctuation of an invertor in the signal converting device, the signal comparing device provides a fixed level signal stabilized at a 50% duty cycle. This stabilization also stabilizes electrical noises that may be present.

Abstract: A digital phase-locked loop comprises a phase comparator, a controllable oscillator whose output signal is compared with an input signal in the phase comparator, and a loop filter preceding the oscillator. The filter comprises a clocked input register for storing the last phase-measuring value of the phase comparator, and an integrator which comprises a clocked register whose output signal is fed back to the register input. When the input signal of the phase comparator is absent or disturbed, a switching signal is generated which immediately erases the input register in the loop filter and after whose appearance the register in the integrator of the loop filter is reset to zero within a limited number of clock cycles.

Abstract: In a high prrecision PLL circuit arrangement, a phase detecting circuit produces a detecting signal which is directly proportional to a phase difference between a horizontal synchronizing signal and a voltage-controlled oscillating signal. A loop filter circuit produces a delay signal for delaying a frequency control at a predetermined time constant in response to the detecting signal derived from the phase detecting circuit. A voltage-controlled oscillating circuit produces an oscillating signal having a frequency directly proportional to a voltage of the delay signal from the loop filter circuit. A non-linear circuit includes a non-linear element for changing at least one of an AC gain and a DC gain of the loop filter circuit, and prevents an erroneous capture phenomenon of the PLL circuit arrangement in response to the detecting signal from the phase detecting circuit.

Abstract: A circuit for generating a control signal includes a frequency-determining element (C3), a clock generator for generating a clock signal and a control circuit coupled to the clock generator for generating a control signal as a function of the magnitude of the voltage at the frequency-determining element and for applying the control signal to the frequency-determining element. The control circuit includes a sawtooth generator having a sawtooth frequency-determining element (C1) for converting the clock signal into a second signal having a constant slope as a function of time, and a storage element (C2) which produces a voltage that depends on the amplitude of the sawtooth signal.

Abstract: A synchronizing circuit including an oscillator, a phase discriminator having a first input coupled to an input terminal of the circuit for receiving an incoming synchronizing signal, a second input for receiving a signal derived from the oscillator and an output for applying a control signal to a control input of the oscillator for controlling the frequency and/or the phase of the oscillator signal. To ensure that the action of the circuit is not disturbed when no signal is present at the input terminal of the circuit, the circuit includes an auxiliary circuit for reducing the difference between the signal at the output of the phase discriminator and a reference, the auxiliary circuit being active in response to a synchronizing signal detector at the output of the phase discriminator in the absence of the incoming synchronizing signal and inactive in the opposite case.

Abstract: Video signal time scaling apparatus includes a gated oscillator enabled and disabled in synchronism with a line scanning rate and capable of generating an oscillatory signal which is other than a multiple of a line scanning rate. The phase of an oscillator output signal is compared to the phase of a reference signal a predetermined time after the oscillator is enabled. Phase coincidence indicates a correct oscillation frequency. Otherwise, the oscillator frequency is incremented or decremented until phase coincidence is achieved. The oscillator signal acts a READ clock for permitting a video signal to be read out of a line memory at a rate different than that at which the video signal was written into memory, thereby producing a time scaled output video signal.

Abstract: Horizontal synchronizing signals included in a video signal are inputted to a PLL circuit. A counter as a divider in the PLL circuit outputs signals which are synchronized with the horizontal synchronizing signals. A gate pulse generator counts the output pulses of counter and produces a control signal for controlling a phase comparator as one of elements of the PLL circuit. The operation of phase comparator is stopped in vertical intervals in accordance with the control signal so that the phase comparator is not affected by signals which are included in the video signal and are not synchronized with the horizontal synchronizing signals. Thus, the PLL circuit produces pulses which are synchronized with the horizontal synchronizing signals in a wide frequency range.

Abstract: An analog-to-digital converter converts an input analog video signal into a corresponding digital video signal. A first input terminal of a phase comparator receives the digital video signal. A loop filter receives an output signal from the phase comparator. A digital-to-analog converter converts an output signal from the loop filter into a corresponding analog control signal. First and second voltage-controlled oscillators generate oscillation output signals having different frequencies respectively which depend on the analog control signal. A switch selects and outputs either of the oscillation output signals. A frequency divider divides a frequency of the selected oscillation output signal into a value corresponding to a horizontal frequency. The frequency divider supplies its output signal to a second input terminal of the phase comparator.

Abstract: An AFC circuit using counters, flip-flops and logic gates produces a first pulse signal only when the phase of a VCO output signal lags the phase of a reference signal, and produces a second pulse signal only when the phase of the VCO output signal leads the phase of the reference signal. The first and second pulse signals control a switch to connect a first or a second constant current source to charge or discharge a filter circuit, to thereby produce a control voltage for the VCO. When the VCO output signal is in phase with the reference signal, the switch remains in a neutral position to hold a constant control voltage on the filter.

Abstract: The pixel clock of a system for receiving, sampling, and digitally storing the information contained in an analog sampled-data video signal is automatically synchronized and stabilized so that the received data is sampled by said system at or near the center of each successive received pixel period. A preset counter is employed to determine whether the receiving system clock is running at a predetermined number of pixel periods per horizontal sweep; any variation from the predetermined number is sensed and converted to a DC voltage level which is used to adjust the receiving system clock automatically to the correct number of periods per sweep. Synchronization of the receiving system clock is accomplished by triggering it with the sync pulse portions of the received video signal.

Abstract: A horizontal oscillation circuit which prevents damage of horizontal output transistors due to the rapid increase of horizontal deflection current at varying states of horizontal scan frequency or at the turning-on state of the power source. The horizontal oscillation circuit is provided with a speed up circuit which rapidly increases the control voltage supplied to a control voltage terminal of a voltage controlled oscillator. This provides increased speed of the oscillation frequency of the voltage controlled oscillator which does not slow in comparison to increasing speed of power source voltage. Consequently, the horizontal deflection current remains nearly constant, even at varying states of the horizontal scan frequency of the turning-on state of the power source, and damage to horizontal output transistors is avoided.

Abstract: 1. Circuitry for automatically switching the control speed of a phase-control circuit.2.1. The switching is, especially in conjunction with different signal sources employed with a television receiver, either difficult or possible only by reserving prescribed program locations. The advantage of the invention is that it becomes possible to switch over without great expenditure to the higher control speed only while necessary and back to the low speed when it no longer needs to be high.2.2. The invention is characterized in that a control circuit 12 increases the control speed, independent of whatever signal source is being employed to produce the picture, only during vertical flyback.2.3. The circuit can be employed in television receivers to reproduce both broadcast television signals and video signals from a recorder connected to the receiver.

Abstract: A circuit is arranged to derive the internal vertical synchronizing signals and field identification signals for a digital television signal. The circuit operates from the internal horizontal synchronizing signals and the separated external synchronizing signals and employs a sign inverter, an accumulator, an absolute value device, a comparator, a counter and AND gates, as well as an OR gate. These components, as coupled, produce the above-noted signals by digital generation and requires no subcircuits that are independent of the horizontal oscillator which horizontal oscillator is arranged in a phase lock loop.

Abstract: A synchronizing pulse signal generation device separates horizontal and vertical synchronizing signals from a video signal; generates a clock signal which is phase locked relative to the phase of the horizontal synchronizing signal; and generates, by using the clock signal, a synchronizing pulse signal which is phase locked relative to the vertical and horizontal synchronizing signals.

Abstract: A charge pump arrangement receives a digital error word representing an error signal and charges or discharges a capacitor in accordance with the sign of the error word by an amount that is proportional to the absolute value of the error word. The voltage produced in the capacitor is coupled to a frequency control terminal of a voltage controlled crystal oscillator that is used in, for example, a stereo decoder.

Abstract: A PLL circuit for a phase comparator, a low-pass filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider. A first control circuit is responsive to a discontinuous phase change of a reference signal of the PLL circuit for inhibiting the operation of the phase comparator or disconnecting the LPF from the phase comparator during a predetermined period so that the discontinuous phase change information is not transmitted through the LPF to the VCO. At the same time, a second control circuit resets the frequency divider by a pulse of the reference signal after the discontinuous phase change or applies a voltage corresponding to the discontinuous phase change to the VCO so that the output signal of the frequency divider is locked in phase to the reference signal after the discontinuous phase change. With the cooperation of the first and second control circuits, the PLL circuit quickly recovers its stable state after the discontinuous phase change of the reference signal.

Abstract: A clock signal generating circuit for a television receiver, which generates a composite synchronizing signal and a masking signal for controlling the operation of the circuit, the composite synchronizing signal including at least two partial signals.

Abstract: A controlled crystal oscillator of a stereo decoder of a television receiver using CMOS technology includes first, second and third differential emplifiers that produce corresponding first, second and third pairs of anti-phase output signals. The first and second differential amplifiers have variable gains that vary in opposing manners in accordance with a frequency control signal. The oscillatory signal of a crystal is coupled to corresponding input terminals of the three differential amplifiers such that the phase of the signal that is developed at the input terminal of the third differential amplifier is phase-shifted by approximately 90.degree. relative to those developed at the input terminals of the other two amplifiers. The three pairs of output signals are combined to form a single-ended oscillatory signal that is coupled back to the crystal to complete a regulative feedback path. The frequency of oscillation is determined in accordance with the frequency control signal.

Abstract: A recording apparatus receives a video signal containing a horizontal sync signal and a data signal comprised of a given number of image bit data arranged within each horizontal scanning period, and stores the number of image bit data in synchronization with the horizontal sync signal. A voltage-controlled oscillator produces in synchronization with the horizontal sync signal a frequency signal having a frequency higher than that of the sync signal. A divider frequency-divides the frequency signal by a given factor to produce a number of sampling pulses corresponding to the given number of image bit data. A data sampling circuit receives the data signal for sampling therefrom the number of image bit data in response to the corresponding sampling pulses to thereby write the image bit data into memory. Another divider frequency-divides the frequency signal by the product of the given factor and the given number to produce a feedback signal.

Abstract: A synchronization signal generator for NTSC, PAL or PALM system, capable of synchronizing by external signal; wherein horizontal information signal of external synchronization signal is processed through a stabilization circuit, and its output is frequency-divided by a counter, and then only such horizontal scanning information parts that makes phase relation of the horizontal synchronization signal and the color sub-carrier to a predetermined relation is extracted, and by resetting the counter based on the extracted information, to obtain SCH phase regulated signal.

Abstract: A deflection circuit for a video apparatus is capable of operating at different horizontal rate frequencies in response to the incoming video information rate. In one embodiment, the deflection oscillator input voltage is varied in a cyclical manner to vary the oscillator frequency. When the oscillator frequency corresponds to the frequency of the incoming video information, the input voltage is maintained to maintain the desired oscillator frequency. In an alternate embodiment, a frequency to voltage converter generates the desired oscillator input voltage in response to the incoming video information rate.

Abstract: An acquisition circuit in an improved phaselocked loop prevents cycle slipping by detecting and compensating an impending large phase difference between an independent incoming signal and a local comparison signal dependently related to a voltage controlled oscillator. A train of pulses is generated in progressively delayed phase relation with each cycle of the oscillator output signal. Additionally a threshold signal related to the independent signal is produced. In response to overlap of the threshold signal and individual ones of the pulses, a phase error signal is generated which controls a commutator to select individual ones of the pulses having a predetermined delay as the comparison signal, thereby generating a correcting control signal to phaselock the oscillator at a faster rate than the linear response time of a standard loop.

Abstract: An oscillating circuit using a phase locked loop (PLL) which includes a voltage controlled oscillator (VCO), a phase comparator, a low pass filter (LPF) and a phase extractor has a small circuit scale. Every repeat period of a reference pulse signal being provided to one input terminal of the phase comparator and having a frequency of 1/N times of an oscillating frequency of the VCO, one of leading edges of the output pulses of the VCO near a leading edge of the reference pulse signal is selectively extracting by the phase extractor. The extracted leading edge of the output pulse of the VCO is provided to another input terminal of the phase comparator and phase-compared with the leading edge of the reference pulse signal by the phase comparator. A phase error signal generated from the phase comparator is supplied through the LPF to the VCO as a control voltage thereof in order to stabilize the oscillating frequency.

Abstract: A line locking system for use with X-ray video imaging equipment comprising: a system oscillator, a divider for frequency dividing the output of the system oscillator to obtain a signal having a frequency that is an integer multiple of the line frequency, a comparator for comparing the phase of the integer multiple signal to the phase of the line signal and means for controlling the oscillator frequency responsive to the output of the comparator.