Abstract: A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.

Abstract: A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

Abstract: An embodiment of a communication system is provided, in which a high frequency oscillator generates a first high frequency signal upon receipt of no disable signal. The first high frequency signal is commonly shared by at least two modules. Each module coupled to the high frequency oscillator operates in either busy or idle mode, wherein the module operates at the first high frequency signal when in busy mode, and asserts a request signal when in idle mode. A disablement unit, coupled to the first and second modules, asserts the disable signal to the high frequency oscillator when all of the request signals are asserted, thereby forcing the high frequency oscillator to cease the generation of the first high frequency signal.

Abstract: Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

Abstract: A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).

Abstract: In a circuit and a method of clock interpolation, an input signal at a first frequency is processed and at least one output signal having a second frequency being a multiple of the first frequency of the input signal is output. The circuit is defined by the fact that the input signal is measured with respect to frequency and phase in a PLL frequency measuring circuit, and by the fact that the measured input signal is multiplied by at least one frequency multiplier and an oscillator that follows the frequency multiplier.

Abstract: A single side band (SSB) mixer includes an in-phase SSB mixer unit and a quadrature-phase SSB mixer unit. The in-phase SSB mixer unit generates an in-phase output current, and includes a first transformer load in which a portion of a quadrature-phase output current flows. The quadrature-phase SSB mixer unit generates the quadrature-phase output current, and includes a second transformer load in which a portion of the in-phase output current flows. The SSB mixer may be used in a wide frequency band without degrading frequency selectivity.

Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Abstract: A communications device (100) includes a frequency divider circuit (106) having a plurality of frequency division ratios. The device also includes at least one phase-lock loop (PLL) circuit (101, 102, 103, 104, 110, 112) coupled to at least a signal input of the frequency divider circuit. The PLL circuit includes a local oscillator (LO) circuit (104) including a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges. The device further includes at least one control input (105) coupled to at least the frequency divider circuit and the PLL circuit for specifying one of the plurality of VCOs and one of the plurality of frequency division ratios of the frequency divider circuit.

Abstract: Systems and methods for distributing a clock signal are disclosed. In some embodiments, systems for distributing a clock signal include a plurality of resonant oscillators, each comprising an inductor; and a differential clock grid that distributes the clock signal. The differential clock grid is coupled to the plurality of resonant oscillators and the clock signal, and the inductances of the inductors are configured such that a resonant frequency of the plurality of resonant oscillators is substantially equal to the frequency of the clock signal.

Abstract: A broadband integrated television receiver for receiving a standard antenna or cable input and outputting an analog composite video signal and composite audio signal is disclosed. The receiver employs an up-conversion mixer and a down-conversion mixer in series to produce an IF signal. An IF filter between the mixers performs coarse channel selection. The down-conversion mixer may be an image rejection mixer to provide additional filtering. The received RF television signals are converted to a standard 45.75 MHz IF signal for processing on-chip by additional circuitry.

Abstract: The invention proposes a simple method suitable for automatically locking frequency during USB data communication. Based on the soft plug/unplug concept proposed in the contents and the error handling mechanism defined in the USB specification, we can calibrate the clock frequency of the digitally controlled oscillator (DCO), through the token packets, to be within the acceptable frequency when USB device is attached to the host controller.

Abstract: LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract: A first serial transceiver has a reference clock, a first transmitter, and a first receiver. The first receiver includes (i) a phase detector, and (ii) a phase rotator. The phase rotator is driven by the reference clock. A first multiplexer is coupled to the first receiver. The first multiplexer receives the phase detector output and a control signal. When the first serial transceiver is in a test configuration, the first multiplexer passes the control signal to the phase rotator, thereby varying the frequency of the phase rotator output. A second multiplexer is coupled to the first transmitter. The second multiplexer receives a reference clock signal and the phase rotator output. When the first serial transceiver is in a test configuration, the second multiplexer passes the phase rotator output to the first transmitter. The first transmitter thereby transmits a serial data stream that varies in frequency from said reference clock.

Abstract: A system and method for ensuring proper synchronization of a plurality of frequency sources used in reception diversity-based radio reception. The frequency sources are concatenated in a synchronization loop, through which one frequency source having a high performance oscillator is configured as a master source. Through its oscillator, the master provides an internal synchronization signal that synchronizes all other sources, which have lower performance oscillators and are configured as slaves. Upon a failure in the master oscillator or in the synchronization loop, a slave source takes over as an alternative master source and provides its internal oscillator signal as an alternative synchronization signal to all other frequency sources.

Abstract: There is provided a frequency synthesizer including a multi-band voltage controlled oscillator having a plurality of voltage controlled oscillating cores outputting oscillation frequencies having different bands according to an input control voltage. Each of the voltage controlled oscillating cores outputs a frequency band divided into a plurality of bands, and the voltage controlled oscillating core operates by each of the divided bands, and one of the voltage controlled oscillating cores operates in one of the bands according to the control voltage. The frequency synthesizer further includes a comparator unit and an oscillation band-determining unit. The comparator unit compares the control voltage with a pre-set reference voltage range. The oscillation band-determining unit changes the band where the voltage controlled oscillating core operates into another one of the bands when the control voltage is out of the pre-set reference voltage range.

Abstract: A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.

Abstract: A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block.

Abstract: A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.

Abstract: A frequency generation unit (FGU) 100 includes a plurality of selectable voltage controlled oscillators (110) whose output frequencies are chosen in relationship with a predetermined intermediate frequency (IF) and frequency divider value (M) to provide multi-band frequency generation capability in a single communication device. A programmable reference divider (104), phase detector (174) and programmable charge pump (106) take an incoming reference frequency (120) and generate a charge pump output (124) to optimize the in-band phase noise in the FGU 100. A fixed loop filter (108) filters the charge pump output (124) to generate a control voltage (126) for the selectable VCOs (110). The desired frequency band is selected and enabled using control logic (128).

Abstract: A self-calibrating temperature compensated oscillator includes a monolithic structure having a first resonator, a second resonator, and a heating element to heat the first and second resonators. The temperature coefficient of the second resonator is substantially greater than the temperature coefficient of the first resonator. A first oscillator circuit operates with the first resonator and outputs a first oscillator output signal having a first oscillating frequency. A second oscillator circuit operates with the second resonator and outputs a second oscillator output signal having a second oscillating frequency. A temperature determining circuit determines the temperature of the first resonator using the second oscillating frequency. A temperature compensator provides a control signal to the first oscillator in response to the determined temperature to adjust the first oscillating frequency and maintain it at a desired operating frequency.

Abstract: The invention discloses a signal detection apparatus and method thereof for detecting whether an input signal of a set of serial ATA signals is an out of band (OOB) signal. The signal detection apparatus includes a calibrated clock generation device, a signal processor, and a logic determination device. The calibrated clock generation device generates a sampling clock signal according to a predetermined clock signal. The signal processor generates a plurality of detection results based on the sampling clock signal and the input signal. The logic determination device receives the plural of detection results and determines whether the input signal is the OOB signal.

Abstract: Systems, methods, and apparatuses including computer program products for oscillator calibration. In one aspect, a calibration module includes a monitor submodule that evaluates operation of a system to determine if the system is operating in a first mode or a second different mode, where the second clock source is not operating as expected in the second different mode; a calibration engine that determines a calibration value using the first clock source and the second clock source in response to the system operating in the first mode; and a register that stores the calibration value; where the calibration engine calibrates the first clock source using the calibration value and provides to the system the calibrated first clock source as a timing reference instead of the second clock source as the timing reference, in response to the system operating in the second different mode.

Abstract: A system and circuit for constructing a synchronous signal diagram from asynchronous sampled data provides a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.

Abstract: A multi-band electronic apparatus and method thereof is provided. The method comprises outputting a first output signal in the first band by a first voltage controlled oscillator according to a switch control signal and a control voltage, outputting a second output signal in the second band by a second voltage controlled oscillator according to the switch control signal and the control voltage, the second band being not completely overlapped by the first band, performing frequency division selectively on the first output signal or the second frequency divided signal according to the switch control signal, and outputting a first frequency divided signal, determining a phase difference between the first frequency divided signal and a reference signal to output a phase difference signal, outputting the control voltage according to the phase difference signal, and selectively driving the first or the second voltage controlled oscillators by the control voltage according to the switch control signal.

Abstract: Aspects of a method and system for frequency calibration of a voltage controlled ring oscillator are provided. In this regard, an oscillating voltage may be generated via a voltage controlled ring oscillator comprising a plurality of delay cells. Each of the plurality of delay cells may comprise a MOSFET differential pair coupled to a plurality of variable resistors. A frequency of oscillation and amplitude of the generated oscillating voltage may be controlled by controlling a resistance of the plurality of variable resistors. The frequency of oscillation and amplitude may be controlled via one or more digital control words generated by a baseband processor, a DSP, and/or a memory. The digital control words may comprise a control word for finely tuning the frequency of oscillation and amplitude and a control word for coarsely tuning the frequency of oscillation and amplitude.

Abstract: An apparatus for the phase synchronization of several devices, wherein one device is the master device and the other devices are slave devices, with a phase synchronization unit for every device, each of which has: a first controlled oscillator for producing a master reference signal, a first phase detector which, in order to control the first oscillator, compares the phase of a first comparison signal derived from the master reference signal with the phase of a second comparison signal derived from an auxiliary reference signal if the device is itself the master device and a second phase detector which, in order to control the first oscillator, compares the phase of a third comparison signal derived from the master reference signal with the phase of a reference signal coming from the phase synchronization unit of the master device if the device is not itself the master device but a slave device.

Abstract: The proposed apparatus and is used for signal generation by multiplexing signals such that there appears no glitches in an output signal. The present apparatus utilizes the knowledge of phase difference between input oscillator signals being multiplexed in order to provide a glitchless output signal. The apparatus comprises a first selection circuit configured to synchronize its response to a first control signal to a next determined event of one of input oscillator signals and convey an input oscillator signal to its output in response to the first control signal. The apparatus comprises a similar selection circuit for each input oscillator signal being multiplexed. Outputs of the selection circuits may be connected to a combining circuit which combines the outputs, thus providing the glitchless output signal.

Abstract: A frequency-control circuit, which is configured to receive a first signal having a first untuned frequency from a first oscillator, and to alter one or more pulses of the first signal to tune an output frequency of an output clock signal to have an average frequency at the desired target frequency. In some embodiments, the two oscillators of intentionally different frequencies are periodically switched at a duty factor, which is dependent on an absolute temperature, to generate a calibrated, precise, and temperature-stable clock.

Abstract: An integrated circuit comprises a film bulk acoustic resonator (FBAR) circuit that generates a reference frequency. A temperature sensor senses a temperature of the integrated circuit. Memory stores calibration parameters and selects at least one of the calibration parameters as a function of the sensed temperature. A phase locked loop module receives the reference signal, comprises a feedback loop having a feedback loop parameter and selectively adjusts the feedback loop parameter based on the at least one of the calibration parameters.

Abstract: In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L/N fRF. The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q)fRF, wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.

Abstract: A clock selection circuit and synthesizer that is capable of selecting an optimum clock signal from among a plurality of clock signals in a short time. A reference-clock counter counts clock pulses in an inputted reference clock signal (REF). A clock counter counts clock pulses in one of the plurality of clock signals which is selected by a selection unit and frequency-divided by a frequency divider. An instruction-signal output unit outputs a plurality of comparison-instruction signals during an interval in which a difference occurs between the counts of two of the plurality of clock signals having the closest frequencies. A comparison unit compares the count of the reference-clock counter and the count of the clock counter. The selection unit selects a clock signal by a binary search according to the result of the comparison.

Abstract: A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved.

Abstract: Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

Abstract: An oscillator includes a first oscillating portion that outputs a first oscillation signal having a first oscillation frequency through a first intermediate node to an output terminal, a mounting portion that includes an insulating layer and that mounts the first oscillating portion, a first line provided in the insulating layer and coupled between the first intermediate node and ground, a second line provided in the insulating layer and coupled between the first intermediate node and a power supply terminal, and a third line provided in the insulating layer and coupled between the first intermediate node and the output terminal.

Abstract: A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.

Abstract: An apparatus includes a stable local oscillator, which includes a first control loop. The first control loop includes a first voltage-controlled oscillator configured to generate a first output signal and a first phase-locked loop. The apparatus also includes a frequency up-converter configured to increase a frequency of the first output signal. The apparatus further includes a second control loop configured to receive the up-converted first output signal. The second control loop includes a second voltage-controlled oscillator configured to generate a second output signal and a second phase-locked loop. The second control loop may further include a mixer having a first input coupled to the frequency up-converter, a second input coupled to the second voltage-controlled oscillator, and an output coupled to the second phase-locked loop. A reference frequency source may be configured to generate a signal identifying a reference frequency and to provide that signal to the phase-locked loops.

Abstract: Provided is an oscillating apparatus that includes a plurality of variable frequency oscillators, each of which is provided in correspondence with a different oscillating band from one another; and a selection section that selects an oscillating signal that is from a variable frequency oscillator provided in correspondence with a designated oscillating band, from among the plurality of variable frequency oscillators, and outputs the selected oscillating signal, where the selection section includes a plurality of selectors connected in a tree structure, each selector outputting a selected one of inputted two or more oscillating signals, and each of the plurality of variable frequency oscillators is connected to a selector positioned at an end of the tree structure of the plurality of selectors.

Abstract: A semiconductor integrated circuit includes S PLLs (S is an integer satisfying S?2), and the (k?1)th PLL 12(k-1) (k is an integer satisfying 2?k?S) is connected to the kth PLL 12k in the test mode. In this manner, the examination of S PLLs can be performed in a single test, and thereby it can reduce the time needed to examine PLLs in the semiconductor integrated circuit having a plurality of PLLs.

Abstract: A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an input signal and a feedback signal. The digital loop filter generates a first control signal according to the first detection signal. The decision circuit generates a divisor value according to the first control signal. The fractional-N PLL generates an oscillation signal according to the divisor value and a reference signal. The frequency divider divides the oscillation signal to produce the feedback signal. The fractional-N PLL includes a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.

Abstract: A method for controlling a frequency output of a phase locked loop (PLL) is provided. The method includes providing digital control words to the PLL to discretely change at least one dividing factor within the PLL. The method further includes applying a time-varying control voltage to a voltage controlled oscillator. The method still further includes applying an output of the voltage controlled oscillator to the PLL as a reference frequency. The method further includes outputting a signal from the PLL, the signal varied in frequency based on one or more of the time-varying control voltage and the at least one dividing factor.

Abstract: A Voltage Controlled Oscillator (VCO) includes a plurality of oscillation units connected in cascade to form a chain; and a plurality of current source sections operatively connected to the oscillation units, the current source sections each being configured to control current provided to the oscillation units, wherein each of the current source sections includes: at least one fixed current source configured to perform a current control of a corresponding oscillation unit by using a fixed voltage; and at least one variable current source configured to perform a current control of the corresponding oscillation unit by using a variable voltage.

Abstract: A method, apparatus and system for acquiring land seismic data includes acquiring seismic data with a first autonomous seismic data acquisition unit and a second autonomous seismic data acquisition unit wherein each acquisition unit comprises a plurality of digitally controlled temperature-compensated crystal oscillators. Oscillator-based timing signals are acquired that are associated with the plurality of digitally controlled temperature-compensated crystal oscillators and a time correction is determined to apply to the seismic data acquired with the first autonomous seismic data acquisition unit. The time correction is determined using the oscillator-based timing signals from the first and second autonomous seismic data acquisition units.

Abstract: A communication system and an oscillation signal provision method based thereon are provided. In the communication system, a high frequency oscillator generates a first high frequency signal upon receipt of an enable signal. The first high frequency signal is commonly shared by a first module and a second module. The first module is coupled to the high frequency oscillator, operating in either busy or idle mode, wherein the first module operates at the first high frequency signal when in busy mode. The second module converts the first high frequency signal to a second high frequency signal and operates at the second high frequency signal when in busy mode.

Abstract: Synthesizers are configured with first and second phase-locked loops (PLL's). The first PLL is arranged to include a digitally-controlled oscillator (DCO) and to respond to an input signal to provide a reference signal with a plurality of selectable reference frequencies. The second PLL is arranged to include a voltage-controlled oscillator (VCO) to thereby provide output signals in response to the reference signal. This synthesizer structure is particularly effective when responding to a noisy input signal as may be the case, for example, in wireless communication systems that provide a network clock to transceivers through lengthy optical links.

Abstract: A radiation hard design for oscillator circuits and circuits having differential outputs is described. The design includes connecting or otherwise coupling outputs of these circuits to a passive polyphase filter. The passive polyphase filter provides four quadrature outputs that are free of glitches that may have occurred at the filter input.

Abstract: Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal having a frequency, a quantizer, a phase-frequency detector to generate an adjustment signal, and a charge pump to modify the control voltage. The example VCO includes several ring-oscillator stages, where each ring-oscillator stage includes several gain stages to provide several output currents based on a comparison of a control voltage and several corresponding threshold voltages. The example quantizer includes several comparators to generate digital signals based on the output currents. The example charge pump modifies the control voltage based on the digital signals and the adjustment signal, and includes several switching elements to increase or decrease current to the charge pump based on the digital signals.

Abstract: Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements.