Abstract: An input signal processing device includes an oscillator circuit, a signal processing circuit, and a control circuit. The oscillator circuit performs an oscillation operation to output a clock signal. The signal processing circuit operates based on the clock signal outputted from the oscillator circuit. The signal processing circuit performs a predetermined process to an input signal when a level of the input signal changes and outputs a signal after the predetermined process. The control circuit instructs the oscillator circuit to start the oscillation operation based on a level change of the input signal. The control circuit instructs the oscillator circuit to stop the oscillation operation when the signal processing circuit finishes the predetermined process.

Abstract: A circuit arrangement for generation of radio frequency output signals which form a broadband frequency ramp, with a reference oscillator, a phase detector, a loop filter, a VC oscillator for generating the output signals, a frequency divider, a step-down mixer and a local oscillator for generating a local oscillator signal. The reference oscillator, the phase detector, the loop filter, the VC oscillator, the frequency divider and the step-down mixer belong to a phase-locking loop. The frequency divider and the step-down mixer are in the feedback path of the phase-locking loop. The step-down mixer mixes the output signals and the local oscillator signal. The frequency of the output signal is adjustable by varying the division ratio of the frequency divider. Characteristics of the output signal are improved using the adjustable frequency of the local oscillator signal.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal.

Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.

Abstract: A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.

Abstract: An ultrasonic generator is provided, in which the control system can easily be changed in accordance with a cleaning application and a cleaning process. The ultrasonic generator according to the present invention, which causes an ultrasonic transducer to oscillate a signal for ultrasonic vibration, includes a programmable multiple control circuit having a signal generation circuit for generating a signal, and an output adjustment circuit for adjusting the output of the signal from the programmable multiple control circuit, wherein the programmable multiple control circuit has a power control circuit electrically connected to the output adjustment circuit, a phase comparison circuit electrically connected to the output adjustment circuit, a frequency control circuit electrically connected to the phase comparison circuit, and a signal modulation circuit electrically connected to the frequency control circuit via the signal generation circuit.

Abstract: A digitally controlled oscillator includes a ring oscillator and a first supplementary circuit. The ring oscillator is coupled to a supply voltage and generates a signal oscillated at an oscillating frequency. The oscillating frequency is controlled by a digital code and further varies with a supply voltage drift in a first direction. The first supplementary circuit is coupled to the ring oscillator and facilitates the oscillating frequency to vary with the supply voltage drift in a second direction reverse to the first direction.

Abstract: An all-digital frequency detector is provided, which includes a phase-frequency detector receiving a reference clock and an input clock, two sample/hold circuits sampling the phase-frequency detector outputs responsive to a ninety-degree phase shifted reference clock and a ninety-degree phase shifted input clock, a plurality of logical operators to generate an output frequency detection signal and a output clock responsive to the difference between the reference clock and the input clock.

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract: In a circuit having a runaway detector coupled to a phase-locked loop (PLL), the PLL may include a loop filter to receive a control voltage within the PLL and provide a filtered control voltage and a voltage-controlled oscillator to receive the filtered control voltage and provide an output clock signal. The runaway detector may provide a control signal for adjusting the filtered control voltage in response to a predetermined PLL condition. The runaway detector may include a comparator to receive a first and second input voltages, where the second input voltage is based on the output clock signal. When the predetermined PLL condition exists, the runaway detector may be active to adjust the filtered control voltage, thereby enabling the PLL to return to a lock condition.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: An apparatus for generating an oscillating output signal includes an inductive-capacitive (LC) circuit and a current tuning circuit. The LC circuit includes a primary inductor and a varactor coupled to the primary inductor. A capacitance of the varactor is responsive to a voltage at a control input of the varactor. The current tuning circuit includes a secondary inductor and a current driving circuit coupled to the secondary inductor. The current driving circuit is responsive to a current at a control input of the current driving circuit. An effective inductance of the primary inductor is adjustable via magnetic coupling to the secondary inductor, and a frequency of the oscillating output signal is responsive to the effective inductance of the primary inductor and to the capacitance of the varactor.

Abstract: Tunable injection locked (IL) dividers having enhanced locking range, good phase noise performance, and low power consumption are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes an oscillator and at least one IL divider. The oscillator provides an oscillator signal at a first frequency. The at least one IL divider receives the oscillator signal and provides an output signal at a second frequency, which is related to the first frequency by an overall divider ratio for the IL divider(s). Each IL divider may be calibrated based on a target frequency of that IL divider. Each IL divider may be calibrated (e.g., by tuning at least one adjustable capacitor) to obtain an oscillation frequency within a predetermined tolerance of the target frequency of that IL divider. The oscillator may be calibrated based on a target oscillation frequency of the oscillator.

Abstract: A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.

Abstract: A digital ring oscillator outputting a toggled clock signal. The clock signal is generated by a plurality of electronic cells that are arranged in series. At least one of the plurality of electronic cells receives a feedback of the clock signal. Control signals are received at an input for the plurality of electronic cells. Each electronic cell includes a first logic gate, a second logic gate, and an inverted logic gate coupled between the first logic gate and the second logic gate. For each electronic cell, a respective control signal controls whether an output signal received from the first logic gate of a preceding electronic cell is transferred through the first logic gate to the first logic gate in a succeeding electronic cell, or is inverted and transferred through the second logic gate to the second logic gate in a preceding electronic cell, based on the control signal.

Abstract: Embodiments of the present invention provide a temperature compensation method and a crystal oscillator, where the crystal oscillator includes a crystal oscillation circuit unit, a temperature sensor unit, an oscillation controlling unit, a relative temperature calculating unit, and a temperature compensating unit. The temperature sensor unit measures a measured temperature of the crystal oscillation circuit unit; the relative temperature calculating unit obtains a temperature difference between the measured temperature and a reference temperature; the temperature compensating unit obtains a temperature compensation value corresponding to the temperature difference from a temperature-frequency curve; and the oscillation controlling unit generates a frequency control signal, according to a frequency tracked by a communications AFC device and the temperature compensation value, thereby controlling a frequency of the crystal oscillation circuit unit to work on the tracked frequency.

Abstract: In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

Abstract: A ring oscillator includes (2N+1) inverting delay circuit cells, and each delay circuit cell has an input port and an output port, where N is an integer larger than zero. Each of these (2N+1) inverting delay circuit cells receives a control voltage, and all of the (2N+1) inverting delay circuit cells are electrically connected with each other in series. Furthermore, the input port of one of the (2N+1) inverting delay circuit cells is electrically connected with the output port of an adjacent delay circuit cell of the (2N+1) inverting delay circuit cells.

Abstract: A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal.

Abstract: A current reuse voltage controlled oscillator with improved differential output is disclosed. In an exemplary embodiment, an apparatus includes a PMOS transistor and an NMOS transistor coupled together for current reuse and configured to provide differential oscillator outputs. The apparatus also includes a common mode rejection (CMR) circuit coupled between the PMOS and the NMOS transistors, the CMR circuit includes an inductor having a least one tap that can be selectively coupled to a ground to reduce common mode signals at the differential oscillator outputs.

Abstract: In some embodiments, provided are calibration techniques for measuring mismatches between TDL delay stage elements, and in some cases, then compensating for the mismatches to minimize performance degradation.

Abstract: The embodiments described herein provide a voltage controlled oscillator (VCO). The VCO may include, but is not limited to a voltage-to-current converter configured to receive a control voltage and to convert the control voltage to a current, a current bias circuit coupled to the voltage-to-current converter and configured to receive frequency band select digital inputs and to bias the current generated by the voltage-to-current converter based upon the band select inputs, and a ring oscillator coupled to receive the biased current and to output an oscillating signal based upon the biased current.

Abstract: Methods and apparatus for calibration and temperature compensation of oscillators having mechanical resonators are described. The method(s) may involve measuring the frequency of the oscillator at multiple discrete temperatures and adjusting compensation circuitry of the oscillator at the various temperatures. The compensation circuitry may include multiple programmable elements which may independently adjust the frequency behavior of the oscillator at a respective temperature. Thus, adjustment of the frequency behavior of the oscillator at one temperature may not alter the frequency behavior at a second temperature.

Abstract: A phase locked loop comprising: an oscillator for generating an output signal of a frequency that is dependent on an input to the oscillator; sampling means for generating a sequence of digital values representing the output of the oscillator at moments synchronized with a reference frequency; a difference unit for generating a feedback signal representing the difference between successive values in the sequence; and an integrator for integrating the difference between the feedback signal and a signal of a desired output frequency; the signal input to the oscillator being dependent on the output of the integrator.

Abstract: In one embodiment, the present invention includes a method of correcting the frequency of a crystal oscillator. The method includes establishing an operating baseline for the crystal oscillator using a frequency reference, storing information in memory, and adjusting the frequency according to the information. The information corresponds to the operating baseline. Adjusting the frequency occurs in response to a power-on event and the absence of the frequency reference.

Abstract: Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing.

Abstract: A frequency error calculator circuit calculates the frequency error in a basic clock based on the basic clock and on a reference clock having a frequency higher than the basic clock. An operation clock generator circuit outputs an operation clock whose error has been corrected based on the frequency error calculated by the frequency error calculator circuit. An ON/OFF control circuit outputs an ON/OFF control signal that specifies the calculation timing that the frequency error calculator circuit calculates the frequency error of the basic clock based on the frequency error calculated by the frequency error calculator circuit.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: A modulation section including a feedback circuit configured to conduct feedback control of an output signal from a voltage controlled oscillator based on an inputted modulation signal, and a feed-forward circuit configured to calibrate the modulation signal and outputting the calibrated modulation signal to the voltage controlled oscillator; a signal output section configured to output, to the modulation section, a predetermined reference signal instead of the modulation signal when a calibration is conducted; and a gain correction section configured to, in a state where the feedback circuit is forming an open loop, calculate a frequency transition amount of the reference signal outputted by the voltage controlled oscillator, and correct a gain used for calibrating the modulation signal at the feed-forward circuit based on the calculated frequency transition amount.

Abstract: Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function: thereby providing two simultaneous operations being determined in place of the one differential function.

Abstract: An automatic self-calibrated oscillation method and an apparatus using the same are provided. After a static time tuning (STT) table and a run time tuning (RTT) table have been established, the apparatus converts an output clock signal to generate a current RTT value at every predefined time and then compares the current RTT value with a reference RTT value generated in response to a STT value of the STT table, or with an interpolated result generated in response to the reference RTT value to generate a deviation value. Thus, through the deviation value, the output clock signal may be calibrated to address the target frequency without the assistance of external reference clock unit or locked loop unit after the STT table and the RTT table are established.

Abstract: A method and apparatus is disclosed for voltage-controlled oscillator selection in a multi-mode system having multiple voltage-controlled oscillators. Part of oscillator selection is a calibration operation that utilizes maximum and minimum capacitance limits for a voltage-controlled oscillator, which translates to a frequency range, to calculate overlap regions. Overlap regions comprise frequency ranges that overlap such that the overlap region may be generated by two voltage-controlled oscillators with adjacent frequency ranges. One voltage-controlled oscillator selection routine comprises a real time voltage-controlled oscillator calibration and selection routine that executes every time the system requests a new frequency. Another selection routine comprises a start-up routine that executes only at power up or periodically.

Abstract: An all-digital frequency detector is provided, which includes a phase-frequency detector receiving a reference clock and an input clock, two sample/hold circuits sampling the phase-frequency detector outputs responsive to a ninety-degree phase shifted reference clock and a ninety-degree phase shifted input clock, a plurality of logical operators to generate an output frequency detection signal and a output clock responsive to the difference between the reference clock and the input clock.

Abstract: An oscillator includes a nominal frequency output unit, a frequency adjustment amount output unit, a gain output unit, a multiplier, and an adder. The nominal frequency output unit is configured to output a first digital value corresponding to the nominal frequency. The frequency adjustment amount output unit is configured to output a second digital value corresponding to a rate of frequency in order to set a frequency adjustment amount with respect to the nominal frequency using the rate of frequency. The gain output unit is configured to output a third digital value corresponding to a gain to be multiplied by the second digital value. The multiplier is configured to multiply the second digital value by the third digital value, thus outputting a fourth digital value. The adder adds the first digital value and the fourth digital value to output the added result as a setting signal of frequency.

Abstract: One aspect of the present invention includes a reference current generator circuit. The circuit includes a bias circuit configured to generate a reference current along a first current path and a second current along a second current path. The reference current and the second current can be proportional. The circuit also includes a first pair of transistors connected in series and configured to conduct the reference current in the first current path. The circuit further includes a second pair of transistors connected in series and configured to conduct the second current in the second current path. The second pair of transistors can be coupled to the first pair of transistors to provide a collective resistance value of the second pair of transistors that is proportional to temperature.

Abstract: A local oscillation generator (LO-GEN) maintains a fixed bandwidth using a voltage controlled oscillator (VCO) calibration module and gain calibration module that together compensate for variations in the VCO gain based on the oscillation frequency. During an open loop calibration of the LO-GEN, the VCO calibration module programs the VCO gain to an initial coarse value based on the oscillation frequency and then the gain calibration module adjusts the charge pump current to compensate for VCO gain changes.

Abstract: A constant-temperature piezoelectric oscillator includes: a piezoelectric vibrator; an oscillation circuit; a frequency voltage control circuit; a temperature control section; and an arithmetic circuit, wherein the temperature control section includes a temperature-sensitive element, a heating element, and a temperature control circuit, the frequency voltage control circuit includes a voltage-controlled capacitance circuit capable of varying the capacitance value in accordance with the voltage, and a compensation voltage generation circuit, and the arithmetic circuit makes the compensation voltage generation circuit generate a voltage for compensating a frequency deviation due to a temperature difference between zero temperature coefficient temperature Tp of the piezoelectric vibrator and setting temperature Tov of the temperature control section based on a frequency-temperature characteristic compensation amount approximate formula adapted to compensate the frequency deviation, and then applies the voltage t

Abstract: A synthesizer architecture, responsive to a low noise reference signal from a discrete oscillator, provides a continuous periodic output with a period that is a fractional multiple of the low noise reference signal. One exemplary embodiment includes a phase detector providing a control signal to a selected one of a plurality of integrated voltage controlled oscillators (VCO), wherein the phase detector is a sub-harmonic continuous time sampling phase detector. Another exemplary embodiment includes a continuous fractional divider input to the phase detector in response to an output of the selected VCO. Yet another exemplary embodiment comprises an injection locked ring oscillator responsive to the low noise narrow band variable reference signal with a fractional output period.

Abstract: There is provided a differential ring oscillation circuit including a differential ring oscillation unit in which delay circuits, to which signals of 2 phases are input, and which delay and output the input signals of 2 phases, are connected at even stages in a ring form, first and second common-mode level detection units that detect that the input signals of 2 phases of one delay circuit at an even stage of the differential ring oscillation unit and the input signals of 2 phases of one delay circuit at an odd stage of the differential ring oscillation unit are at same predetermined levels, respectively, and first and second switches that set, to specific potentials, one of the output signals of 2 phases of the delay circuit delaying the input signals of 2 phases, when the first and second common-mode level detection units detect the same predetermined levels, respectively.

Abstract: Tunable injection locked (IL) dividers having enhanced locking range, good phase noise performance, and low power consumption are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes an oscillator and at least one IL divider. The oscillator provides an oscillator signal at a first frequency. The at least one IL divider receives the oscillator signal and provides an output signal at a second frequency, which is related to the first frequency by an overall divider ratio for the IL divider(s). Each IL divider may be calibrated based on a target frequency of that IL divider. Each IL divider may be calibrated (e.g., by tuning at least one adjustable capacitor) to obtain an oscillation frequency within a predetermined tolerance of the target frequency of that IL divider. The oscillator may be calibrated based on a target oscillation frequency of the oscillator.

Abstract: A clock generator and generating method, and a mobile communication device using the clock generator. A clock generator comprises a first accumulator, an oscillating signal generating circuit and a frequency adjustment circuit. The oscillating signal generating circuit generates a first oscillating signal and adjusts a frequency of the first oscillating signal according to a first overflow output signal of the first accumulator. The frequency adjustment circuit generates a frequency control value according to the first oscillating signal and a reference oscillating signal. The first accumulator accumulates the frequency control value according to the first oscillating signal to generate the first overflow output signal.

Abstract: Mechanical resonating structures are used to generate signals having a target frequency with low noise. The mechanical resonating structures may generate output signals containing multiple frequencies which may be suitably combined with one or more additional signals to generate the target frequency with low noise. The mechanical resonating structures may be used to form oscillators.

Abstract: There is provided a signal processing apparatus including an oscillating unit having a division ratio of an integer that performs oscillation at a predetermined oscillation frequency, a frequency transforming unit that transforms a frequency of a signal of a processing target using a signal of the oscillation frequency obtained by the oscillation of the oscillating unit, and a correcting unit that corrects an error of the frequency of the signal of the processing target transformed by the frequency transforming unit based on an error of the oscillation frequency.

Abstract: An oscillator arrangement comprises a current controlled oscillator, a frequency to voltage converter, and an operational amplifier. The current controlled oscillator is adapted to generate a clock signal based on a control voltage signal, wherein the generated clock signal is supplied to the frequency to voltage converter. The frequency to voltage converter is adapted to generate an output voltage signal based on the generated clock signal and based on a supply voltage signal.

Abstract: Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.

Abstract: Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter.

Abstract: A method and a system are described for controlling and stabilizing in time, as temperature changes, the frequency of a signal generated by a controllable oscillator (3), the method includes the steps of: measuring the frequency of the signal generated by the controllable oscillator (3) by using a first signal, whose duration is proportional to the length of a delay line (5) includes at least a first (7) and a second (9) delay line portions arranged in series and having a first (L1) and a second (L2) lengths, respectively; applying a frequency correction to the signal generated by the controllable oscillator (3) if the difference in frequency between the signal and the desired frequency value exceeds a predetermined threshold; providing the first portion of the delay line (5) by coupling a conductive material to a first dielectric material having a first negative gradient of its dielectric constant as a function of temperature; providing the second portion (9) of the delay line (5) by coupling or another cond

Abstract: According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.

Abstract: A limiter circuit in a voltage controlled oscillator (VCO) includes a first control circuit, a second control circuit and a driving circuit having a pull-up transistor and a pull-down transistor. The first control circuit generates a first driving control signal for controlling the pull-up transistor based on an AC input signal and a first DC bias voltage. The second control circuit generates a second driving control signal for controlling the pull-down transistor based on the AC input signal and a second DC bias voltage. The driving circuit generates an output signal based on the first driving control signal and the second driving control signal. The output signal swings between a first voltage at the pull-up transistor and a second voltage at the pull-down transistor.

Abstract: An injection locked pulsed oscillator includes a voltage controlled oscillator (VCO) responsive to an injection signal. The injection locked pulsed oscillator includes at least one enable circuit responsive to a first enable signal to enable output pulses from the VCO. The injection locked pulsed oscillator also includes timing circuit responsive to a pulse repetition frequency signal and is configured to provide the injection signal to phase lock the VCO and provide the first enable signal delayed from the injection signal to shape a width of the output pulses from the VCO.