Abstract: Device and method for temperature compensation in a clock oscillator using quartz crystals, which integrates dual crystal oscillators. The minimal power consumption is achieved through an efficient use of a processor in charge of the synchronization of the two oscillators. The invention is particularly adapted for the provision of a precise reference clock in portable radiolocalization devices.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.

Abstract: An integrated circuit comprises an oscillator that generates an oscillator signal. A first counter generates a first count based on transitions of the oscillator signal. A first circuit generates a match signal based on the first count and a reference count. A second counter generates a second count that is initialized at a starting count and adjusts the second count based on transitions of a reference clock signal. An output circuit outputs an oscillator speed based on the second count and the match signal. The oscillator speed is defined by a range that is independent of a frequency of the reference clock signal.

Abstract: A technique for oscillator stability and accuracy verification involves analysis of parameters from a plurality of phase locked loops (PLLs). During testing, each PLL receives a stable reference clock to identify variations in its clock oscillator. Mathematical calculations on the data extracted from each PLL permit identification of clock oscillators having undesirable timing characteristics. Remedial measures may then be implemented to correct problems with any faulty oscillators.

Abstract: Circuitry for determining timing characteristics, for example, access time, setup time, hold time, recovery time and removal time, of as-manufactured digital circuit elements, such as latches, flip-flops and memory cells. Each element under test is embodied in variable-loop-path ring oscillator circuitry that includes multiple ring-oscillator loop paths, each of which differs from the other(s) in terms of inclusion and exclusion of ones of a data input and a data output of the element under test. Each loop path is caused to oscillate at each of a plurality of frequencies, and data regarding the oscillation frequencies is used to determine one or more timing characteristics of the element under test. The variable-loop-path ring oscillator circuitry can be incorporated into a variety of test systems, including automated testing equipment, and built-in self test structures and can be used in performing model-to-hardware correlation of library cells that include testable as-manufactured digital circuit elements.

Abstract: An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency.

Abstract: An apparatus includes a phase locked loop (PLL). The phase locked loop (PLL) has coarse tuning (CT), fine tuning-integer (FT-i), fine tuning fractional (FT-f), frequency modulator tuning-fractional (FMT-f), and narrowband (NB) modes of operation.

Abstract: Embodiments disclosed herein may provide circuits having two or more different supplies to separately power analog and digital components in a circuit. In some embodiments, circuits such as PLLs may be provided with adjustable analog supplies. Other embodiments may be disclosed and/or claimed herein.

Abstract: An aging compensation method for an oscillator circuit device, in which the oscillator circuit device receives a control voltage from an application end, and outputs a clock signal with a predetermined frequency in response to the control voltage, includes the steps of: a) inspecting the control voltage from the application end to obtain a first value thereof; b) after a predetermined time period has elapsed, inspecting the control voltage from the application end to obtain a second value thereof; c) determining whether there is a difference between the first and second values of the control voltage; d) if it is determined that there is a difference, performing compensation on the value of the control voltage based on the difference; and e) repeating steps b) through d).

Abstract: A crystal oscillator tester includes first and second test pins, first and second transistors, an indicator, a first diode, and first-third capacitors. The first test pin is connected to a power source. The collector of the first transistor is connected to the first test pin. The base of the second transistor is connected to the second test pin. The emitter of the first transistor is grounded via the indicator. The base of the first transistor is connected to the cathode of the first diode. The anode of the first diode is connected to the first test pin via the first and second capacitors one by one in series. The emitter of the second transistor is connected to a node between the first and second capacitors. The collector of the second transistor is grounded. The third capacitor is connected between the base and emitter of the second transistor.

Abstract: A phase-locked method includes: generating a selection signal according to a detection result of a phase/frequency detector (PFD) of a phase-locked loop (PLL); generating a plurality of oscillation signals according to at least a first oscillation signal generated by the PLL, wherein the plurality of oscillation signals respectively correspond to a plurality of phases; and from the plurality of oscillation signals, selecting an oscillation signal as an output signal of the PLL according to the selection signal.

Abstract: A semiconductor integrated circuit includes S PLLs (S is an integer satisfying S?2), and the (k?1)th PLL 12(k-1) (k is an integer satisfying 2?k?S) is connected to the kth PLL 12k in the test mode. In this manner, the examination of S PLLs can be performed in a single test, and thereby it can reduce the time needed to examine PLLs in the semiconductor integrated circuit having a plurality of PLLs.

Abstract: Exemplary embodiments of the invention provide a reference harmonic oscillator integrated circuit having three or more terminals, with systems and methods for calibrating the harmonic oscillator to a selected first frequency using a limited number of terminals. An exemplary apparatus comprises: a reference harmonic oscillator, a first terminal to receive a supply voltage, a second terminal to receive a ground potential, a third terminal to provide an output signal having an output frequency, and may also include a fourth terminal. One of the first, second, third or fourth terminals is further adapted for input of a calibration of the first frequency. The exemplary apparatus may enter calibration and testing modes in response to various commands such as a calibration mode signal, and may also be configured through one of the terminals for output frequency selection, spread-spectrum output, and output voltage levels.

Abstract: The crystal oscillator for surface mounting includes: a container body having first and second recesses on both principal surfaces thereof; a crystal blank hermetically encapsulated within the first recess; and an IC chip in which an oscillation circuit using the crystal blank is integrated, the IC chip being accommodated within the second recess. The IC chip is provided with a plurality of IC terminals including a pair of crystal terminals used for electrical connection with the crystal blank. A plurality of mounting electrodes to which the IC terminals are connected through flip-chip bonding are formed on a bottom surface of the second recess in correspondence with the IC terminals. A pair of mounting electrodes corresponding to the pair of crystal terminals are electrically connected to the crystal blank and also formed as a pair of dual-purpose electrodes having greater areas than the other mounting electrodes.

Abstract: The present invention discloses a two-step VCO calibration method. The two-step VCO calibration method, comprising power-on calibration, used to provide a coarse VCO tuning; real-time calibration, real-time calibration, used to provide a fine VCO tuning according to the loaded result of said power-on calibration. The two-step VCO calibration method according to the present invention can cover all the variation of process and temperature and gain the advantages of shorter calibration time, smaller gain of VCO, pretty smaller size of passive loop filter and less operating power consumption.

Abstract: A configurable ring oscillator is operated in a first configuration so that an oscillating signal passes from a first node to a second node through a first signal path. A first measurement of an operational characteristic is made. The ring oscillator is operated in a second configuration where an oscillating signal passes from the first node to the second node through a second signal path. A second measurement is made. The first and second measurements are used to determine a circuit simulator parameter. If the first path has little interconnect and the second path has substantial interconnect, then the effect on circuit operation due to interconnect loading can be isolated from the effects on circuit operation due to variations in transistor performance. If the first and second paths are laid out to be identical, then the first and second measurements are usable to determine a circuit simulator mismatch parameter.

Abstract: Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed.

Abstract: A programmable reference-less oscillator provides a wide range of programmable output frequencies. The programmable reference-less oscillator is implemented on an integrated circuit that includes a free running controllable oscillator circuit such as a voltage controlled oscillator (VCO), a programmable divider circuit coupled to divide an output of the controllable oscillator circuit according to a programmable divide value. A non-volatile storage stores the programmed divide value and a control word that controls the output of the controllable oscillator circuit. The control word provides a calibration capability to achieve a desired output frequency in conjunction with the programmable divider circuit. Open loop temperature compensation is achieved by adjusting the control word according to a temperature detected by a temperature sensor on the integrated circuit. Additional clock accuracy may be achieved by adjusting the control word for process as well as temperature.

Abstract: A DPLL circuit is provided for making it possible to inhibit an initial frequency offset during holdover. The DPLL circuit includes a slave oscillator for generating a frequency signal corresponding to the size of a control signal value; a phase difference detection circuit for detecting the difference in phase between the output of said slave oscillator and the inputted reference clock, and outputting a digital signal of the prescribed number of bits corresponding to said detected phase difference; and a holdover unit for generating a correction value based on the output of said phase difference detection circuit, wherein when the holdover is detected, said holdover unit periodically adds the correction value to the output of said phase difference detection circuit to obtain a control value for said slave oscillator.

Abstract: A crystal oscillator tester includes first and second test pins, first and second transistors, an indicator, a first diode, and first-third capacitors. The first test pin is connected to a power source. The collector of the first transistor is connected to the first test pin. The base of the second transistor is connected to the second test pin. The emitter of the first transistor is grounded via the indicator. The base of the first transistor is connected to the cathode of the first diode. The anode of the first diode is connected to the first test pin via the first and second capacitors one by one in series. The emitter of the second transistor is connected to a node between the first and second capacitors. The collector of the second transistor is grounded. The third capacitor is connected between the base and emitter of the second transistor.

Abstract: A temperature correcting apparatus divides an actually measured waveform of correcting voltages, which are required at each of different temperatures, by a minimum resolution of D/A conversion; obtains voltage digital values representing voltage values at individual dividing points of the actually measured waveform, and obtains times corresponding to the voltage digital values; prestores pairs of the voltage digital values and times together with addresses as correcting data; reads out the correcting data in response to the detection address representing the temperature; extracts or calculates from the correcting data the voltage digital values and times about the correcting voltages required by the detection address; and sequentially supplying a D/A converter (36) with the resultant voltage digital values in synchronization with the corresponding times.

Abstract: Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.

Abstract: A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals.

Abstract: Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed.

Abstract: A frequency-locking device including a digitally-controlled oscillator (DCO) and a comparing unit is disclosed. The DCO is used for generating an output frequency signal. The comparing unit receives a Keep Alive signal from a universal serial bus (USB) and the output frequency signal, and compares the Keep Alive signal with the output frequency signal to generate a calibration signal. Then, the DCO adjusts the frequency of the output frequency signal according to the calibration signal to meet the USB specification for data communication.

Abstract: A second harmonic oscillator has a series positive feedback configuration, suppresses output of a fundamental signal, and outputs a second harmonic signal having a frequency in a range from 1 GHz to 200 GHz generated inside of a circuit. The second harmonic oscillator includes: a transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal; a resonator circuit connected to the base terminal; a first transmission line shod-circuiting stub connected to one of the two emitter terminals; and a second transmission line short-circuiting stub connected to the other of the two emitter terminals and having a line length obtained by adding one-fourth of one wavelength of the fundamental signal to an integer multiple of one-half wavelength of the fundamental signal.

Abstract: A self-calibrating modulator apparatus includes a modulator having a controlled oscillator and an oscillator gain calibration circuit. The oscillator gain calibration circuit includes an oscillator gain coefficient calculator configured to calculate a plurality of frequency dependent oscillator gain coefficients from results of measurements taken at the output of the controlled oscillator in response to a test pattern signal representing a plurality of different reference frequencies. The plurality of frequency dependent gain coefficients determined from the calibration process are stored in a look up table (LUT), where they are made available after the calibration process ends to scale a modulation signal applied to the modulator. By scaling the modulation signal prior to it being applied to the control input of the controlled oscillator, the nonlinear response of the controlled oscillator is countered and the modulation accuracy of the modulator is thereby improved.

Abstract: A method and apparatus for correcting oscillator frequency drift due to crystal aging. Correction signals that reflect a difference between an oscillator timing signal and a reference timing signal over a reference timing signal interval are modeled so that auxiliary correction signals can be generated in the event of loss of the reference timing signal. A temperature curve is generated to model how temperature variation impacts oscillator frequency drift. A rate of frequency drift due to crystal aging is also determined. During loss of a reference timing signal, auxiliary correction signals can be generated to maintain the oscillator at a desired frequency until the reference timing signal becomes available again.

Abstract: This invention discloses a crystal-less communication device and self-calibrated embedded virtual crystal clock generation method. In communication systems, the invention proposes a crystal-less scheme in the device for wireless or wired-line communications. The operation concepts are that the transmitter Device-1 provides Device-2 a reference signal, and Device-2 takes this signal to generate a local signal with the similar frequency that has limited frequency error compared with the one from Device-1. This invention is done via the circuit-design methodology, so it can be implemented from any kinds of circuit implementation processes, especially the CMOS process. As a result, the hardware can be designed in the way of highly integration and extremely low cost. Also, this can largely change and improve existing communications design architecture, hardware cost, and hardware area.

Abstract: Embodiments of present invention provide a circuit including a voltage regulator, a phase frequency detector, a charge pump, a low pass filter a control-voltage generating circuit and a voltage controlled oscillator. In a first mode of operation the voltage controlled oscillator produces an output clock in accordance with a control voltage produced from the control-voltage generating circuit and the output voltage of the voltage regulator. In a second mode of operation, the voltage controlled oscillator produces an output clock in accordance with a control voltage from the low pass filter and the output voltage of the voltage regulator.

Abstract: A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.

Abstract: A reference voltage generator and a method for generating a reference voltage for a logic device using the reference voltage generator is provided. The voltage reference generator includes a ring oscillator having a plurality of logic gates and a phase/frequency detector. A first reference voltage is generated on the basis of a phase/frequency difference between the phase/frequency of a reference clock and the phase/frequency of the ring oscillator. A second reference voltage is generated on the basis of a voltage swing of the oscillator circuit. Both reference voltages can be applied to the plurality of logic gates of the ring oscillator such that a constant delay is created through each logic gate of the logic device.

Abstract: A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.

Abstract: Systems, circuits, and techniques for the calibration and fast tuning of VCOs in PLLs are provided. Information for coarse tuning before normal operation are calculated and stored. These systems and techniques decrease significantly the time needed for a PLL to transition from one frequency to another. These techniques involve: determining a digital code Dc, to coarse tune to a calibration frequency, Fc; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, these systems and techniques involve: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency.

Abstract: A method, system and computer program product for characterizing FET transistors in an electronic circuit (IC) device using Performance Screen Ring Oscillator (PSRO) techniques. During PSRO testing, logic and non-logic bias voltages are applied to gate terminals of the being tested FETs to determine process-related variations and the relative strength of N-type and P-type transistors.

Abstract: A high frequency signal detection circuit includes an input terminal for a high frequency signal to be detected, a switch transferring the high frequency signal as intermittent ringing signal to a first node in response to a pulse signal whose frequency is lower than that of the high frequency signal, a transistor amplifying the signal at the first node, and outputting to a second node, a bias generator generating a bias voltage by which the transistor is operated in its weak inversion region, a resonant circuit outputting the bias voltage to the first node, and resonating the high frequency signal, a capacitor removing a high frequency component of the signal at the second node; and a judgment circuit judging whether or not the high frequency signal is inputted by detecting the signal at the second node, which has the same frequency as the pulse signal.

Abstract: A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.

Abstract: A voltage-controlled oscillator is provided that avoids use of any crystal resonator, or any resonator that is external to and not integrated upon the voltage-controlled oscillator monolithic substrate. The present oscillator can receive two or more parameters that would likely have an affect on the oscillator frequency, yet the oscillator includes compensating transfer functions that will remove, or correct for, that effect. Transfer functions involve electronic subsystems implemented in hardware or software that receive the input parameter that has changed from a nominal value, and will note the drift in output frequency, yet will compensate for that drift so that the output frequency remains near the nominal value. The voltage-controlled oscillator preferably is an LCVCO, and the transfer function outputs can be summed to take into account multiple parameter changes.

Abstract: A method of manufacturing a temperature compensated oscillator including the steps of assembling an oscillator in which an IC chip constituting a temperature compensation circuit with an oscillation circuit and a compensation data storage circuit, and a resonator for the oscillation circuit are mounted in a package; adjusting the resonator with an oscillation frequency of the oscillation circuit to a desired oscillation frequency in condition that the oscillator is kept at a reference temperature, in condition that a temperature compensation function of the temperature compensation circuit is disabled; sealing the resonator hermetically; creating temperature compensation data and storing it into the compensation data storage circuit; and enabling the temperature compensation function of the temperature compensation circuit.

Abstract: A frequency synthesizer with automatic calibration includes a voltage-controlled oscillator, which has several working bands for receiving a coarse-tuned signal and a fine-tuned signal and generating an output signal in the working band of the coarse-tuned signals; preliminary frequency divider unit, which receives the output signal and generates an intermediate signal by frequency dividing; a feedback frequency divider unit, which receives the intermediate signal and generates a feedback signal by frequency dividing; an automatic calibration unit, which receives the input signal and the intermediate signal to generate a coarse-tuned signal; a phase-frequency comparator, which compares the input signal with the feedback signal and generates an error signal according to the frequency and phase differences between the input signal and the feedback signal; and a low-pass filter, which filters the error signal and generates a fine-tuned signal.

Abstract: Techniques are disclosed for estimating a frequency of a crystal oscillator based on temperature. In an embodiment, the oscillator frequency is computed using a polynomial approximation. Techniques are disclosed for deriving and periodically updating the coefficients used in the polynomial approximation.

Abstract: An aging compensation method for an oscillator circuit device, in which the oscillator circuit device receives a control voltage from an application end, and outputs a clock signal with a predetermined frequency in response to the control voltage, includes the steps of: a) inspecting the control voltage from the application end to obtain a first value thereof; b) after a predetermined time period has elapsed, inspecting the control voltage from the application end to obtain a second value thereof; c) determining whether there is a difference between the first and second values of the control voltage; d) if it is determined that there is a difference, performing compensation on the value of the control voltage based on the difference; and e) repeating steps b) through d).

Abstract: During testing frequency divider PS, test control voltage signal TC and RF test signal TS are supplied via balun Ti to input terminals IN1 and IN2. Test control voltage signal TC flows through resistors R1, R2 to turn on NPN transistor Q0. A current from current source I1 then ceases to be supplied through voltage-controlled oscillator V1 and buffer B10 to voltage-controlled oscillator V1 and buffer B10 to halt their operation. Output impedance of buffer B10 is increased. Since potential of input terminals is that of test control voltage signal TC, varactor diodes VD1, VD2 are forward-biased, increasing capacitance values of the varactor diodes further. RF test signal TS may be supplied to frequency divider PS, through varactor diodes VD1, VD2, without being affected by buffer B10 exhibiting high output impedance. Chip area of test circuit for PLL circuit is reduced.

Abstract: A method of determining a gain nonlinearity receives a phase difference and generates an output frequency based on the received phase difference. The method reconstructs a waveform by using the output frequency. The method preprocesses the phase difference to generate a comparison waveform. The method compares the reconstructed waveform to the comparison waveform and determines a gain nonlinearity based on the comparison between the reconstructed and comparison waveforms. A modulation system includes a voltage controlled oscillator for receiving an input signal based on a phase difference and generating an output frequency. The system further includes a waveform reconstructor and a comparator. The waveform reconstructor is coupled to the voltage controlled oscillator, and is for reconstructing a waveform based on the output frequency. The comparator is coupled to the waveform reconstructor, and is for comparing the output of the waveform reconstructor with the input signal.

Abstract: The surface-mount type crystal oscillator includes a container body made of laminated ceramics, having a flat bottom wall layer, a frame wall defining a recess and a step portion formed at an inner wall of the recess, a crystal blank fixed to the step portion, an IC chip fixed to an inner bottom surface of the recess and a pair of inspection terminals provided on outer side surfaces of the container body and used to measure a vibration characteristic of the crystal blank. The bottom wall layer is made up of a first layer making up an outer bottom surface of the container body and a second layer between the first layer and the frame wall, and the inspection terminals are formed so as to extend across an end face of the second layer and the outer side surface of the frame wall.

Abstract: A basestation for a cellular communication system has an interface, for connection to a computer network, and also includes an oscillator, for generating wireless transmit and receive frequencies. A controller receives timestamped response messages from a time server over the computer network, each response message being subject to a network propagation delay, which is a sum of a minimum network propagation delay and a jitter component. For each received response message an apparent network propagation delay is determined as a function of a difference between a first timestamp applied by the time server and a second timestamp based on a clock derived from said oscillator. A subset of the received response messages are selected, whose network propagation delays include minimal jitter components. The frequency accuracy of the oscillator is then determined based on changes over time in the apparent network propagation delays of the selected received response messages.

Abstract: Exemplary embodiments of the invention provide a system, method and apparatus for frequency calibration of a free-running, reference harmonic oscillator. An exemplary system comprises the harmonic oscillator, a frequency divider, a comparator, and a reactance modulator. The reference harmonic oscillator includes a plurality of switchable reactance modules controlled by corresponding coefficients, and provides an oscillation signal having an oscillation frequency, which is divided or multiplied by the frequency divider to provide an output signal having an output frequency. The comparator compares the output frequency to an externally supplied reference frequency using first and second predetermined levels of discrimination, and provides first or second comparison signals when the output frequency is higher or lower than the reference frequency.

Abstract: A system and a method for self calibrating a voltage-controlled oscillator (VCO). In the system, a mode controller generates a control signal for each of an automatic band selection mode, an automatic gain tuning mode, and a phase-locking mode, from a frequency comparison result between a reference clock signal and a divided clock signal which is generated by dividing a frequency of an oscillation signal, and thereby controls the VCO, so that the VCO may generate the oscillation signal which is automatically phase-locked in a target frequency with an optimal state.

Abstract: An integrated tuner includes circuitry to receive a television signal, a quadrature mixer coupled to the output of the circuitry, a polyphase filter coupled to the output of the quadrature mixer, a relaxation oscillator, and a digital calibration module. The relaxation oscillator generates a clock having a period that is directly proportional to the on-chip RC time constant. The clock is fed into a counter of the digital calibration module. The counter is started and stopped at predefined time intervals by a finite state machine. The finite state machine updates the calibration code based on a successive approximation algorithm according to the end count results received from the counter. The digital calibration module outputs the updated calibration code to the polyphase filter and to the relaxation oscillator.

Abstract: A system for real time clock (RTC) calibration includes: a timer counter; a clock generator; and a clock calibration unit coupled between the clock generator and the timer counter. The clock calibration unit receives calibration parameters comprising an average calibration value, a remainder calibration value and a calibration period, counts a plurality of clock cycles generated by the clock generator, calibrates a number of the counted clock cycles according to the average calibration value and remainder calibration value in the calibration period, and increments the timer counter by one second when a predetermined number of clock cycles have been reached.