Abstract: A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.

Abstract: A minimum frequency synchronization discriminator for use in providing a clock signal for a switch mode power supply automatically detects when the frequency of a sync signal is above a minimum frequency and causes the sync signal to serve as the clock signal for the controller. If the frequency of the sync signal is below the minimum frequency, the minimum synchronization frequency discriminator causes the output signal of the internal oscillator to serve as the clock signal.

Abstract: A ring oscillator setting apparatus and method depending on an environmental change of an image formation apparatus is provided. The apparatus includes a plurality of ring oscillators for generating different oscillation frequencies. The apparatus further includes a loopspeed detection unit to detect a loopspeed representing the number of pulses generated at the oscillation frequency by one of the ring oscillators selected from the plurality of ring oscillators for a predetermined unit time. Moreover, a state sensing unit is provided to detect a state of system environment of the image formation apparatus. A setting control unit is also provided to select and set one of the ring oscillators selected corresponding to change of the loopspeed detected from the loopspeed detection unit among the plurality of ring oscillators in response to the detected state of the state sensing unit.

Abstract: An integrated circuit device is provided having a reference ring oscillator circuit having a plurality of stages. Each stage has a logic gate and electrically connecting to a first independent voltage source. The integrated circuit device also has at least one additional ring oscillator circuit having a plurality of stages. Each stage has a logic gate substantially identical to the logic gates of the reference ring oscillator circuit and electrically connecting to a respective at least one second independent voltage source. Each stage also has a FET load driven by the logic gate and electrically connecting to a third independent voltage source. A measured difference in capacitance between the reference ring oscillator circuit per stage and the at least one additional ring oscillator circuit per stage comprises a gate capacitance of a FET load.

Abstract: Method for stabilizing the frequency of a MEMS (Micro Electro Mechanical Systems) reference oscillator, and a MEMS reference oscillator, wherein the method comprises following steps: using two or more MEMS components, wherein each MEMS component is characterized by a set of properties, and selectively combining the desired properties from the MEMS components.

Abstract: A clock signal outputting method in which either a clock signal based on a signal from the outside or an alternative clock signal from a fixed oscillator is selected and outputted, wherein, when the clock signal is selected to be outputted, the fixed oscillator is put into non-operating state, and when any error occurs in the clock signal, the fixed oscillator is operated to output the alternative clock signal.

Abstract: An oscillator circuit includes a current source for generating a current depending on the ambient temperature, a plurality of oscillators for oscillating at respective periods depending on the current from the current source and based on different relations between the ambient temperature and the periods, and a frequency demultiplication unit for receiving an output signal from one of the oscillators selected by a period selecting circuit 103. The frequency dividing ratio of the frequency demultiplication circuit is set so that a higher ambient temperature provides a smaller frequency dividing ratio.

Abstract: An integrated circuit includes an oscillator circuit, where a frequency of an oscillator output signal provided by the oscillator circuit is adjustable by either coupling a resistor to an input pin, or by applying an external clock signal to the input pin. The oscillator circuit includes a comparator, a follower, a current-controlled oscillator, and a switch circuit. The switch circuit is coupled between the input pin and a node that is coupled to the current-controlled oscillator. Also, the follower is arranged to cause the voltage at the node to be at a pre-defined voltage unless the voltage at the node is overdriven by an external clock signal. The comparator circuit is arranged to determine whether the signal at the input pin is a clock signal. If it is determined that the signal at the input pin is a clock signal, the switch circuit is opened.

Abstract: A redundant-source clock generator has only two oscillators, rather than three oscillators. A secondary oscillator is phase-locked to a primary clock from a primary oscillator using a phase detector, charge pump, and filter that generate a control voltage to the secondary oscillator that determine the frequency of a secondary clock. The primary clock is compared to the secondary clock to detect primary clock failure. When clock failure is detected, a mux is switched to select a delayed secondary clock rather than a delayed primary clock to output as a system clock. Since the mux receives delayed clock signals, clock-failure detection has additional time to detect the clock failure before the clock failure is propagated through the mux. When the primary oscillator fails and the clock failure is detected, the phase detector stops comparing a feedback secondary clock to the primary clock and instead holds the control voltage steady.

Abstract: A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.

Abstract: A first phase-locked loop circuit that includes a crystal oscillator, receives a reference clock signal and supplies a first phase-locked loop output signal based on the reference clock during normal operational mode and a stored value in holdover mode. A second phase-locked loop circuit receives the first phase-locked loop output signal and utilizes the first phase-locked loop output signal when generating an output clock in holdover mode. The second phase-locked loop utilizes the first phase-locked loop output signal during operation in the holdover mode to generate the output clock and utilizes the reference clock during normal operational mode to generate the output clock. Alternatively, the second phase-locked loop utilizes the first phase-locked loop output signal both during operation in the holdover mode and during normal operational mode to generate the output clock.

Abstract: In one embodiment, a clock generation system comprises a redundant clock source (RCS) device for receiving multiple timing signals and for generating at least one clock from the timing signals for distribution to other circuits, and first and second oscillator devices, wherein the RCS device switches between timing signals from the first and second oscillator devices in response to timing signal failure, wherein the RCS device filters timing signals from the first and second oscillator devices using respective bandpass filters to detect an incorrect oscillator frequency.

Abstract: A voltage-controlled oscillator has a voltage-controlled oscillation circuit that oscillates at a frequency according to a control voltage and a limiter circuit that limits the output of the voltage-controlled oscillator to a predetermined level. This configuration makes it possible to maintain a constant output level irrespective of the oscillation frequency.

Abstract: A pulse width of a pulse having a nominal pulse width is modulated in accordance with a digital value to be communicated. The number of clock cycles that the modulated pulse width exceeds the nominal pulse width is counted. Various embodiments use a counter to determine the extent that the modulated pulse exceeds the nominal pulse width. The counter is initialized to a value (P) upon detection of a first edge of the extended pulse. The counter is configured to rollover or is reset when the counter reaches a count of P+M, where M represents the nominal pulse width count. In various embodiments, P is zero. The counter is halted upon detection of a second edge of the extended pulse. The resulting count represents the digital data value.

Abstract: A polyphase numerically controlled oscillator (PNCO) is defined to include a plurality of sub-numerically controller oscillators (SNCO's). Each SNCO is capable of receiving a clock signal at a first clock rate and an assigned phase offset signal. Each SNCO is configured to generate a digital waveform for the assigned phase offset signal. The PNCO also includes a plurality of frequency multipliers for generating a frequency multiplied representation of the digital waveform generated by each SNCO. The PNCO further includes a multiplexer configured to receive output from each of the frequency multipliers according to the first clock rate. The multiplexer is further configured to receive a select signal, wherein the select signal triggers the multiplexer at a second clock rate.

Abstract: A direct calibration technique significantly tightens a tolerance band between multiple voltage controlled oscillators (VCOs), to correct for slight frequency mismatch between the multiple VCOs. The tightened tolerance band enhances the bit error rate (BER) and/or lengthens the possible consecutive identical digits (CIDs) length, and is particularly useful in integrated circuit applications. A Frequency Locked Loop (FLL), an accumulator, and a DAC are implemented to form a calibration loop that becomes far more digital in nature than a PLL, permitting greater embedded circuit test coverage and ease of integration in VLSI digital technologies. A frequency calibrated loop with digital accumulator and DAC in lieu of a PLL with associated charge pump integrator eliminates the need for large integrated capacitors, sensitivity to drift due to the leakage currents associated with deep sub-micron technologies, and embedded analog voltages which generally cannot be tested.

Abstract: A frequency-selective high-frequency oscillator includes a first switching circuit that controls the operation of a first amplifying circuit, and a second switching circuit that controls the operation of the first switching circuit and a second amplifying circuit. Switching control signals are input to the second switching circuit. When the switching control signal is “Low”, the second switching circuit turns ON and the second amplifying circuit only operates, thereby outputting a high frequency signal with a resonant frequency according to a second resonant circuit. On the other hand, when the switching control signal is “High”, the second switching circuit turns OFF and the first switching circuit turns ON, which causes the first amplifying circuit only to operate. Thus, a high frequency signal with a resonant frequency acceding to a first resonant circuit is output.

Abstract: A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master, generating a system clock signal, while the second clock board acts as a slave. The first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal. If the phase difference exceeds a limit, the first crystal clock signal may be inhibited, preventing the first clock board from generating the system clock signal. The second clock board may monitor the system clock board in reference to a feedback clock signal. If the second clock board detects a predetermined number of consecutive missing clock edges, it may enable a second crystal clock signal, which may be used to generate a system clock signal.

Abstract: A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated within a video-processing portion of a personal digital assistant is analyzed. As reduced activity is identified, power conservation modes are implemented. In a normal mode of operation, a clock signal generated through an external oscillator is provided to a phase locked loop (PLL). An output clock signal from the PLL is then provided to several dividers to generate system clock signals. In a reduced mode of operation, the output clock from the external oscillator is provided to a divider, bypassing the PLL. Video processing components then use clock signals based on the external oscillator. In a suspend mode, both the PLL and the external oscillator are disabled.

Abstract: A voltage-controlled oscillator has a voltage-controlled oscillation circuit that oscillates at a frequency according to a control voltage and a limiter circuit that limits the output of the voltage-controlled oscillator to a predetermined level. This configuration makes it possible to maintain a constant output level irrespective of the oscillation frequency.

Abstract: A redundant clock module provides a highly reliable fixed clock reference output. This clock reference output is based on at least two internal reference oscillators that are monitored and eliminated from use if they are not operating or within tolerance requirements. The redundant clock module comprises at least two oscillators, detection circuitry, switching circuitry and control circuitry. If a primary oscillator fails or is out of tolerance, the redundant clock module will detect the failure or out of tolerance condition and switch to a secondary working and in tolerance oscillator to take over primary timing functions of an end user application. The redundant clock module provides a slow and seamless transition between oscillator switching to assure no significant phase shift or runt pulses will affect the end user application.

Abstract: The invention relates to a phase-locked loop structure providing local oscillator signals. In order to enable an improved supply of local oscillator signals, the phase-locked loop structure comprises a first phase-locked loop including a first voltage controlled oscillator and a second phase-locked loop including a second voltage controlled oscillator. A first local oscillator output provides a first local oscillator signal, wherein a signal output by the first voltage controlled oscillator is forwarded to the first local oscillator output. A second local oscillator output provides a second local oscillator signal. A selection component forwards a signal output by the first voltage controlled oscillator or a signal output by the second voltage controlled oscillator to the second local oscillator output. The invention relates equally to a corresponding communication unit and to a corresponding method.

Abstract: Embodiments of the invention provide techniques for calibrating voltage-controlled oscillators (VCOs). Multiple VCOs may be disposed on a chip with the VCOs having different frequency ranges. The VCOs may be selected and tested to determine a desired VCO to use to tune to a selected channel frequency. Each of the VCOs has multiple possible varactor configurations. The varactor configurations of the desired VCO determined to be used to tune to the selected channel frequency can be selected and tested to determine a desired varactor configuration for the desired VCO. The desired VCO with the desired varactor configuration will preferably be able to produce a full range of desired frequencies corresponding to all channel frequencies desired.

Abstract: A single integrated chip has first and second voltage controlled oscillators and first and second buffers. The first voltage controlled oscillator has a first output defined by a first frequency band, and the second voltage controlled oscillator has a second output defined by a second frequency band. The first and second buffers selectively couple the first and second outputs to a common output. The first buffer is coupled between the first frequency controlled oscillator and the common output, and the second buffer is coupled between the second frequency controlled oscillator and the common output. The first buffer has a high output impedance when the second buffer couples the second output to the common output, and the second buffer has a high output impedance when the first buffer couples the first output to the common output.

Abstract: Oscillator circuitry on an integrated circuit automatically detects the presence or absence of an external resistor which is used to bias and set the frequency of an internal resistor-capacitor (RC) oscillator. If the resistor is present, the RC oscillator begins to oscillate to generate an oscillator clock. The presence of the oscillator clock is detected, and the RC oscillator continues to generate the oscillator clock. If the resistor is not present, the RC oscillator does not begin to oscillate. The absence of the oscillator clock is detected, and the oscillator circuitry automatically re-configures itself to generate the oscillator clock from an internal crystal oscillator circuit employing an external crystal.

Abstract: An analysis operation section uses a digital signal converted by an A/D converter, and performs frequency analysis for a modulation signal and modulation analysis for the modulation signal selected by a signal selection circuit in order to modulate/analyze a digital signal level of the modulation signal as an analysis object outputted from a level converter. A controller instructs the analysis operation section to execute an analysis instruction inputted via an operation input section, sends a selection instruction to the signal selection circuit in accordance with a modulation type of the inputted modulation signal, and sets a bandwidth of an RBW filter in accordance with the modulation type when the modulation signal having a band limited by the RBW filter is selected as the modulation signal inputted to the A/D converter, and the modulation analysis instruction is inputted.

Abstract: A voltage-controlled oscillator (“VCO”) structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.

Abstract: A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling both the oscillator and the low power oscillator. The oscillator control circuit including at least one real time counter. The oscillator control circuit being so configured that the oscillator is energized when said oscillator control circuit is in a normal mode and that, when a power down signal is received: a) the oscillator control circuit measures an oscillation frequency of the low power oscillator, b) the oscillator control circuit uses the measured oscillation frequency of the low power oscillator to set the real time counter so as to maintain the power down mode for the predetermined time, c) the oscillator control circuit turns off the oscillator and uses the low power oscillator for the duration of the power down.

Abstract: A voltage controlled oscillation device includes a voltage controlled oscillator, fixed-frequency oscillator, frequency mixer, and frequency selector. The voltage controlled oscillator changes the output signal frequency in the microwave band in accordance with the input voltage of a frequency control signal. The fixed-frequency oscillator has a fixed oscillation frequency higher than that of the voltage controlled oscillator. The frequency mixer mixes the output signal from the fixed-frequency oscillator and the output signal from the voltage controlled oscillator and outputs the sum frequency and difference frequency between the two signals. The frequency selector selects and outputs one of the sum frequency and difference frequency contained in the output signal from the frequency mixer.

Abstract: A method for switching between multiple clock signals in a digital circuit is provided that includes providing to a clock selector at least three distinct clock signals for the circuit. A master clock signal for the circuit is generated with the clock selector based on a first one of the distinct clock signals. The master clock signal is asynchronously blocked. The master clock signal for the circuit is generated with the clock selector based on a second one of the distinct clock signals. The master clock signal is synchronously unblocked.

Abstract: An oscillator transmission switching circuit switches between asynchronous oscillator signals with low latency. Preferably, a fast switching circuit triggers a transition from a first oscillator to a second oscillator by entering a bridge input immediately following an edge of the first oscillator, holding in the bridge input until the same edge of the second oscillator is detected, and switching to the second oscillator. Preferably, the bridge input is selectable to accommodate conditions in which the first oscillator signal is stuck at either a logic 0 or a logic 1. A change of oscillators may be triggered by a fault detection circuit or by an external signal.

Abstract: A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

Abstract: A microcomputer is provided, which eliminates the need of input of a selection signal to select whether an external oscillator element is connected to generate an internal clock signal or an external clock signal is inputted to generate an internal clock signal. In this microcomputer, a delay circuit generates a delayed reset signal from an external reset signal to have a specific delay period. An external clock signal detection circuit detects an external clock signal at a second terminal, outputting a detection signal. An oscillation control signal generation circuit generates an oscillation control signal for an amplifier circuit, where the oscillation control signal is generated corresponding to a detection signal outputted from an external clock signal detection circuit. The oscillation control signal is used to activate the amplifier when the external clock signal does not exist at the second terminal and to inactivate the amplifier when the external clock signal exists at the second terminal.

Abstract: A phase-locked loop (PLL) keeps tracking a reference clock when a frequency offset is introduced. The PLL has primary and secondary PLL loops. A digital-to-analog converter (DAC) generates a current that is passed through an offset resistor to generate an offset voltage. An op amp is inserted in the primary loop between a filter capacitor and a voltage-controlled oscillator (VCO). The offset resistor is coupled between the inverting input of the op amp and the op amp's output. When the DAC offset occurs, the voltage to the VCO and the frequency of the primary loop change and the primary loop loses tracking of the reference clock. The secondary loop keeps tracking the reference clock during the DAC offset while the primary loop is open. Then the output clock of the secondary loop is applied as the feedback clock to the phase comparator of the primary loop.

Abstract: A frequency variation apparatus is provided for use in a hardware-based random number generator. The frequency variation apparatus includes sampling frequency variation logic and a sampling frequency oscillator. The sampling frequency variation logic produces a noise signal that corresponds to parity of two independent and asynchronous oscillatory signals. The sampling frequency oscillator is coupled to the sampling frequency variation logic. The sampling frequency oscillator receives the noise signal, and varies a sampling frequency within the random number generator in accordance with the noise signal.

Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Abstract: A multi-octave, wideband voltage controlled oscillator has a plurality of high impedance current output individual voltage controlled oscillators coupled in parallel to form a bank of voltage controlled oscillators covering at least one high frequency octave. The outputs of the VCOs are wire-OR'd together and the VCOs are selected by a select signal that turns on the desired oscillator(s). A main limiter/divider selects a frequency octave at either the fundamental frequency of the selected VCO or a sub-harmonic thereof as the multi-octave, wideband voltage controlled oscillator output. A reference limiter/divider selects a reference frequency from the selected VCO for use in a phase locked loop. Each VCO has a tank circuit coupled across the bases of a pair of transistors, the emitters of which are coupled through respective current sources to ground. The collectors of the transistors are coupled to the wire-OR'd network.

Abstract: An apparatus comprising a first oscillator, a second oscillator and a logic circuit. The first oscillator circuit may be configured to generate a first clock signal. The second oscillator circuit may be configured to generate a second clock signal. The logic circuit may be configured to generate an output clock signal by selecting either the first clock signal or the second clock signal.

Abstract: An RC type oscillator (10) is integrated into a processor circuit (2) of a mobile device (1). This oscillator is used to set the pace of the activity of the processor circuit during periods when the mobile device is on standby. The frequency drift due to the temperature variations of the oscillator is concerted by a regular calibration of the oscillator by a faster oscillator recognized to be stable. This embodiment gives gain in space and a reduction in cost.

Abstract: A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

Abstract: A dual band voltage controlled oscillator that has low phase noise. The oscillator includes two voltage controlled oscillators that are each coupled to a tank circuit for adjusting the output frequency. One voltage controlled oscillator operates at a low frequency and one operates at a high frequency. Both voltage controlled oscillators are coupled to a combiner circuit that provides the oscillator output signal. A low frequency bandstop filter is coupled to the output of the second voltage controlled oscillator. The low frequency bandstop filter operates so as to reject the low frequency.

Abstract: A voltage control oscillator used in mobile communication systems such as cellular phones and video machines. An oscillation output of the first output oscillation circuits (1a) enters a broad band buffer amplifier circuit (4) through a stage-to-stage coupling capacitor (22) and an oscillation output of the second output oscillation circuit (1b) enters the broad band buffer amplifier circuit (4) through frequency selective filters (3a, 3b) and the stage-to-stage coupling capacitor (22). On/off operation of a control voltage of a switch terminal (2) installed on the first or second output oscillation circuit outputs selectively an oscillation signal from the first or second output oscillation circuit.

Abstract: A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slower clock signal and provided to an AND gate gating the slower clock signal based on the value of a select signal formed by the synchronized sleep signal. The slower clock signal is delayed by a number of faster clock cycles equal to the time taken by the select signal to be received at the AND gate after the sleep signal is synchronized to the slower clock signal. In an alternative embodiment, a signal control block ensures that the 0 to 1 transition on one of the select signals follows the 1 to 0 transition on another select signal when the value of the sleep signal changes. In addition, each select signal is synchronized with a negative edge of the corresponding clock signal selected.

Abstract: A radiation hardened timer that keeps accurate time before, during and after passage through a radiation-containing environment, the radiation hardened timer having a first oscillator that is stable in a radiation-free environment, a second oscillator that is stable in a radiation-containing environment, and digital circuitry that interfaces the two oscillators.

Abstract: An apparatus comprising a first circuit and a timing circuit. The first circuit may be configured to generate an output clock signal that may compensate for oscillation build-up and stabilization time after a power up. The timer circuit may be configured to provide timing in response to the output clock signal.

Abstract: In a clock control circuit, a multiplication factor setting unit outputs a multiplication factor. A buffer circuit holds a previous multiplication factor and the multiplication factor output by the multiplication factor setting unit and compares the two multiplication factors. When the multiplication factors are different from each other, a clock state control circuit provides a control to, stop the output of clock to the outside, switch the clock to a clock other than those output by the PLL oscillation circuit, change the multiplication factor in the PLL oscillation circuit, switch the clock to clock output by the PLL oscillation circuit after the PLL output clock is stabilized, and restart output of the clock to the outside.

Abstract: A variable frequency oscillator provides an output frequency that is adjustable by selectively combining different delay signals from separate signal paths. The present invention's oscillator includes first and second differential signal paths, each exhibiting a different time delay or “phase.” Each signal path includes a series coupling of multiple delay elements, where each delay element comprises a single differential amplifier transistor pair. Each signal path's delay is established by setting the biasing and geometry of the signal paths' differential amplifier transistor pairs. A combiner, separately coupled to each signal path, selectively combines signals from the paths to provide a representative output. This output is also fed back as input to both signal paths. As an example, the combiner may be provided by two non-nested differential amplifier transistor pairs.

Abstract: A sweep controller supplies a current to a YTO(YIG-Yttrium-Iron-Garnet Tuned Oscillator) from a current drive circuit in such a manner that frequencies corresponding to a first range in an oscillation frequency of the YTO designated as a desired frequency range for analysis with one sweep, and a second range designated as a frequency range higher than the first range for the analysis with the next one sweep are oscillated by the YTO. Moreover, the sweep controller outputs an instruction for increasing the current flowing through the YTO from the current drive circuit over a part of a period between an end of the first range and a start of the second range in order to shorten the period between the end of the first range and the start of the second range when it is detected that a difference between an end frequency of the first range and a start frequency of the second range is larger than a predetermined frequency difference.

Abstract: A dual band voltage controlled oscillator that has low phase noise. The oscillator includes two voltage controlled oscillators that are each coupled to a tank circuit for adjusting the output frequency. One voltage controlled oscillator operates at a low frequency and one operates at a high frequency. Both voltage controlled oscillators are coupled to a combiner circuit that provides the oscillator output signal. A low frequency bandstop filter is coupled to the output of the second voltage controlled oscillator. The low frequency bandstop filter operates so as to reject the low frequency.