Abstract: A loss-of-phase-lock indicator circuit is described which detects an out-limit voltage, whether steady or transitory. A pair of comparators, one for the high limit and the other for the low limit, are inserted in series between the tuning voltage and the sweep feedback amplifier, and are dc-coupled to the peak detector in the failure circuit. Additionally, a "dither" voltage is added in series with the phase detector, which ac voltage is large enough to swing the tuning voltage between limits at the loop amplifier output, but small enough to produce little effect on the output during phase lock.

Abstract: A first phase locked loop (PLL) having a second PLL with programmable divider therein supplying 50 kilohertz steps of coarse tuning to a mixer and a third PLL with programmable divider therein providing 50 Hertz fine tuning steps to a phase detector for providing any of a plurality of steps of frequency within a band of frequencies in response to control signals applied to the two programmable dividers.

Abstract: A partly analog partly digital bit synchronizer capable of acquisition and operation over an arbitrarily broad range of data rates is disclosed. A second order phase lock loop (PLL) is employed providing both phase and frequency correction to a voltage controlled oscillator (VCO). The phase detector consists of a binary counter whose most significant bit (MSB) is defined to be the recovered clock. The desired data transition points are defined as coinciding with the falling edge of the counter's MSB. At each data transition, the least significant bits within the counter are used to set the duration of phase and frequency correction pulses proportional to the phase error, which pulses are then fed to the VCO. An acquisition circuit diverts the frequency correction pulses in order to sweep the VCO within a selected half octave. Lock is recognized when a preselected number of data transitions with phase error below a preset maximum occur consecutively.

Abstract: The oscillation frequency of a variable frequency oscillator is swept by a sweep signal from a sweep signal generator and the oscillation frequency is compared with a preset sweep start frequency for detecting coincidence therebetween. Upon detecting the coincidence, the sweep operation of the sweep signal generator is stopped and, at the same time, the oscillation frequency of the variable frequency oscillator is made by phase lock loop means to be phase-synchronized with a reference frequency. When the phase synchronization is established, an error signal in the phase synchronization is held and the loop of the phase lock loop means is cut off and then the error signal is applied to the sweep signal generator to re-start the frequency sweep of the variable freqency oscillator. When coincidence is detected between the oscillation frequency of the variable frequency oscillator and a preset sweep stop frequency, the sweep operation is stopped.

Abstract: The sweep rate of a linearly swept frequency generator is increased while maintaining strict linearity by artificially increasing the number of zero axis crossings of the output signal from a linearly swept voltage controlled oscillator over those that would naturally occur during a linear sweep. This permits an increased sampling rate which, in turn, permits the oscillator sweep rate to be increased without loss of accuracy. Increasing the number of zero axis crossings is accomplished by introducing phase shifts in the output of the oscillator at calculated sampling times with phase shifting being accomplished indirectly by heterodyning the swept oscillator output with the output from a fixed oscillator whose output signal is phase shifted by discrete amounts during the frequency sweep. Only a small number of phase shifts need be introduced due to the discovery of certain symmetries of phase when sweeping through a frequency range.

Abstract: A sweep signal generation system for producing an output sweep signal of very high frequency includes a circuit for generating an input sweep signal, and a phase locked loop which includes a phase detector, a voltage controlled oscillator and a harmonic frequency mixer. The output sweep signal is applied to the harmonic mixer together with a local oscillator signal of fixed frequency, the output from the harmonic frequency mixer being applied to the phase detector together with the input sweep signal. The output from the phase detector is applied to the voltage controlled oscillator to cause the frequency of the output thereof to be swept in accordance with variation of the input sweep signal.

Abstract: The automatic sweep and acquisition circuit for a phase locked loop includes a first circuit to detect when the error signal into the voltage controlled oscillator of an unlocked phase locked loop drifts to a DC voltage of a predetermined magnitude which represents an out-of-lock condition for the loop and this detected predetermined value is used to start the sweep waveform so as to regain a locked condition. Simultaneously with the start of the sweep waveform a dither tone is introduced into the loop filter which will not be fed back into the loop filter until the loop is locked. This fed back tone is detected and used to turn off or disconnect the sweep voltage and the dither tone.

Abstract: A receiver for high frequency electromagnetic oscillations, having frequency readjustment with a voltage-control oscillator, includes a phase control loop for regaining the carrier in the signal path of the receiver. The phase control loop comprises a device for recovering the carrier, a phase-locked loop oscillator and phase detector which receives the output signal of the carrier recovery device and the oscillations of the phase-locked loop oscillator as a reference, and a demodulator which receives the modulated input signal and the output of the phase-locked loop oscillator.

Abstract: A method and a circuit for stably driving an ultrasonic transducer by sweeping, as a first step of starting the oscillation, the oscillating frequency over a range wider than a PLL followable range, finding a resonant point to lock the oscillating frequency thereto, and effecting, as a second step, the PLL following operation starting from the above resonant point.

Abstract: The automatic pretuning of a voltage controlled oscillator in a phase locked loop frequency synthesizer utilizes a successive approximation technique to rapidly bring the coarse tuning voltage of the oscillator to the desired pretuning value. A digital number stored in a digital register is converted to an analog voltage value and applied to the voltage controlled oscillator as the coarse tuning voltage. The frequency of the output signal from the oscillator is compared with a reference signal, and control logic responsive to the sense of the frequency difference between the reference signal and the oscillator output signal adjusts the value of the number stored in the digital register successively from the most significant bit to the least significant bit. A microprocessor can be used to adjust the value of the number stored in the register, as well as provide additional functions such as reverse successive approximation when the synthesizer is switched from one frequency to another frequency.

Abstract: A voltage controlled oscillator (VCO) and reference oscillator are connected in a phase locked loop with a first phase detector, loop switch, and acquisition sawtooth sweep circuit. A second phase detector and fast integrator circuit are connected to the VCO and reference oscillator in quadrature relation with respect to the first phase detector. As the acquisition sweep circuit sweeps the VCO, the fast integrator produces a signal whose magnitude increases as the swept VCO frequency approaches the frequency needed for the phase locked loop to achieve phase lock. When this signal magnitude exceeds a predetermined threshold, an output control signal is produced. This output control signal causes the loop switch to close and make the phase locked loop operational. A delay circuit is connected to the second phase detector and fast integrator. The delay circuit produces a delayed output at a predetermined time after the control signal is produced.

Abstract: The output of a VCO, a referenced frequency signal and an offset frequency signal are mixed to provide a control signal for the VCO and a double offset frequency signal which is mixed with an output of the offset frequency source to provide a DC component having a positive polarity if the signals are inphase and the VCO is locked on one sideband and a negative polarity if the signals are out of phase and the VCO is locked on the other sideband. A sweep signal is activated and applied to the VCO in response to the VCO being locked onto the wrong sideband.

Abstract: A method is presented for generating highly-linear periodic frequency sweeps by providing closed-loop linearity corrections for linear frequency sweeps that are error averaged over a number of sweeps. The technique can operate with a variable sweep period.

Abstract: An improved automatic frequency control arrangement for a missile-borne inverse receiver is shown to include a reference oscillator and a voltage-controlled oscillator with control means for the latter, such means including a frequency-to-voltage converter responsive to the difference frequency between the two oscillators so that the latter may produce a signal representative of the Doppler shift frequency of a target. A starting circuit is also shown to ensure that the frequency of the reference oscillator is always lower than the frequency of the voltage-controlled oscillator.

Abstract: A piezo-electric crystal vibrating in several modes controls several frequencies generated by voltage controlled oscillators simultaneously. The output of each voltage controlled oscillator is fed to a summing amplifier which drives the crystal. The output of the crystal is fed to individual phase detectors; each phase detector is also supplied with the output of a voltage controlled oscillator and generates a voltage proportional to the phase difference between the voltage controlled oscillator and the crystal output for correcting the output frequency of each oscillator.

Abstract: A phaselock loop in a phaselock receiver includes a voltage-controlled oscillator, and a main phase detector receptive to an output of the oscillator and a received signal. Means to detect when the oscillator is phase locked with the received signal includes a quadrature phase detector receptive to a quadrature-phase-shifted oscillation from the oscillator and the received signal. Means are provided to subtract the direct-current component of the output of the main phase detector from the direct-current component of the output of the quadrature phase detector to provide a phaselock-indicating signal which is substantially zero when the oscillator is out-of-lock with the received signal, and which is high when the oscillator is in-lock with the received signal.

Abstract: An improved phase-locked loop includes a phase detector, active loop filter and a VCO, in conventional phase-locked loop relationship. In addition, a positive feedback path couples active loop filter output to active loop filter input. In the absence of loop lock, the positive feedback provided by the positive feedback path satisfies the conditions necessary for the production of an oscillating output from the active loop filter circuit. The oscillating output generated by this "oscillator" drives the VCO in a sweeping action allowing the loop to acquire signals outside of its normal capture range. On capture, phase detector output provides an additional negative feedback path which overrides the effect of the positive feedback path and therefore, oscillations cease and the loop locks. The positive feedback path can comprise a relatively simple passive frequency selective circuit.

Abstract: A sampling linearizer including a phase shifter for use in improving the accuracy of an FM generated waveform with respect to a desired frequency rate of change is disclosed. The sampling linearizer comprises an oscillator for generating a reference frequency signal; a mixer governed by the generated FM waveform signal and the reference frequency signal to generate a first signal which is sampled at predetermined sampling times; and a linearizing servo controller which is governed by the sampled signal to reduce the inaccuracies in the genereated FM waveform with respect to the desired frequency rate of change. The sampling linearizer further includes a phase shifter disposed between the oscillator and mixer thereof and operative upon the reference frequency signal to generate another signal, the phase shifter being operative to shift the phase of the another signal with respect to the reference frequency signal as governed by a sequence of control signals representative of predetermined phase shift values.

Abstract: An incoming signal including the object signal and plurality of noise signals dispersed about the object signal is fully masked with white noise and applied to a phase synchronization loop wide in loop band width and including a local oscillator repeatedly swept by a sweep generator. During the repeated sweep a control signal generator successively decreases the level of the white noise until the oscillator is locked in the phase of the object signal. At that time the signal control generator is operated to suspend the sweeping operation and prevent the white noise from being added to the incoming signal.

Abstract: An RF-IF signal receiving circuit of a television receiver controls a tuner which receives an amplitude modulated RF signal and converts it to an IF signal and an IF signal carrier generator for demodulating the amplitude modulated signal from the IF signal by synchronous detection, using a phase synchronous loop. A sweep voltage generator of a voltage-controlled oscillator in the phase synchronous loop comprises an envelope detector which is DC-coupled to an output of an amplitude synchronous detector and a low pass filter in order to enhance the pull-in range of the phase synchronous loop.

Abstract: A comparator-discriminator is provided, suitable for use with a phaselock control system of a frequency synthesizer, to permit automatic tuning of a variable oscillator to a selected frequency lying within a frequency band for which a phaselock may occur. This system permits the frequency of the variable oscillator to lock-on to an arbitrary value in the range other than the preselected value, at which time the phaselock is broken by an injected signal, thereby permitting the shifting of the oscillator frequency to a value lying closer to the selected frequency value. Upon achievement of phaselock to the selected frequency, in a slightly more elaborate embodiment, the injected signal is inhibited and no further breaking of phaselock can occur.

Abstract: A phase lock loop operable with narrow band filtering characteristics in-lock and wideband acquisition characteristics when an out-of-lock condition is detected. The phase lock loop comprises a phase detector coupled to a differential amplifier to which a step ramp voltage is also coupled when an a.c. signal, which indicates an out-of-lock condition, is coupled from the phase detector to an out-of-lock detector. The a.c. signal from the phase detector also causes a switch means to short out a narrow band filter which is serially coupled with a wideband filter between the differential amplifier and a voltage controlled oscillator. The frequency of the voltage controlled oscillator is caused to vary by the a.c. signal until lock-in is achieved at which time, the out-of-lock detector stops and holds the step ramp voltage at the value required to achieve lock and the switch means reintroduces the narrow band filter to the loop.

Abstract: A variable frequency oscillator is disclosed which is electronically and periodically swept from one frequency to another. Prior to the beginning of each sweep, the variable frequency oscillator is phase locked to a reference signal source and the error voltage in the phase lock loop is stored. When the sweep begins the phase lock loop is opened and the error voltage is summed with a sweep voltage to provide for correction of oscillator drift on a sweep by sweep basis.

Abstract: A phase synchronizing circuit for the demodulation of multi-phase PSK signals has a broadened capture frequency range while avoiding false capture. The circuit includes a phase synchronizing loop having a voltage controlled oscillator for generating a variable frequency output in response to a control voltage and a phase comparator for providing a comparison output representative of the phase difference between the output of the voltage controlled oscillator and an input signal. The comparison output serves as the control voltage for the voltage controlled oscillator. A phase-lock detection circuit is connected to the phase synchronizing loop to detect the phase-synchronized or unsynchronized states of the loop. A low frequency sweep generator is responsive to the phase-lock detection circuit for generating a variable-amplitude voltage which is supplied as a frequency sweep voltage to the voltage controlled oscillator.

Abstract: A variable frequency oscillator including a nonlinear element for varying the frequency has alternately attached thereto a phase lock loop for maintaining the base or starting frequency of the oscillator substantially constant, and a sweep generator with a rate error loop for sensing the frequency linearity of the output sweep and altering the input signal to maintain the output linear.

Abstract: In a phase locked loop circuit which includes a variable frequency oscillator, a reference signal oscillator, a phase comparator for detecting the phase difference between the output signals of the reference signal oscillator and the variable frequency oscillator, respectively, and a low pass filter supplied with the output of the comparator so as to provide a corresponding DC voltage for controlling the variable frequency oscillator, and in which the variable frequency oscillator is manually changed, as by a variable capacitor, so that the frequency thereof is an integral multiple of the frequency of the reference signal oscillator; a control signal generating circuit is provided to detect the DC voltage from the low pass filter and to produce a control signal when the DC voltage is outside a predetermined voltage range, with the control signal being applied to the variable frequency oscillator so as to vary the frequency thereof outside of the lock range of the phase locked loop toward the capture range the

Abstract: A received, suppressed carrier, quadraphase shift key modulated (QPSK) signal is demodulated with a phase locked loop including a variable frequency, coherent reference that drives first and second channels also responsive to the QPSK signal. The channels respectively derive first and second replicas of binary signals that modulated the suppressed carrier. The replicas are combined to derive a variable amplitude error signal for controlling the coherent reference frequency. The frequency of the coherent reference is dithered at a low rate so that there is derived a relatively low level tracking error phase from the locked loop. The frequency of the coherent reference is swept when the phase of the error signal differs from the dithering phase by a predetermined value that is appreciably less than 90.degree..

Abstract: A phase lock loop system that includes a voltage controlled oscillator. The output of an integrator provides the voltage to a tuning port for determining the precise frequency and phase of the oscillator. In response to a change in frequency, the input to the integrator is switched off at the precise time that its output voltage reaches the value for the proper phase relationship at the new frequency. The output of a low pass filter fed by the loop's phase detector determines such precise time. At said precise time, the stabilized condition of the loop is sensed and corrected for minor deviations.

Abstract: A dual bandwidth loop filter includes a filter loop, resistive means, switching means for coupling and decoupling the resistive means for changing the bandwidth of the loop from a wider acquisition bandwidth to a narrower tracking bandwidth and a sweep generator for enabling the filter to provide sweep acquisition of an incoming signal.

Abstract: Apparatus and method are provided to discriminate between true locking of a phase-locked loop on the main lobe of an information signal, and false locking on a side lobe thereof. The energy in the locked signal is sensed and compared with the signal energy at fixed frequency increments, preferably twice the bit clock rate frequency, above and below the lock frequency. A greater energy content at the increment frequencies than at the locked frequency indicates a false lock condition and is used to inhibit the loop from entering a locked mode.

Abstract: A frequency scanning automatic phase control includes a phase detector, a local oscillator and an APC filter. A coincidence detector includes an AND gate responsive to the horizontal retrace and reference synchronizing pulses. A lock detector also responsive to the retrace and reference sync pulses produces an output signal when a predetermined interval of non-coincidence has existed. An AND gate responsive to both the lock detector and coincidence detector gates a current sink which unbalances the phase detector producing a ramp-like error voltage across the APC filter. A threshold detector coupled to the APC filter activates a discharge circuit also coupled to the filter when the filter voltage exceeds the threshold. The oscillator responds to the variations of error voltage and changes frequency accordingly. Once coincidence occurs frequency variation ceases and is resumed only if non-coincidence returns.

Abstract: A conventional phase-lock loop circuit is modified for use at microwave frequencies. The modification includes a low-frequency oscillator connected in the phase-lock loop to sweep the voltage-controlled oscillator through the frequency of the incoming signal thereby ensuring that lock-in is achieved. The oscillator is automatically turned off when "lock-in" is achieved, thereby reducing residual phase error.

Abstract: A device for generating a repetitive, highly-linear, frequency ramp. A voltage controlled oscillator responds to a ramp generator to produce the desired frequency modulation, and means are included for modifying the ramp amplitude vs. time shape as a function of the variation of instantaneous values of the frequency ramp from the linearized ideal.

Abstract: A phase lock loop configuration having a voltage controlled oscillator utilized, for example, in radar systems wherein false locking is prevented and loop bandwidth is maintained substantially constant. The voltage controlled oscillator includes a cavity resonator within which is located two tuning varactor diodes, one of which is heavily coupled to the resonator and comprises a coarse tuning port and one of which is lightly coupled and comprises the fine tuning port. The configuration is such that when the loop is locked, following a sweep mode of the coarse tuning voltage, the fine tune voltage is held constant at a predetermined DC level thereby making the fine tuning sensitivity essentially constant as the coarse tuning voltage changes the frequency over the band of interest.

Abstract: A search and confirm frequency synthesizer for generating an output frequency which is a multiple of a predetermined reference frequency is disclosed. A first means is provided for generating a reference frequency signal. A second means is provided for generating a comparison frequency signal. A first spectrum generator means is coupled to the first means and produces a plurality of harmonics of the reference frequency signal. A second spectrum generator means is coupled to the second means and produces a plurality of harmonics of the comparison frequency signal. Means including a phase-locked loop and feedback and control circuitry is operatively coupled to the first and second spectrum generator means for controlling the operation of the phase-locked loop to produce an output signal having a frequency equal to a selected harmonic of the reference frequency signal.

Abstract: A side lock detector to prevent side lock in coherent PSK demodulation. For demodulation purposes it is necessary to recreate the carrier at the receiver. This may be accomplished with a phase-locked loop. However, with plural phase PSK modulation the input signal to the phase-locked loop has energy at side bands spaced at modulation rate intervals from the desired lock frequency as well as at the desired lock frequency. To detect side band lock, a band pass filter monitors the phase detector output of the phase-locked loop. The center frequency of the filter is equal to the modulation rate and the filter band width is very narrow. Only during side lock will significant amounts of energy pass the filter. This energy may be detected by a simple diode detector or the like. A lock inhibit means is provided, responsive to the output of the detector, to drive the voltage controlled oscillator out of a side lock condition.

Abstract: A stabilized frequency oscillating circuit comprises a voltage or current controlled variable frequency oscillator, a delay device receiving the output of the oscillator, an adder for adding the output of the oscillator and the delayed output of the delay device, and a detecting circuit which detects the amplitude of the output of the adder to provide a control signal which varies cyclically with changes in the oscillating frequency of the oscillator which is applied to the latter for locking the oscillating frequency of the oscillator to a predetermined or desired frequency. The oscillating circuit may further have a control circuit by which an additional control voltage or current is superimposed on the cyclically varying control signal for selecting the oscillating frequency to which the variable frequency oscillator is to be locked, or by which either the oscillator output or delayed output is phase-shifted before being applied to the adder.

Abstract: A system for automatically maintaining the center frequency of a swept voltage controlled oscillator. At a known amplitude of sweep voltage input, a lock pulse is actuated. The oscillator output is divided by a number N and applied simultaneously with the reference signal to a phase and/or frequency detector. The detected signal is applied via a gate under the control of such lock pulse to a memorization unit whose output is used to maintain the center frequency.

Abstract: An arrangement for simultaneously producing signals having a decreasing frequency and signals having an increasing frequency. In this arrangement the signals have frequencies which are complementary relative to the double value of a central frequency. The arrangement includes a pair of voltage-controlled oscillators controlled by signals supplied by a control generator. The arrangement is characterized in that for each oscillator there is provided with a phase control loop and that the control generator is of the digital type designed to supply two pairs of digital signals. One pair is applied to the frequency dividers and the other is applied to the oscillators so as to tune them to such a frequency that they are in the operating range of the phase control loop.Use: Radio-electric transmission of data.

Abstract: A phase locked loop including a reference oscillator connected to one input of a loop phase detector the output of which is connected through an integrating low pass filter to a voltage controlled oscillator with the output of the voltage controlled oscillator being mixed with a second frequency and compared to the reference in the loop phase detector. The mixer output is also compared to an output of the reference oscillator shifted 90.degree. in a quadrature phase detector, the output of which controls a lock detector which in turn controls a fixed current sink. The fixed current sink is connected to the integrating low pass filter when the loop is in an unlocked condition so that a linear voltage, ramp signal is applied to the voltage controlled oscillator from the output of the integrating low pass filter.

Abstract: Apparatus and method for providing an automatic frequency tuning system capable of supplying a local oscillator signal with a preselected frequency. The frequency of an output signal of the local oscillator is electronically varied across a frequency region which includes the preselected frequency. The output signal of the local oscillator is combined with the output signal of a reference signal generator. After the combination of the local oscillator signal with the reference oscillator signal produces a preestablished condition which is the result of the local oscillator signal attaining the preselected frequency, the frequency of the local oscillator signal is held constant. The local oscillator signal is thereafter compared to the reference oscillation signal and a change in the local oscillator signal frequency is corrected by means of an automatic frequency control feedback loop containing a discriminator circuit.BACKGROUND OF THE INVENTION1.

Abstract: A variable frequency voltage controlled oscillator is tuned to a selected frequency by applying a varying voltage to the control port of the oscillator to sweep the oscillator signal through a frequency range which includes the frequency of a reference frequency source. The value of the varying voltage is stored at the instant the oscillator frequency coincides with the frequency of the reference source. A dc offset voltage is then added to the stored voltage to produce a sum voltage which is substituted for the varying voltage at the control port of the oscillator to tune the oscillator to the selected frequency. The offset voltage is equal to the difference in the control voltages at the selected and reference frequencies and may be determined from the oscillator control voltage characteristic.

Abstract: A circuit for locking an otherwise unstable oscillator to a frequency standard oscillation by the use of a discriminator and a differential amplifier, which amplifier produces a low-frequency output signal in response to a lack of synchronization between the oscillator being controlled and the reference oscillator.