Transistorized Controls Patents (Class 331/8)
  • Publication number: 20090167442
    Abstract: An integrated circuit, a voltage controlled oscillator (VCO) and a phase-locked loop (PLL). In one embodiment, the VCO includes: (1) a voltage tune line configured to receive a tuning voltage for the VCO and (2) an odd number of ring-coupled delay elements. Each of the delay elements includes: (2A) an inverter having a power supply line being coupled to the voltage tune line and (2B) a feedback path having a gain-attenuating transistor with a gate thereof being coupled to the voltage tune line.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: Texas Instruments Incorporated
    Inventor: Stanley J. Goldman
  • Patent number: 7545223
    Abstract: A PLL circuit according to an embodiment of the present invention includes: a phase comparator to output an up signal and a down signal based on a phase difference between a reference clock signal and a feedback clock signal; an offset correcting circuit to correct a pulse width of at least one of the up signal and the down signal to output a modified up signal and a modified down signal; a first charge pump circuit to increase or decrease a charge pump output voltage to be output in accordance with the modified up signal and the modified down signal; a loop filter to filter out noise of the charge pump output voltage and generate a filter voltage; and a voltage-controlled oscillation circuit having an oscillation frequency controlled based on a voltage value of the filter voltage and outputting an output clock signal.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: June 9, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Masafumi Watanabe
  • Publication number: 20090128206
    Abstract: An apparatus and method for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler are provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 21, 2009
    Inventors: David W. Boerstler, Eskinder Hailu, Masaaki Kaneko, Jieming Qi
  • Publication number: 20090115533
    Abstract: A voltage controlled oscillator may include a plurality of inverting units connected in serial and connected between a first and a second voltage sources to produce an oscillating frequency. Each of the inverting units may have a first current source for producing a constant current that may determine an oscillating frequency, a switching inverter connected between the first voltage source and the first current source that may produce a current having a phase opposite to an output current from a preceding inverting unit, and a frequency adjuster that may control the oscillating frequency by charging and/or discharging the current from the inverting unit.
    Type: Application
    Filed: October 26, 2008
    Publication date: May 7, 2009
    Inventor: Sang-June Kim
  • Patent number: 7528666
    Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: May 5, 2009
    Assignee: Broadcom Corporation
    Inventor: Ramon A. Gomez
  • Patent number: 7508270
    Abstract: In a differential-to-single-ended (D2S) converter having reduced power consumption and excellent duty ratio characteristics, and a phase-locked loop (PLL) circuit having the same, the D2S converter includes a differential amplifier and a latch circuit. The differential amplifier amplifies a differential input signal to generate a differential output signal. The latch circuit latches the differential output signal to generate a single output signal. A bias current of the differential amplifier may be determined according to a bias voltage proportional to a voltage which is provided to a delay cell of a voltage-controlled oscillator (VCO). The D2S converter may have reduced power consumption and excellent duty ratio characteristics, and the PLL circuit having the D2S converter may have a simple circuit configuration and less power consumption.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: March 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Young Jung, Young-Min Kim
  • Patent number: 7504892
    Abstract: A charge-pump includes a first charge-pump sub-circuit having a control terminal that communicates with a first bias voltage line. A first charge-pump mirror sub-circuit regulates current on the control terminal. A first capacitance and a first ripple reducing sub-circuit communicate with the first bias voltage line. A second charge-pump sub-circuit and a second charge-pump mirror sub-circuit communicate with a second bias voltage line. A second capacitance and a second ripple reducing sub-circuit communicate with the second bias voltage line. An output communicates with the first and second charge-pump sub-circuits.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: March 17, 2009
    Assignee: Marvell International Ltd.
    Inventors: Alessandro Pesucci, Shafiq M. Jamal
  • Patent number: 7471160
    Abstract: An integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: December 30, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kai Di Feng, Anjali R. Malladi
  • Patent number: 7400205
    Abstract: The present invention provides a frequency synthesizer capable of switching an oscillation frequency band while maintaining a lock state realized with a small-scale and low-current-consumption circuit configuration, and an oscillation control method of the frequency synthesizer.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: July 15, 2008
    Assignee: Fujitsu Limited
    Inventor: Takahiro Niwa
  • Publication number: 20080094144
    Abstract: This invention adds a non-linear sweep accumulator to the conventional sigma-delta fractional-N divider to produce a N.F value that is a polynomial function of time. This allows any non-linear sweep profiles to be approximated.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Inventor: Wing J. Mar
  • Patent number: 7339438
    Abstract: A phase locked loop includes a phase difference detector for detecting a phase difference between an input clock signal and an output clock signal to generate an up signal and a down signal; a charge pump for raising a level of a control signal by supplying a supply current in response to the up signal, for lowering a level of the control signal by discharging a discharge current in response to the down signal, and for adjusting the supply current in response to a first control voltage and by discharge current in response to a second control voltage in a locked state; a compensator for generating the first and second control voltages corresponding to difference between the up signal and the down signal in the locked state; and a voltage controlled oscillator for varying a frequency of the output clock signal in response to the control signal.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: March 4, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Soo Sohn
  • Patent number: 7339439
    Abstract: A multi-phase realigned voltage-controlled oscillator (MRVCO) achieves phase realignment based on charge injection in the VCO stages. The individual VCO stages provide an oscillating output signals having an asymmetric waveform with substantially different rise and fall times. This ensures that the VCO as a whole has a multiphase impulse response to the charge injection that is strictly positive or strictly negative, and substantially constant so as to be independent of the VCO phase or timing of charge injection. The MRVCO may form a component part of an implementation of a multi-phase realigned phase-locked loop (MRPLL).
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: March 4, 2008
    Assignee: Atmel Corporation
    Inventors: Regis Roubadia, Sami Ajram
  • Patent number: 7304544
    Abstract: A method is described that involves developing a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of the PLL at the system level, a lower level expression that describes a characteristic of one the PLL's basic building blocks.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: December 4, 2007
    Assignee: Sabio Labs, Inc.
    Inventors: Dave Colleran, Arash Hassibi
  • Patent number: 7253691
    Abstract: A clock generator circuit is provided wherein a comparison clock signal is generated by comparing a standard clock signal and an operating clock signal. The comparison clock signal is converted into a current signal. The current signal is converted to multiple current signals and an operating clock signal having multiple varying frequencies is generated based on the multiple current signals.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: August 7, 2007
    Assignee: Fujitsu Limited
    Inventor: Koji Okada
  • Patent number: 7218178
    Abstract: A frequency generator with a phase locked loop includes a loop filter, the transfer function of which has a pair of complex conjugated poles. The present invention provides an optimum and greatly improved compromise, in particular as opposed to the prior art, between phase noise and settling time of the phase locked loop of the frequency generator.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: May 15, 2007
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschunge e.V
    Inventors: Niels Christoffers, Rainer Kokozinski, Bedrich Hosticka, Stephan Kolnsberg
  • Patent number: 7199673
    Abstract: A precharge circuit that initializes an electronic filter to a middle voltage level of an operational voltage includes a filter isolation device, a filter communication device, and an initializing device. The filter isolation device isolates the electronic filter from electronic circuits connected to an input and an output of the electronic filter to segregate the electronic filter from the electronic circuits connected to the input and the output of the electronic filter during a precharge time. The filter communication device allows communication between the precharge circuit and the electronic filter for initializing the charge state during the precharge time. The initializing device provides an initializing signal to the charge state of the electronic filter during the precharge time. The precharge circuit further has a biasing device in communication with the initializing device to provide a mid level control signal providing a reference level of the charge state.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: April 3, 2007
    Assignee: Qualcomm Incorporated
    Inventor: Ozan Erdogan
  • Patent number: 7173494
    Abstract: An offset related to a feedback system for a VCO is quantified and then a parameter of the feedback system is adjusted in response to the quantified offset to correct for the offset. Correcting for offset in a feedback system can improve the performance of a PLL by reducing phase drift between the input signal and the VCO signal. The reduced phase drift can have benefits such as, for example, reduced bit errors and/or improved phase tracking accuracy.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: February 6, 2007
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Michael A. Robinson, Gunter Willy Steinbach, Brian Jeffrey Galloway
  • Patent number: 7146149
    Abstract: A local oscillator (LO) circuit is disclosed which provides improved isolation between the unselected LO source and a mixer. The LO circuit includes a first LO source to generate a first periodic signal cycling at a first frequency, a second LO source to generate a second periodic signal cycling at a second frequency different than the first frequency, a limiter, a first switching element to selectively couple the first LO source to the limiter, and a second switching element to selectively couple the second LO source to the limiter. The limiter improves the isolation of the leakage LO signal (i.e. the unselected LO signal) with respect to the selected LO signal. The improved isolation comes about because the limiter gain associated with the selected LO signal is greater than the gain associated with the leakage LO signal. A receiver and transmitter using the LO circuit are also disclosed.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: December 5, 2006
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Kathiravan Krishnamurthi
  • Patent number: 7126432
    Abstract: A multi-phase realigned voltage-controlled oscillator (MRVCO) achieves phase realignment based on charge injection in the VCO stages with the injection amount proportional to the instantaneous phase error between the VCO output clock and a reference clock. The MRVCO may be incorporated as part of an implementation of a multi-phase realigned phase-locked loop (MRPLL). A separate phase detector, as well as a specific realignment charge pump, may be provided in the PLL for controlling the VCO. The VCO has lower phase modulation noise, so that the PLL has very large equivalent bandwidth.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: October 24, 2006
    Assignee: Atmel Corporation
    Inventors: Regis Roubadia, Sami Ajram
  • Patent number: 7053727
    Abstract: Method and system are disclosed for automated calibration of the VCO gain in phase modulators. The method and system of the invention comprises synthesizing, in a phase modulator, a signal having a given output frequency using a controlled oscillator having a frequency control input, a modulation input, and a feedback loop. A frequency control signal is applied to the frequency control input, and gain variation of the controlled oscillator is compensated for outside of the feedback loop via the modulation input. The method and system of the invention may be employed in any telecommunication system that uses phase and amplitude modulation, including EDGE and WCDMA systems.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: May 30, 2006
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Magnus Nilsson
  • Patent number: 6992536
    Abstract: A voltage-controlled oscillator (VCO) enabling proper gain adjustment with a simple configuration. The VCO includes a first current source for generating a first control current in accordance with the first control voltage and a second current source for generating a second control current in accordance with the second control voltage. A control voltage generation circuit synthesizes the first and second control currents to generate an oscillation control voltage in accordance with the synthesized current. A ring oscillator generates an oscillation signal with a frequency corresponding to the oscillation control voltage. The first current source varies a changing amount of the first control current relative to a change in the first control voltage. The second current source varies a changing amount of the second control current relative to a change in the second control voltage.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: January 31, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masashi Kiyose, Takuya Shiraishi
  • Patent number: 6954110
    Abstract: In some embodiments, a ring oscillator includes a plurality of delay cells coupled in series as a ring, and a replica cell coupled to the delay cells to provide at least one bias signal to the delay cells. The replica cell includes a differential transistor pair formed of a first transistor and a second transistor. The first transistor has a drain terminal and a gate terminal coupled to the drain terminal. The second transistor has a drain terminal and a gate terminal coupled to the drain terminal of the second transistor.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: October 11, 2005
    Assignee: Intel Corporation
    Inventor: Shenggao Li
  • Patent number: 6919769
    Abstract: A self-biased phase locked loop (PLL) circuit includes a charge pump to generate a control voltage, a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage, discharge circuitry coupled to the charge pump to discharge the control voltage, and frequency detection circuitry coupled to the controlled oscillator and the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: July 19, 2005
    Assignee: Intel Corporation
    Inventors: Chee How Lim, Keng L. Wong
  • Patent number: 6909330
    Abstract: A method is described that involves developing a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of the PLL at the system level, a lower level expression that describes a characteristic of one the PLL's basic building blocks.
    Type: Grant
    Filed: April 7, 2002
    Date of Patent: June 21, 2005
    Assignee: Barcelona Design, Inc.
    Inventors: David M. Colleran, Arrash Hassibi
  • Patent number: 6897733
    Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: May 24, 2005
    Assignee: Broadcom Corporation
    Inventor: Myles H. Wakayama
  • Patent number: 6894570
    Abstract: The present invention is related to a fast frequency locking method and architecture realized by employing adaptive asymmetric charge-pump current mechanism, whose circuit is composed of elements such as: a pair of frequency-dependent main current sources, a pair of (rising, descending) frequency-dependent assistant current sources, a digital control circuit, a voltage controlled oscillator, an impedance, a sampling frequency sampled from output frequency of the voltage controlled oscillator, a fixed reference frequency and a phase detector, etc. The difference between the present invention and traditional charge-pump circuit is that the present invention had added at least one pair of frequency-dependent assistant current sources.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: May 17, 2005
    Assignee: Holtek Semiconductor Inc.
    Inventor: Fong-Lieh Liang
  • Patent number: 6885251
    Abstract: Phase locked loop charge pump comprising a drain node (A, B) and at least a cascode transistor (M4, M6) for limiting the variation of the voltage of said drain node, characterized in that an intermediate switch transistor (M3, M5) is placed between the drain node (A, B) and the cascode transistor (M4, M6).
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: April 26, 2005
    Assignee: Alcatel
    Inventors: Thierry Delmot, Frans Theresia Jozef Bonjean
  • Patent number: 6882237
    Abstract: A voltage controlled oscillator generates an output signal whose frequency varies as a first function of a control voltage applied to a control terminal. The voltage controlled oscillator has a wide range of frequency of operation. A gain adjust circuit adjusts the gain of the voltage controlled oscillator such that the first function varies as a second function of the gain. In a preferred embodiment the gain adjust circuit includes a variable impedance that may be external or integrated onto a common chip with the oscillator core.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: April 19, 2005
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Ranjit Singh, Youcef Fouzar, Simon John Skierszkan, Hazem Abdel-Maguid
  • Patent number: 6879218
    Abstract: A correction circuit for a voltage-controlled oscillator (VCO) is arranged outwardly of the voltage-controlled oscillator. The oscillation of the selected frequency and the frequency modulation are carried out independently of each other. The correction circuit includes a frequency selection controller generating a frequency selection signal of the DC potential, and a frequency modulation controller generating a modulation adjusting signal responsive to the input of a modulating signal. When a frequency modulation control signal, including the DC potential of the frequency selection signal and the modulation adjusting signal, is supplied to the voltage-controlled oscillator, the capacitance is lowered even if the frequency is increased, thus allowing the modulation degree to frequency to be decreased to a substantially constant level.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: April 12, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Ken Fujita
  • Patent number: 6867654
    Abstract: An apparatus is disclosed that is an analog phase detector where a summation technique is used to determine the phase difference of the two input waveforms of the phase detector. Instead of multiplying the two signals—a technique used in the prior art—a difference amplifier subtracts one waveform from the other. The difference amplifier produces a waveform whose maximum peak-to-peak amplitude is directly proportional to the phase difference. Feeding this waveform into an envelope detector followed by a low pass filter, we are able to get a DC voltage level that is directly proportional to the phase difference of the two input waveforms.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: March 15, 2005
    Inventor: Arshad Suhail Farooqui
  • Patent number: 6774730
    Abstract: A the charge pump suitable for use in phase-locked loop (PLL) circuits employed by mixed signal integrated circuits (IC) is disclosed. The PLL charge pump includes a constant current source that generates constant current source references with high power supply rejection for the P- and N-channel devices of the charge pump. Pass-gate transistors are inserted between the output terminals and the drains of the respective P- and N-channel devices. The switching transients power supply and ground are confined to the turn on/off leads of the pass-gate transistors and, thus, are isolated from the constant current source P- and N-channel devices. In exemplary embodiments of the invention, the constant current of the P- and N-channel devices may be made programmable and used for controlling the range of the current controlled oscillator of the PLL circuit.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventor: Frank Gasparik
  • Patent number: 6734739
    Abstract: The phase comparator in a phase locked loop synthesizer has a identical first and second transmission gates connected to a front row and a back row of 2N−1 gate delay elements, respectively. Third and fourth transmission gates are permanently set to an ON setting. The first transmission gate and NAND gates operate as a gate delay element when a COUNT signal is at a low logical level and operate as a ring oscillator when the COUNT signal is at a high logical level.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: May 11, 2004
    Assignee: Mitsubishikdenki Kabushiki Kaisha
    Inventor: Tadashi Kawahara
  • Patent number: 6680654
    Abstract: A phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A phase detector (18) is activable in response to a gating signal (20) to generate an error signal representing a difference between a reference frequency signal and the variable output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. An offset cancellation circuit (22) is coupled to the loop filter (12). In response to an error signal representing phase offset of the phase locked loop (10), the offset cancellation circuit (22) supplies a compensating signal to reduce the phase offset.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: January 20, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Gerald R. Fischer, Talley J. Allen, Ken K. Tsai
  • Patent number: 6583675
    Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: June 24, 2003
    Assignee: Broadcom Corporation
    Inventor: Ramon A. Gomez
  • Patent number: 6570457
    Abstract: The present invention provides a phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A feedback frequency divider (16) coupled to the controlled oscillator (14) is operable to generate a divided frequency signal from the variable output frequency signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the divided frequency signal. A sample and hold circuit (22) is activable in response to a gating signal (20) derived from the reference frequency, to sample the error signal and generate a sampled signal. A loop filter (12) filters the sampled signal and generates the tune signal.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: May 27, 2003
    Assignee: Northrop Grumman Corporation
    Inventor: Gerald R. Fischer
  • Patent number: 6563389
    Abstract: A phase locked loop (10) for generating an output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the output frequency signal in response to a tune signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. The loop filter (12) includes a bandwidth switching circuit (19) to vary the filter characteristics. A charge cancellation circuit (22) is coupled to the loop filter (12). In response to the error signal, the charge cancellation circuit (22) cancels errors associated with the bandwidth switching circuit.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: May 13, 2003
    Assignee: Northrop Grumman Corporation
    Inventor: Gerald R. Fischer
  • Patent number: 6549080
    Abstract: A phase-locked loop circuit is described and has a digital circuit section and an analog circuit section that are fed with different supply voltages. Control signals generated by the digital circuit section are conducted to the analog circuit section via level converters and therefore can control functions in the analog circuit section.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: April 15, 2003
    Assignee: Infineon Technologies AG
    Inventors: Edmund Götz, Markus Scholz, Shen Feng
  • Patent number: 6538517
    Abstract: The invention provides a structure, method and means for receiving a reference frequency and a variable frequency, differentiating the frequencies, and generating a logic pulse in response to a first frequency leading a second frequency, the frequencies having a small phase difference. In an aspect, the invention maintains a signal when the reference frequency and the variable frequency transition. In another aspect, the invention provides additional timing balance to prevent early generation of the logic pulses. In another aspect, the logic pulses drive a charge pump used in one of a phase-locked loop and a delay-locked loop.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: March 25, 2003
    Assignee: Intel Corporation
    Inventor: Shih-Lien L. Lu
  • Patent number: 6529082
    Abstract: A charge pump has two charge pump nodes. The first charge pump node has a first current source (CS) with a source terminal connected to a positive supply voltage and an output terminal connected to the first charge pump node with a P channel metal oxide silicon transistor (PFET) controlled by a first control signal. The first charge pump node is also connected to a second CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a second control signal. The second charge pump node has a third CS with a source terminal connected to the positive supply voltage and an output terminal connected to the second charge pump node with a PFET controlled by a third control signal. The second charge pump node is also connected to a fourth CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a fourth control signal.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Gary D. Carpenter, Hung C. Ngo, Kevin J. Nowka
  • Patent number: 6525613
    Abstract: An efficient current feedback buffer is revealed. The buffer is useful in power supplies for a number of analog and digital devices, including CMOS voltage controlled ring oscillators, frequency synthesizers, delay locked loops, phase accumulators, and phase locked loops. The power supply and buffer maintains a low impedance output to the load, regulates the voltage output of the supply, and rejects power line noise.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 25, 2003
    Assignee: Infineon Technologies AG
    Inventor: Sasan Cyrusian
  • Patent number: 6515520
    Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO) and a pair of charge pump circuits (CP) and provides a stable oscillation clock signal. A phase comparator compares a reference clock signal with an oscillation clock signal generated by the VCO and generates two comparison signals. The comparison signals are input to the first CP, which generates a first CP output signal. The first CP output signal is filtered with a first low pass filter (LPF) and the filtered signal (control voltage) is provided to the VCO, which produces the oscillation clock. The second CP receives two clock signals and generates a second CP output signal. The second CP output signal is filtered with a second LPF and the filtered signal is converted to a digital signal with an A/D converter. The digital signal is applied to a bias circuit, which then produces first and second control voltages.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: February 4, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Masashi Kiyose
  • Patent number: 6512419
    Abstract: A local oscillator calibrator comprises a main charge pump that drives a voltage controlled oscillator (VCO) through a loop filter. A second, replica charge pump can also drive the VCO, but is setup to output only its most positive or most negative analog output control voltage. Since the construction and characteristics of the replica charge pump duplicate the main charge pump, the main charge pump's minimum and maximum analog control outputs can be cloned out to the VCO on demand. A VCO calibration procedure therefore includes switching the VCO to each of its ranges set by a bank of fixed capacitors, and using the replica charge pump to drive the VCO to its minimum and maximum frequency for each range setting. The min-max frequency data is stored in a lookup table, and operational requests to switch to a new channel frequency can be supported with a priori information about which fixed-capacitor range selection will be best.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: January 28, 2003
    Assignee: Cisco Sytems Wireless Networking (Australia) Pty Limited
    Inventors: Andrew Adams, Neil Weste, Stephen Avery
  • Patent number: 6504436
    Abstract: A tuning circuit includes an oscillator that receives an oscillating input signal and a control signal, and generates an oscillating output signal. The control signal is obtained from a frequency control circuit that compares the phases of the oscillating output signal and a reference signal. The control signal controls the transconductance of a transconductance element in the oscillator, thereby controlling the oscillator output frequency. The oscillating input signal is obtained from an amplitude control circuit that detects an amplitude limit of the oscillator output. The oscillator output amplitude is responsive to the oscillating input signal. Frequency control and amplitude control in this tuning circuit are mutually independent, so their respective control loops remain stable under all frequency and amplitude combinations.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: January 7, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Akira Horikawa, Akira Yoshida, Takashi Taya
  • Patent number: 6498538
    Abstract: System and method for providing low noise signal having a broad tuning range (1 GHz to 10 GHz, or larger), with associated jitter no more than about 10 percent of the selected period of a target output signal. In a first stage, a ring-based VCO phase locked loop system provides a broad tuning range with some associated noise, and a second stage in a first state is relatively transparent, with no substantial differential attenuation based on frequency. After phase lock is achieved, the second stage is switched to a second state with low associated noise and high differential attenuation based on input signal frequency.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: December 24, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: Ming Qu, Ji Zhao
  • Patent number: 6466098
    Abstract: Apparatus for generating an oscillating signal in a desired phase relationship with an input signal, including a mixer arranged to receive a pair of reference signals oscillating at a common frequency and having a phase offset between them, and to mix the reference signals in variable proportions according to the value of input weighting signals to generate an output signal. A comparator is to compare the phase of the output signal with that of the input signal to determine whether the signals are in the desired phase relationship and, if not, to output one or more control signals indicative of the required adjustment in the phase of the output signal to achieve the desired phase relationship. An adjustable ring oscillator including a plurality of stages is connected in a ring and arranged to propagate oscillations around the ring.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: October 15, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew Pickering
  • Patent number: 6466100
    Abstract: A voltage controlled oscillator of a phase locked loop circuit having digitally controlled gain compensation. The digital control circuitry provides binary logic input to the voltage controlled oscillator for a digitally controlled variable resistance circuit, a digitally controlled variable current transconductor circuit, or differential transistor pairs having mirrored circuitry for adjusting the V-I gain.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: October 15, 2002
    Assignee: International Business Machines Corporation
    Inventors: Allan L. Mullgrav, Jr., Michael A. Sorna
  • Patent number: 6456166
    Abstract: Object of the present invention is to provide a semiconductor integrated circuit and a voltage control oscillator capable of performing stable oscillating operation and generating an oscillating signal with little jitter. The present invention has a VCO cell, a replica cell constituted in the same way as the VCO cell, an operational amplifier, and a current generator bias circuit. A NMOS transistor is connected between a node in the VCO cell and a ground terminal. The operational amplifier controls the voltages of a node in the replica cell and the node in the VCO so that they are equal to the reference voltage. Because of this, the PMOS transistor composing of a current generator always operates at pentode region, thereby stabilizing the oscillating operation. Furthermore, according to the present embodiment, a CC jitter at low frequency side can be reduced more efficiently than that of the conventional circuit.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: September 24, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoaki Yabe
  • Patent number: 6404290
    Abstract: A regulator circuit for providing a regulated voltage, comprises a driver for generating a drive signal, and a charge pump having a first voltage input coupled to a first voltage source, being responsive to the drive signal, to generate a pump voltage from the first voltage source. An amplifier having a reference input is coupled to a reference voltage, a sense input is coupled to a sense signal representative of the pump voltage, and an output is operable in response to a difference between the reference voltage and the sense signal, to control the driver. A switch is coupled from the amplifier output to an output of the charge pump such that the pump voltage is controllably boosted by the amplifier output through the switch.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: June 11, 2002
    Assignee: Marvell International, Ltd.
    Inventor: Thart Fah Voo
  • Patent number: 6356160
    Abstract: A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: March 12, 2002
    Assignee: Xilinx, Inc.
    Inventors: Moises E. Robinson, Bernard L. Grung, Yiqin Chen
  • Patent number: 6356158
    Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: March 12, 2002
    Assignee: Xilinx, Inc.
    Inventor: Austin H. Lesea