Abstract: Briefly, a transmitter that includes first and second fractional N synthesizers that may generate outphased modulated signals. First and second sigma-delta modulators may control the modulation of the first and second fractional N synthesizers.

Abstract: Provided is a frequency modulation circuit 1 for outputting a highly precise frequency-modulated signal regardless of variation in a characteristic of a VCO 15. A correction value calculation section 17 calculates a correction value Vt2 based on a voltage value (Vtx?Vt1) resulting from subtracting a control voltage Vt1, which is generated by a control voltage generation section 11, from a control voltage Vtx at which a sensitivity of the VCO 15 is maximized. A variable amplifier 18 amplifies the correction value Vt2. An addition section 13 outputs a control voltage Vt3, which results from adding the amplified correction value Vt2 to the control voltage Vt1, to the VCO 15 via a DAC 14.

Abstract: A phase tracking system includes a source of an input signal representing a received symbol. A phase rotator has a first input terminal which is responsive to the input signal, a second input terminal which is responsive to a phase correction signal, and an output terminal which produces a phase adjusted output signal. A decision element generates an ideal signal representing the received symbol in response to the phase adjusted output signal. A phase adjuster, which has full phase wrap-around capability, generates the phase correction signal in response to the phase difference between the phase adjusted output signal and the ideal signal.

Abstract: A synthesizer arrangement includes an oscillator, a phase detector, and a loop filter that form a phase-locked loop. The loop filter is coupled to a control unit to activate a respective set of internal states out of a plurality of sets of internal states.

Abstract: An apparatus includes a phase locked loop (PLL). The phase locked loop (PLL) has coarse tuning (CT), fine tuning-integer (FT-i), fine tuning fractional (FT-f), frequency modulator tuning-fractional (FMT-f), and narrowband (NB) modes of operation.

Abstract: An apparatus for providing a two point phase/frequency modulation system is disclosed herein. The apparatus includes a first network configured to introduce an offset to center a signal applied to a VCO. The apparatus further includes a second network configured to set a gain of the VCO. A phase tracking network is configured to dynamically adjust the offset and the gain.

Abstract: A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The adaptation algorithm determines a true stochastic gradient between a forcing function and its corresponding system measure to estimate the system parameters being adapted. A momentum term is generated and injected into the adaptation algorithm in order to stabilize the algorithm by adding inertia against any large transient variations in the input data. In the case of adaptation of DCO gain KDCO, the algorithm determines the stochastic gradient between time varying calibration or actual modulation data and the raw phase error accumulated in an all digital phase locked loop (ADPLL). Two filters preprocess the observable data to limit the bandwidth of the computed stochastic gradient providing a trade-off between sensitivity and settling time.

Abstract: Linear wideband phase modulation system. Apparatus is provided for linear phase modulation utilizing a phase-locked loop. The apparatus includes a limiting circuit that restricts a range of a modulation signal that is coupled to a voltage controlled oscillator (VCO) associated with the phase-locked loop, and a linearizing circuit that reshapes the modulation signal to improve linearity.

Abstract: In a frequency modulator, a VCO oscillates at a frequency according to a voltage applied to an input terminal. A divider divides an output signal of the VCO. A phase comparator compares the output of the divider with a reference clock signal and outputs a voltage corresponding to a phase difference. A loop filter is provided on a path leading from an output terminal of the phase comparator to the input terminal of the VCO, and the loop filter removes a high-frequency component of an output voltage of the phase comparator. A terminal for inputting a modulation signal is provided in the loop filter, separately from a terminal connected with the path leading from the output terminal of the phase comparator to the input terminal of the VCO.

Abstract: A method and system for generating noise in a frequency synthesizer are provided. The method includes generating a noise portion of an input signal within the frequency synthesizer and appending the noise portion to a control portion of the input signal.

Abstract: A multiple path angle modulator includes a closed secondary loop added to a main control loop to automatically adjust a scaling factor related to high frequency gain. The main control loop is configured as a primary path to process the low frequency portion of the angle modulation signal, and the secondary loop is configured as an auxiliary path to process the high frequency portions of the angle modulation signal. The secondary loop senses calibration information and uses it to continuously calibrate the gain within the modulation loop in real time while the system performs its primary operation, thereby eliminating the need for a system shut down or calibration specific timing, such as a lapse time, to balance the modulation paths. Calibration is continuously performed as a background process. The angle modulator is applicable to all modulation type systems.

Abstract: A two-point polar modulator for generating a polar-modulated signal based on an amplitude information and a phase information includes a two-point modulation phase-locked loop which is implemented to enable a frequency setting depending on a first control value via a feedback path of the two-point modulation phase-locked loop and to enable a frequency setting depending on a second control value, directly, bypassing the feedback path, wherein the two-point modulation phase-locked loop is implemented to provide a phase-locked loop output signal depending on the two control values.

Abstract: A charge pump-based frequency modulator is provided. The charge pump-based frequency modulator comprises an analog phase correction path comprising a varactor and a charge pump. The varactor is coupled to an output of the charge pump-based frequency modulator. The charge pump is coupled to a node between the varactor and the output and receives a signal containing the modulated data.

Abstract: An arrangement for determining a gradient factor for a digitally controlled oscillator has a data alignment device and an identification device. The data alignment device can be supplied a modulation signal, a phase error signal and an oscillator control word. The data alignment device is configured to output a modulation setting word based on the modulation signal, output a time interval magnitude based on the phase error signal and a reference interval, and output an oscillator modulation word based on the oscillator control word. The identification device is configured to adapt and output the gradient factor based on the modulation setting word, the time interval magnitude and the oscillator modulation word.

Abstract: Devices (1) for exchanging ultra wide band signals comprise frequency translating stages (20,30) for frequency translating signals and oscillating stages (40) for supplying main inphase/quadrature oscillation signals to the frequency translating stages (20,30). By providing the oscillating stages (40) with polyphase filters (43,44) for reducing harmonics in oscillation signals, the main oscillation signals will be sufficiently clean. The oscillating stages (40) comprise mixers (46) for converting first inphase/quadrature oscillation signals and second inphase/quadrature oscillation signals into the main oscillation signals. The polyphase filters (43,44) may be located before and after the mixers (46). Frequency selectors (45) replace prior art multiplexers located after the mixers (46).

Abstract: A method and apparatus for frequency modulating a PWM involves 1) generating a high frequency carrier signal much greater in frequency than the PWM signal; 2) modulating the high frequency signal to generate a spread spectrum carrier signal; and, 3) retiming a PWM signal with this high frequency SS carrier signal so that the binary transitions of the PWM signal are aligned with the frequency varying carrier signal. In another embodiment, a PWM oscillator is driven by a second, FM oscillator having spread spectrum characteristics. In another embodiment a PWM oscillator is driven and modulated by a counter/frequency divider comprised of modules.

Abstract: A frequency synthesizer modulates a signal by directly modulating a signal input to a voltage controlled oscillator (VCO) associated with the frequency synthesizer. The modulation signal has a bandwidth greater than a closed-loop bandwidth of the frequency synthesizer. The frequency synthesizer suppresses the modulation signal from a feedback path of the synthesizer.

Abstract: A radio frequency modulator based on direct frequency/phase modulation of output signal of a controllable oscillator (724) that is a part of a phase locked loop (PLL) provides a direct modulator that is able to operate over a wide frequency range with a flat frequency response. A modulation signal is digitally processed (721, 730) before injection to a high-pass path of a direct modulator. Applicability of digital signal processing is based on the fact that the modulation signal is a base band signal. Therefore, the modulation signal (702) occupies such a band in the frequency domain so that a sufficient ratio of a sampling rate to an upper edge frequency of the modulation signal can be achieved. Digital processing is used for compensating an effect of non-flat high-pass PLL transfer function and/or to perform pre-distortion of the input signal of a controlled oscillator to compensate an effect of non-linearity of a controlled oscillator.

Abstract: Noise detection is performed by using the output of the phase comparator that the PLL comprises. The phase comparator outputs a signal that is based on the phase difference between the output of the voltage controlled oscillator and the reference signal. The phase difference reflects the effect of noise on the PLL and, in addition to the characteristics of the noise itself, such as the wave height value of the noise and the frequency component thereof, reflects the tolerance of the PLL to noise, whereby the level of risk that the system can actually be caused to malfunction can be judged.

Abstract: A frequency modulator is provided for generating an output signal with a frequency that is a function of a modulation signal, wherein the modulation signal can assume N?2 different discrete modulation values, and a predetermined frequency value of the output signal is associated with each modulation value, containing: a) a closed phase locked loop with a loop filter for providing a first control voltage, with a voltage controlled oscillator for generating the output signal, and with a switchable frequency divider for deriving a frequency-divided signal, and b) a modulation unit that is designed to provide, at a first output, values of a divisor that are a function of the modulation signal, and at a second output, a second control voltage that is a function of the modulation signal, c) wherein the oscillator has a first control input connected to the loop filter and has a second control input connected to the second output of the modulation unit, and is designed to generate the output signal as a function of t

Abstract: Briefly, according to embodiments of the invention, there is provided a method and an apparatus to compensate for a closed loop response error of a transfer function of a phase locked loop unit.

Abstract: Embodiments of the invention describe a method and a device for digital measurement of the momentary frequency response of the phase-path component of a modulator, based on digitally sampling the output frequency of the modulator by clocks and count values derived from components already used by the modulator, e.g. a counter in a divider, and a reference frequency based on a crystal oscillator.

Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

Abstract: A single-point modulator (1) has a PLL circuit (2) and a programmable frequency divider (7) whose control connection is connected to a circuit branch for injecting a digital modulation signal (15) which is arranged in the feedback path of the PLL circuit (2). The circuit branch contains a sigma-delta modulator (9) which, in turn, has a digital filter (24) having a transfer function H(z). The noise transfer function NTF(z) of the sigma-delta modulator (9) is given by the function NTF(z)=1?H(z).

Abstract: Correction of glitches output from a delta-sigma modulator is accomplished using an integer boundary crossing detector and a FIR filter. The detector monitors a portion of an input to the modulator. The detector recognizes a transition from an all 1's bit pattern to an all 0's bit pattern or vice versa as representative of potential for a glitch to be present on the output of the modulator. The detector responsively generates condition detection output. Receipt of such condition detection output triggers the generation of a correction signal by the filter. The correction signal is, at least substantially similar, in magnitude but opposite in sign from to the expected glitch at the output of the modulator. The correction signal is added to the output of the modulator to substantially eliminate the glitch.

Abstract: Apparatus and method for generating first, second and third carrier frequencies of 3432 MHz, 3960 MHz and 4488 MHz respectively, for use in a wireless transmission system deploy only first and second PLLs which are configured to generate 6336 MHz and 2640 MHz signals respectively with only in-phase components. Frequency dividers are employed for frequency-dividing the 6336 MHz signal severally by 2, 4, and 12 to obtain frequency-divided intermediate outputs with both in-phase and quadrature components. The intermediate output components and other intermediate signal components are selectively combined in a mixer (e.g., a single side-band mixer), for deriving the first, second and third carrier frequencies of 3432 MHz, 3960 MHz and 4488 MHz with both in-phase and quadrature components. The invention has application in UWB, WPAN, WLAN, or other wireless systems and has the simplicity and advantages of using only two PLLs instead of the prior art arrangements of three PLLs.

Abstract: A system is described for generating a discrete noise-shaped variable switching frequency signal that may be used to define a digital pulse width modulation (“PWM”) period. The system may define a switching frequency waveform that may be used to generate a current switching frequency signal as a function of a system clock. The system may quantize the current switching frequency signal to generate a discrete switching frequency signal that is realizable with the system clock. The system may detect quantization noise and input the noise into the current switching frequency signal to eliminate or reduce discrete tones at the switching frequencies of a PWM signal spectrum.

Abstract: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

Abstract: A direct division modulator is provided. The direct division modulator includes a symbol mapper converting the input data from a binary bitstream to a desired frequency deviation, such as where the frequency deviation data encodes the information from the bitstream. A converter generates a divide value using the desired frequency deviation information, and a summer adds an average value to the divide value. A converter quantizes the divide value and shapes quantization noise associated with the quantized divide value. A divider modulates a reference signal with the quantized divide value and generates an output signal.

Abstract: A system and method for modulating a phase component of an electromagnetic signal includes a phase/frequency detector having first and second inputs and an output. The first phase/frequency detector input may be configured to receive a reference signal. The system may include an oscillator having an input and an output. The oscillator may be configured to generate a desired oscillator output signal at its output. A divider may be configured to receive the oscillator output signal. The divider may have a divider count input and a divider carryout output that may be connected to the second phase/frequency detector input. A loop filter may be connected in series between the phase/frequency detector output and the oscillator input. The loop filter has a transfer function including at least two frequency response rate change points, where each of the frequency rate change points corresponds to a pole or a zero in the transfer function.

Abstract: A control loop (10) for producing an output signal with a stable nominal frequency is provided. The control loop includes inputs for reference (11) and oscillator (25) output signals, a beat frequency generator (12) for producing a signal with a frequency that is the difference between the oscillator and reference signal frequencies, an ADC (14) to convert the beat frequency to a digital beat frequency signal, an estimator (17) for estimating the frequency or phase of the beat signal, an adder (18) for combining an offset and modulation signal and the estimated frequency or phase of the beat signal into an added signal, and a DAC (23) for generating an analogue control signal for controlling the oscillator output frequency.

Abstract: A phase locked loop for outputting a high frequency signal by executing synchronization and frequency conversion based on an input signal includes a control-type oscillator, and a phase comparator circuit for comparing a phase of the input signal and a phase of an output signal from the control-type oscillator, and outputting and supplying a phase error signal to the control-type oscillator via a loop filter. The phase locked loop further includes a correction signal generating circuit for adding a high frequency component of the phase error signal outputted from the phase comparator circuit to the phase error signal as a correction signal. In accordance with this phase locked loop, the high frequency component of the phase error signal outputted from the phase comparator circuit is added to an output signal of a loop filter as the correction signal so that a flat frequency characteristic can be acquired over a broad band.

Abstract: A clock generator circuit, comprising: a multi-phase clock signal generator for generating a plurality of clock signals having a same frequency but difference phases according to a reference clock signal; a modulation device for generating a phase modulation signal through Delta-Sigma modulation; and a phase modulator, which is electrically coupled to the modulation device, for selecting one of the clock signals to be a modulated clock signal according to the phase modulation signal.

Abstract: A spread-spectrum clock signal generator includes a circuit loop receiving a reference signal at a reference frequency and adapted to generate an output signal at an output frequency dependent on and locked to the reference frequency, and a modulator circuit generating a modulation signal at a modulation frequency; the modulation signal is injected into the circuit loop to induce a modulation of the frequency of the output signal with respect to the frequency dependent on the reference frequency. The circuit loop is a frequency-locked loop and has a bandwidth sufficiently higher than the modulation frequency, so that the output frequency tracks the modulation signal. Frequency-offset correction circuit is further provided, for evaluating a frequency offset between an average frequency of the output signal and the frequency dependent on the reference frequency, and for generating a frequency-offset correction signal which is injected into the circuit loop for correcting the evaluated frequency offset.

Abstract: A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an input for supplying the integer and fractional components for the frequency division ratio which is to be set, includes an input for supplying a phase correction signal. To produce the phase correction signal, the phase locked loop further includes a phase correction apparatus. The phase correction signal preferably contains a signal component with an exponential profile, and is supplied to the control circuit for producing a frequency division ratio for the frequency divider circuit such that it compensates for a phase drift in the output signal from the voltage controlled oscillator in the phase locked loop.

Abstract: A frequency synthesizer modulates a signal by directly modulating a signal input to a voltage controlled oscillator (VCO) associated with the frequency synthesizer. The modulation signal has a bandwidth greater than a closed-loop bandwidth of the frequency synthesizer. The frequency synthesizer suppresses the modulation signal from a feedback path of the synthesizer.

Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal, the signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a control unit for controlling the control signal generator to adjust the control signal in a calibration mode to thereby adjust a frequency of the synthesized signal, wherein the phase/frequency detector does not output the detected signal to the control signal generator in the calibration mode; a detecting device for detecting the synthesized signal to generate a calibrating signal in the calibration mode; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered signal; and a modulating device for modulating the filtered signal to generate the dividing factor.

Abstract: Provided is a frequency modulation circuit for outputting a frequency-modulated signal with a high precision. A VCO 13 includes a first variable capacitor 132 having a predetermined capacitance change rate, and a second variable capacitor 133 having a greater capacitance change rate than that of the first variable capacitor 132. When the frequency modulation circuit is applied in a narrowband modulation method, a switch 15 switches a connection path of an open loop such that an input terminal and the first variable capacitor 132 are connected. On the other hand, when the frequency modulation circuit is applied in a wideband modulation method, the switch 15 switches the connection path of the open loop such that the input terminal and the second variable capacitor 133 are connected.

Abstract: The present invention relates to a method for stabilising the operation of a voltage controlled oscillator driven by a phase locked loop, the voltage controlled oscillator delivering an RF signal and receiving through at least one spurious path a harmonic component of a frequency equal or proximate to that of the RF signal, capable of disturbing its operation by injection pulling. According to the present invention, the method comprises a step of injecting into the voltage controlled oscillator an injection pulling compensation signal, the phase and the amplitude of which are adjusted so as to neutralise the effects of the spurious harmonic component. Application particularly to phase modulation IQ circuits in radiotelephony.

Abstract: A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The adaptation algorithm determines a true stochastic gradient between a forcing function and its corresponding system measure to estimate the system parameters being adapted. A momentum term is generated and injected into the adaptation algorithm in order to stabilize the algorithm by adding inertia against any large transient variations in the input data. In the case of adaptation of DCO gain KDCO, the algorithm determines the stochastic gradient between time varying calibration or actual modulation data and the raw phase error accumulated in an all digital phase locked loop (ADPLL). Two filters preprocess the observable data to limit the bandwidth of the computed stochastic gradient providing a trade-off between sensitivity and settling time.

Abstract: A two-point modulation device includes a first sigma-delta modulator (SDM), a second SDM and an analog phase-locked loop (PLL). The first SDM provides a division control signal based on channel data and modulation data. The second SDM provides a feedforward path modulation signal based on the modulation data. The analog PLL receives the division control signal and the feedforward path modulation signal, and generates a voltage-controlled oscillating frequency signal that follows a reference frequency signal.

Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. An input baseband signal is interpolated and upconverted in the digital domain to an IF. The LO operates at a frequency which is a n/m division of the target RF frequency fRF. The IF frequency is configured to ½ of the LO frequency. The upconverted IF signal is then converted to the analog domain via digital power amplifiers followed by voltage combiners. The output of the combiners is band pass filtered to extract the desired replica.

Abstract: Phase locked loop circuit (105) having a double entry VCO (158) and two independent charge pumps (171, 172), each connected with one of the entries of the VCO. Each of the VCO entries has a different gain coefficient, thereby allowing a better optimisation and control of the device bandwidth and a reduced phase noise. Can be employed in radio transmitters and/or receivers and allows simultaneous and precise FM modulation both inside and outside the PLL bandwidth.

Abstract: A delta-sigma modulated fractional-N PLL frequency synthesizer is provided. The frequency synthesizer includes a phase frequency detector for receiving a reference signal with a reference frequency (Fref) and an overflow signal to output a phase difference signal by detecting a phase and frequency difference between the reference signal and the overflow signal; a charge pump for generating an output current pulse in response to the phase difference signal; a loop filter for filtering the charge pump output current pulse and generating a corresponding control voltage; a VCO for generating a VCO output signal with a voltage controlled frequency (Fvco) in response to the control voltage; and a delta-sigma modulator, with a clock input terminal for receiving the VCO output signal, an overflow output terminal for generating the overflow signal and an integer input terminal, for determining the ratio of the VCO frequency (Fvco) and the reference frequency (Fref).

Abstract: Disclosed herein is a method and apparatus used to create an idealized voltage controlled oscillator (VCO) which allows very high modulation rates without the expected phase noise (jitter) which nominally comes from wide bandwidth VCOs. In this fashion, high quality VCOs that typically offer pure signals at the cost of small tuning bandwidths can be enhanced to create idealized VCOs that offer both high quality (low jitter) and high tuning bandwidths. A high-frequency phase modulator and control voltage processing is used in conjunction with a natural VCO to create a method and apparatus in accordance with the invention. The control voltage processing includes separation of frequency components of the controlling voltage and electrical integration of high-frequency control voltage components directed to the phase modulator to create the overall voltage-to-frequency transfer function for the ideal VCO.

Abstract: The present invention relates generally to the field of frequency modulation, and in particular to dual port frequency modulators. The present invention provides a frequency modulator comprising a phase lock loop circuit (108) for receiving and modulating a carrier signal according to the low frequency component of a modulating signal, the phase lock loop circuit comprising a voltage controlled oscillator (118) for outputting a modulated carrier signal and a loop filter (116) for outputting a steering voltage to the VCO, the VCO having a tank circuit (120) comprising a voltage controlled capacitance (VAR1). The frequency modulator also comprises an external voltage controlled capacitance (122) which is arranged to modulate its capacitance according to a high frequency component of the modulating signal, the second voltage controlled capacitance being coupled to the tank circuit.

Abstract: A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.

Abstract: A frequency generation apparatus and a method are provided. The frequency generation apparatus for generating a plurality of center frequencies for use in multi-band hopping communication, includes: an oscillator generating an oscillation frequency; a reference frequency generator multiplying the oscillation frequency by a first multiplication rate to generate a reference frequency; a compensation frequency generator multiplying the oscillation frequency by a second multiplication rate to generate a compensation frequency for compensating for the influence of a frequency offset of the oscillation frequency; and a center frequency generator generating the plurality of center frequencies using the reference frequency and the compensation frequency. Therefore, by compensating for the influence of a frequency offset of an oscillation frequency on the generation of center frequencies, it is possible to generate stable center frequencies.

Abstract: A method and apparatus improves the stability and noise performance of frequency synthesis and synchronization circuits. A cancellation circuit provides an error signal that is a measure of integrated quantization error in a delta-sigma modulator that controls the ratiometric division factor in a fractional-N phase-lock loop (PLL). The error signal is fed to the loop filter of the phase-lock loop as a correction signal via a differentiator (high-pass filter). The high pass filter removes substantially all in-band components from the cancellation signal, which reduces the linearity requirement on the cancellation signal path. The cancellation signal can be tapped from an internal numerical integrator of the delta-sigma modulator that is then converted to an analog signal, that is then filtered and combined with the phase comparator output in the loop filter.