Terminal And Resistance Element Disposed In Flat Layers Patents (Class 338/328)
  • Patent number: 9881719
    Abstract: A chip resistor includes first and second electrodes spaced apart from each other, a resistor element arranged on the first and the second electrodes, a bonding layer provided between the resistor element and the two electrodes, and a plating layer electrically connected to the resistor element. The first electrode includes a flat outer side surface, and the resistor element includes a side surface facing in the direction in which the thirst and the second electrodes are spaced. The outer side surface of the first electrode is flush with the side surface of the resistor element. The plating layer covers at least a part of the outer side surface of the first electrode in a manner such that the covering portion of the plating layer extends from one vertical edge of the outer side surface to the other vertical edge.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: January 30, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Kenichi Harada, Masaki Yoneda
  • Patent number: 9269942
    Abstract: A secondary battery including a circuit board unnecessitating a cut-out portion is provided. The secondary battery includes a battery cell having a cell tab, a protective circuit module electrically connected to the cell tab and having a circuit pattern formed therein, and a connection tab attached to the protective circuit module and electrically connected to the circuit pattern, wherein the connection tab includes a conductive layer adhered to the protective circuit module and including a first plating layer formed on the conductive layer and a second plating layer formed on the first plating layer, and the cell tab is welded to the connection tab.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 23, 2016
    Assignee: SAMSUNG SDI CO., LTD.
    Inventor: Wonil Lee
  • Publication number: 20140232515
    Abstract: A chip resistor includes first and second electrodes spaced apart from each other, a resistor element arranged on the first and the second electrodes, a bonding layer provided between the resistor element and the two electrodes, and a plating layer electrically connected to the resistor element. The first electrode includes a flat outer side surface, and the resistor element includes a side surface facing in the direction in which the thirst and the second electrodes are spaced. The outer side surface of the first electrode is flush with the side surface of the resistor element. The plating layer covers at least a part of the outer side surface of the first electrode in a manner such that the covering portion of the plating layer extends from one vertical edge of the outer side surface to the other vertical edge.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 21, 2014
    Applicant: ROHM CO., LTD.
    Inventors: Kenichi HARADA, Masaki YONEDA
  • Patent number: 8558656
    Abstract: An over-current protection device comprises a resistance material with positive or negative temperature coefficient and an upper surface and a lower surface; a first electrode layer having a first groove, disposed on the upper surface; a first surface mount pad disposed on the upper surface; a second electrode layer disposed on the lower surface, electrically connecting to the first surface mount pad; a second surface mount pad disposed on the lower surface, electrically connecting to the first electrode layer; a second groove electrically separating the first surface mount pad from the first electrode layer; and a third groove electrically separating the second electrode layer from the second surface mount pad. The first groove divides the first electrode layer into two connected regions. The first and second surface mount pads are separated from each other and one end of the first groove connects to the second groove.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 15, 2013
    Assignee: Polytronics Technology Corp.
    Inventors: David Shau Chew Wang, Chun Teng Tseng
  • Patent number: 8482373
    Abstract: An over-current protection device comprises a PTC material layer, first and second conductive layers, first and second electrodes, and four conductive vias. The first and second conductive layers are in physical contact with first and second surfaces of the PTC material layer, respectively. The first electrode contains a pair of first metal foils, and the second electrode contains a pair of second metal foils. The four conductive vias are formed at the corners each defined by two adjacent planar lateral surfaces. Two conductive vias connect the pair of the first metal foils and the first conductive layer, and the other two conductive vias connect the pair of the second metal foils and the second conductive layer. The ratio of the sum of the cross-sectional areas of the conductive vias to a form factor area of the device is in the range of 7% to 20%.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: July 9, 2013
    Assignee: Polytronics Technology Corp.
    Inventors: Chun Teng Tseng, David Shau Chew Wang
  • Patent number: 8461956
    Abstract: An over-current protection device includes a first conductive member, a second conductive member, a resistive device and a temperature sensing switch. The first conductive member includes a first electrode foil and a second electrode foil those are formed on a same plane. The resistive device is laminated between the first conductive member and the second conductive member and exhibits positive temperature coefficient or negative temperature coefficient behavior. The temperature sensing switch can switch the first electrode foil and the second electrode foil between electrically conductive status and current-restriction status, e.g., open circuit, according to temperature variation. The threshold temperature of the temperature sensing switch is lower than the trip temperature of the resistive device.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 11, 2013
    Assignee: Polytronics Technology Corp.
    Inventors: Chun Teng Tseng, David Shau Chew Wang
  • Patent number: 8451085
    Abstract: A co-fired multi-layer stack chip resistor is provided. The co-fired multi-layer stack chip resistor includes a ceramic substrate and a multi-layer stack resistance structure monomer. The ceramic substrate is formed by stacking multiple layers of the ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant. The multi-layer stack resistance structure monomer is stacked on the ceramic substrate, and includes multiple bearing membranes and multiple resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: May 28, 2013
    Assignee: Prosperity Dielectrics Co., Ltd.
    Inventors: Yung Cheng Tsai, Ching Jen Tsai, Tung Yi Chou, Hung Chun Wu
  • Patent number: 8432248
    Abstract: To provide manufacturing method for resistor that uses metal plate as resistance body, which can obtain desired accurate resistance value without trimming resistance body even if product becomes small. The method comprises; in method for manufacturing an unit resistor that has a pair of electrodes separated by insulation film, from resistor material that is provided with a metal plate consisting of resistance material, an insulation film pattern formed on the metal plate, and an electrode region formed besides area where insulation film pattern has been formed, by piercing predetermined piercing area, wherein length E of insulation film pattern is longer than width w of piercing area, wherein width L of insulation film pattern extends or narrows along direction of length E of insulation film pattern, and wherein position X of piercing area is adjusted in extent and in direction of length E of insulation film pattern.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: April 30, 2013
    Assignee: KOA Corporation
    Inventors: Hiromu Sakai, Hitoshi Amemiya, Takanori Kikuchi
  • Patent number: 8421584
    Abstract: An over-current protection device includes a conductive composite having a first crystalline fluorinated polymer, a plurality of particulates, a conductive filler, and a non-conductive filler, wherein the plurality of particulates include a second crystalline fluorinated polymer. The first crystalline fluorinated polymer has a crystalline melting temperature of between 150 and 190 degrees Celsius. The plurality of particulates including the second crystalline fluorinated polymer are disposed in the conductive composite, having a crystalline melting temperature of between 320 and 390 degrees Celsius and having a particulate diameter of from 1 to 50 micrometers. The conductive filler and the non-conductive filler are dispersed in the conductive composite.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: April 16, 2013
    Assignee: Polytronics Technology Corp.
    Inventors: Tong Cheng Tsai, Yi An Sha, David Shau Chew Wang, Fu Hua Chu
  • Patent number: 8325007
    Abstract: A metal strip resistor is provided with a resistive element disposed between a first termination and a second termination. The resistive element, first termination, and second termination form a substantially flat plate. A thermally conductive and electrically non-conductive thermal interface material such as a thermally conductive adhesive is disposed between the resistive element and first and second heat pads that are placed on top of the resistive element and adjacent to the first and second terminations, respectively.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: December 4, 2012
    Assignee: Vishay Dale Electronics, Inc.
    Inventors: Clark L. Smith, Todd L. Wyatt, Thomas L. Bertsch, Rodney J. Brune
  • Patent number: 8299888
    Abstract: There are provided a process for manufacturing a PTC device as well as a PTC device manufactured by such process wherein a resin coating for preventing the oxidation can be easily formed. The PTC device includes (A) a polymer PTC component (14) comprising: (a1) an electrically conductive filler, and (a2) a polymer material wherein the polymer PTC component is defined by opposite main surfaces and a side surface connecting outer peripheries of these main surfaces, and (B) layered metal electrodes (12, 22) placed on the main surfaces on both sides of the polymer PTC component. The PTC device has a support member (20) extending outward from a periphery of at least one of the main surfaces, and the side surface of the polymer PTC component is sealed from an ambient environment around the PTC device by a cured curable resin (24) disposed and supported on the support member.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: October 30, 2012
    Assignee: Tyco Electronics Japan G.K.
    Inventor: Hiroyuki Koyama
  • Patent number: 8193898
    Abstract: A laminated body and fabrication method thereof, which allow space saving and control of variation in internal layer resistance, are provided. When forming an internal-layer resistive element 7 in a multilayer ceramic substrate 10, the internal-layer resistive element 7 is connected to exterior electrodes (an upper surface electrode 32 and an undersurface electrode 34) via multiple via-electrodes 3a and 3b arranged in parallel, without a pad electrode adopted in the conventional laminated body. Moreover, in a multilayer ceramic substrate having multiple internal-layer resistive elements arranged in a multilayer structure, multiple internal-layer resistive elements are directly connected via multiple via-electrodes arranged in parallel.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: June 5, 2012
    Assignee: Koa Kabushiki Kaisha
    Inventor: Isao Tonouchi
  • Patent number: 8193899
    Abstract: A chip-like electric component such as a chip resistor is provided, which is easy to manufacture and in which cracks or fractures of an insulating substrate are unlikely to occur. A pair of surface electrodes 21, 23 are formed so that thicknesses of the pair of surface electrodes increase from a resistor layer 13 toward end portions 30 of an insulating substrate 29 in a direction in which the pair of surface electrodes 21, 23 are arranged. A plating reservoir S is formed between one of the surface electrodes 21, 23 and an insulating protective layer 15. When forming at least one plated layer 33, a plated metal pools in the plating reservoir S. The at least one plated layer 33 may work to reduce to some extent a height difference between a soldering electrode portion 21, 23, 27, 33 and the insulating protective layer 15.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: June 5, 2012
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Katsumi Takeuchi, Yutaka Nomura, Hiroyuki Kurokawa
  • Patent number: 8143992
    Abstract: A multilayer chip varistor is provided as one capable of suppressing production of cracks and thereby preventing a connection failure between an internal electrode and a through-hole conductor. An internal electrode 21 is so configured as to be curved toward a direction of penetration of a through hole 10 in a connection portion 28 thereof to a through-hole conductor 27. By this configuration, a region T sandwiched between a curved surface 28a of the connection portion 28 and the through-hole conductor 27 is formed in a varistor layer 9 near the connection portion 28. In this region T, a metal concentration thereof becomes higher because of diffusion of metal of the internal electrode 21 and the through-hole conductor 27 into the varistor layer 9, and therefore, after completion of firing, the region T has an intermediate contraction percentage between that of the internal electrode 21 and through-hole conductor 27 and that of the other region of the varistor layer 9.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: March 27, 2012
    Assignee: TDK Corporation
    Inventors: Hiroyuki Sato, Goro Takeuchi, Osamu Taguchi, Ryuichi Tanaka
  • Patent number: 8085551
    Abstract: The present invention is to provide an electronic component where positional accuracy for arranging members constituting a circuit element such as a resistor element and the like is mitigated and corrosion of a terminal electrode caused by sulfur in the atmosphere is reduced.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: December 27, 2011
    Assignee: KOA Corporation
    Inventors: Seiji Karasawa, Koji Fujimoto
  • Patent number: 8058966
    Abstract: A PTC thermistor provided with a conductive member having PTC characteristics and two electrodes each placed in two different locations on the conductive member. The, conductive member and at least one of the two electrodes is bonded via an adhesive which has conductivity and which at the same time deteriorates in an overheated state and irreversibly increases the electrical resistance.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: November 15, 2011
    Inventor: Hiroyuki Koyama
  • Patent number: 8031043
    Abstract: The invention relates to an arrangement comprising a shunt resistor with at least an electrically conductive first connecting leg and an electrically conductive second connecting leg. A resistance area of the shunt resistor is electrically connected to the first connecting leg and to the second connecting leg. The arrangement further comprises a circuit carrier with a first metallization and a second metallization. The first connecting leg is directly joined to the first metallization and the second connecting leg is directly joined to the second metallization. The resistance area of the shunt resistor is in thermal contact with the thermally conductive substrate by use of a thermal filler arranged between the resistance area and the substrate, and/or by directly contacting the resistance area with the substrate. The invention further relates to a method for producing an arrangement with a shunt resistor and a circuit carrier.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: October 4, 2011
    Assignee: Infineon Technologies AG
    Inventors: Martin Schultz, Peter Kanschat
  • Publication number: 20110156860
    Abstract: A metal strip resistor is provided with a resistive element disposed between a first termination and a second termination. The resistive element, first termination, and second termination form a substantially flat plate. A thermally conductive and electrically non-conductive thermal interface material such as a thermally conductive adhesive is disposed between the resistive element and first and second heat pads that are placed on top of the resistive element and adjacent to the first and second terminations, respectively.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: VISHAY DALE ELECTRONICS, INC.
    Inventors: CLARK L. SMITH, TODD L. WYATT, THOMAS L. BERTSCH, RODNEY J. BRUNE
  • Patent number: 7947933
    Abstract: A ceramic heater comprising a ceramic body, a heat generating resistor buried in the ceramic body, an electrode pad that is electrically connected to the heat generating resistor and is formed on the surface of the ceramic body and a lead member bonded onto the electrode pad.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: May 24, 2011
    Assignee: Kyocera Corporation
    Inventors: Ryuichi Nagasako, Osamu Hamada, Koji Sakamoto
  • Publication number: 20100176913
    Abstract: There is provided a method for manufacturing rectangular plate type chip resistors which provides easy and convenient control of resistance, and easy and low cost manufacture of rectangular plate type chip resistors having a reliable electrode structure, as well as a rectangular plate type chip resistor obtained by this method and having excellent properties particularly at low resistance.
    Type: Application
    Filed: May 18, 2007
    Publication date: July 15, 2010
    Inventors: Tatsuki Hirano, Osamu Matsukawa
  • Patent number: 7696677
    Abstract: A lamination-type resistance element includes a laminated sinter having internal electrodes of a first group and internal electrodes of a second group, the first internal electrode group including a plurality of internal electrodes facing each other through a ceramic resistance layer and defining a resistance unit at the portion where the plurality of internal electrodes face each other. A first end of the resistance unit is connected to a first external electrode and the second end is connected to a second external electrode. The second internal electrode group includes a plurality of pairs of internal electrodes in which the inner ends face each other through a gap on the same plane inside the laminated sinter, and a plurality of pairs of gaps in the plurality of internal electrodes are arranged at the same location when seen from one end of the lamination direction of the laminated sinter. Thereby, fine adjustment of a resistance value can be performed.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: April 13, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunori Ito, Kiyohiro Koto, Masahiko Kawase
  • Patent number: 7696856
    Abstract: A laminated chip varistor comprises a varistor body, first and second inner electrodes, a heat conductor, and first and second outer electrodes. The varistor body has first and second outer faces. The first and second inner electrodes are disposed in the varistor body so that at least portions thereof are opposing to each other. The first and second outer electrodes are formed on the first outer face, the first outer electrode being connected to the first inner electrode, and the second outer electrode being connected to the second inner electrode. The heat conductor is formed in the varistor body extending in a direction from the first outer face toward the second outer face with one end face thereof exposed on the first outer face and the other end face thereof exposed on the second outer face.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: April 13, 2010
    Assignee: TDK Corporation
    Inventors: Yo Saito, Hitoshi Tanaka, Makoto Numata, Hiroyuki Sato, Goro Takeuchi
  • Patent number: 7688177
    Abstract: A varistor comprises a varistor element body, first and second inner electrodes opposing each other, a first outer electrode connected to the first inner electrode physically and electrically, a second outer electrode connected to the second inner electrode physically and electrically, and an electrically insulating layer. The first and second inner electrodes are arranged within the varistor element body so as to have end portions exposed at two outer surfaces of the varistor element body. The first outer electrode is arranged on one of the two outer surfaces so as to cover a portion of the end portion of the first inner electrode exposed at the one outer surface. The second outer electrode is arranged on the one outer surface so as to cover a portion of the end portion of the second inner electrode exposed at the one outer surface.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: March 30, 2010
    Assignee: TDK Corporation
    Inventors: Yo Saito, Hiroyuki Sato, Hitoshi Tanaka, Makoto Numata
  • Patent number: 7679485
    Abstract: A multilayer positive temperature coefficient thermistor that has semiconductor ceramic layers containing a BaTiO3-based ceramic material as a primary component, and at least one element selected from the group consisting of Eu, Gd, Tb, Dy, Y, Ho, Er, and Tm as a semiconductor dopant in the range of 0.1 to 0.5 molar parts with respect to 100 molar parts of Ti. The ratio of the Ba site to the Ti site is in the range of 0.998 to 1.006. Accordingly, even when the semiconductor ceramic layers have a low actual-measured sintered density in the range of 65% to 90% of a theoretical sintered density, a multilayer positive temperature coefficient thermistor having a sufficiently high rate of resistance change and a high rising coefficient of resistance at the Curie temperature or more can be realized.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: March 16, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kishimoto, Kenjirou Mihara, Hideaki Niimi
  • Patent number: 7667568
    Abstract: A chip resistor (A1) includes a chip-like resistor element (1), two electrodes (31) spaced from each other on the bottom surface (1a) of the resistor element, and an insulation film (21) between the two electrodes. Each electrode (31) has an overlapping portion (31c) which overlaps the insulation film (21) as viewed in the vertical direction.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: February 23, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Masanori Tanimura, Torayuki Tsukada, Kousaku Tanaka
  • Patent number: 7649437
    Abstract: A multilayer positive temperature coefficient thermistor that has a BaTiO3-based ceramic material contained as a primary component in semiconductor ceramic layers, the ratio of the Ba site to the Ti site is in the range of 0.998 to 1.006, and at least one element selected from the group consisting of La, Ce, Pr, Nd, and Pm is contained as a semiconductor dopant. In this multilayer positive temperature coefficient thermistor, a thickness d of internal electrodes layer and a thickness D of the semiconductor ceramic layers satisfy d?0.6 ?m and d/D<0.2. Accordingly, even when the semiconductor ceramic layers have a low sintered density such that an actual-measured sintered density is 65% to 90% of a theoretical sintered density, a multilayer positive temperature coefficient thermistor having a low rate of temporal change in room-temperature resistance can be obtained without performing any complicated processes, such as a heat treatment. When the content of the semiconductor dopant is 0.1 to 0.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: January 19, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenjirou Mihara, Atsushi Kishimoto, Hideaki Niimi
  • Patent number: 7629872
    Abstract: A chip-type component 11 includes an insulating chip substrate 12 whose upper surface is provided with a resistor element 13 and a cover coat 14 covering the resister film. At the opposite ends of the substrate, terminal electrode films 15, 16 are formed for the resistor element in a manner such that they extend onto the lower surface 12a of the insulating substrate. The lower surface 12a of the substrate is provided with an insulating projection 18 between the terminal electrode films, where the projection includes a peak portion 18a positioned at or near the center of the insulating substrate in a longitudinal direction along which the terminal electrode films are spaced from each other. This prevents the insulating substrate from breaking when the chip-type component 11 is vacuum-sucked by a collet nozzle 19 to be supplied to a printed circuit board 17.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: December 8, 2009
    Assignee: Rohm Co., Ltd.
    Inventor: Takahiro Kuriyama
  • Patent number: 7528350
    Abstract: The present invention provides a novel method for electrical connection between a polymer PTC device and a metal lead element to thereby prevent the problems of the connection by caulking or soldering. For this purpose, the present invention provides a process for producing a connection structure by laser welding, said connection structure having (A) a PTC device (10) including (i) a laminar polymer PTC element (12) and (ii) a metal foil electrode (14) disposed on a main surface of the laminar polymer PTC element (12), and (B) a metal lead element (20) electrically connected to the metal foil electrode. The metal foil electrode (14) has at least two metal layers, one of which, the X-th layer, has laser beam absorption a % that is the lowest among the metal layers of the metal foil electrode (14). The X-th layer is present between a first metal layer (18) of the metal foil electrode and the laminar polymer PTC element (12).
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: May 5, 2009
    Assignee: Tyco Electronics Raychem KK
    Inventors: Atsushi Nakagawa, Arata Tanaka, Mikio Iimura
  • Patent number: 7446286
    Abstract: A heater strip for use as a heating element in an electric heater is made up of a profiled strip made of a flat metallic material forming a resistor section and of mounting elements extending over one common longitudinal side and they are manufactured as one piece with the resistor section for mounting the heater strip to a support. The strip has a zigzag-shaped structure. The mounting elements are provided only on the flat leg sections of the zigzag-shaped heater strip.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: November 4, 2008
    Assignee: Electrovac AG
    Inventors: Josef Reithofer, Christian Auradnik
  • Patent number: 7352272
    Abstract: An over-current protection device comprises two metal foils and a PTC material layer laminated between the two metal foils. The PTC material layer essentially comprises a polymer matrix and a conductive filler. The polymer matrix at least comprises a first crystalline polymer, e.g., LDPE, and a second crystalline polymer, e.g., PVDF, in which the melting temperature of the second crystalline polymer subtracting the melting temperature of the first crystalline polymer is equal to or more than 50° C. The conductive filler is selected from metallic grain of a volumetric resistivity less than 500 ??-cm, and is distributed in the polymer matrix. The initial volumetric resistivity of the PTC material layer is less than 0.1?-cm, and the trip temperature of the PTC material layer at which the resistance thereof increases to 1000 times the initial resistance subtracting the melting temperature of the first crystalline polymer is less than 15° C.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: April 1, 2008
    Assignee: Polytronics Technology Corporation
    Inventors: David Shau Chew Wang, Jyh Ming Yu, Kuo Chang Lo
  • Patent number: 7326889
    Abstract: A method of manufacturing a PTC element comprising a pair of lead terminals bonded together by thermocompression with a matrix held therebetween comprises a matrix preparing step of preparing a matrix constructed by dispersing a conductive filler into a crystalline polymer; a terminal preparing step of preparing a pair of lead terminals holding the matrix therebetween, a surface of each lead terminal facing the matrix being formed with a plurality of anchor protrusions separated from each other; a flattening step of flattening the anchor protrusions formed in respective nonoverlapping areas in the pair of lead terminals kept from overlapping the matrix; and a thermocompression bonding step of holding the matrix between respective overlapping areas in the pair of lead terminals overlapping the matrix, and securing the pair of lead terminals and the matrix together by thermocompression bonding.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: February 5, 2008
    Assignee: TDK Corporation
    Inventors: Hisanao Tosaka, Tokuhiko Handa, Hirokazu Satoh, Tsutomu Hatakeyama
  • Patent number: 7286038
    Abstract: An over-current protection device comprises two metal foils and a positive temperature coefficient (PTC) material layer laminated between the two metal foils. The PTC material layer includes: (1) a polymer substrate, being 35-60% by volume of the PTC material layer and including a fluorine-containing crystalline polymer with a melting point higher than 150° C., e.g., polyvinylidine fluoride (PVDF); and (2) a conductive ceramic filler (e.g., titanium carbide) distributed in the polymer substrate. The conductive ceramic filler is 40-65% by volume of the PTC material layer, and has a volume resistivity less than 500 ??-cm. The volume resistivity of the PTC material layer is less than 0.1 ?-cm, and the ratio of the hold current of the PTC material layer at 25° C. to the area of the PTC material layer is between 0.05 and 0.2 A/mm2.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: October 23, 2007
    Assignee: Polytronics Technology Corporation
    Inventors: David Shau Chew Wang, Jyh Ming Yu
  • Patent number: 7277006
    Abstract: Chip resistor includes the rectangular first substrate made of ceramics and having surfaces, the rectangular second substrate made of ceramics and having surfaces, and a joint layer interposed between the surfaces, and electrodes are formed on two opposing sides of the substrate and resistor is formed between the electrodes. Further, electrodes are formed on two opposing sides of the substrate and resistor is formed between the electrodes.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: October 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideo Yokoo
  • Patent number: 7215235
    Abstract: A conductive substrate with a resistance layer comprising a substantially flat high conductivity substrate roughening treated on its surface by a resistance component and provided with a resistance layer by the resistance component so as to enable the interface between the high conductivity substrate and resistance component layer to be substantially flattened, enable acquisition of a thin film resistance layer with a stable resistance after dissolving away the high conductivity substrate, and able to maintain the peel strength with the insulating support, and a resistance board using the same.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: May 8, 2007
    Assignee: Furukawa Circuit Foil Co., Ltd
    Inventors: Akira Matsuda, Yuuji Suzuki, Hideo Otsuka, Yuuki Kikuchi, Sadao Matsumoto
  • Patent number: 7173512
    Abstract: A thermistor of which resistance is changed depending on temperature and a secondary battery to which the thermistor is attached are disclosed. The thermistor is attached to an object via a lead which is made of different kinds of materials. The lead is configured so that a part of the lead to be united to the thermistor electrode is mainly made of the same material as the electrode and a part of the lead to be united to the object is mainly made of the same material as the surface of the object. Thus, the thermistor may be simply attached to the object only using the ultrasonic welding, thereby remarkably reducing junction inferiorities.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: February 6, 2007
    Assignee: LG Cable, Ltd.
    Inventors: Chang-Mo Ko, Su-An Choi, Jun-Ku Han, An-Na Lee, Jong-Hwan Lee, Ju-Dam Kim, Jong-Ho Lee, Jong-Seo Yoon
  • Patent number: 7161463
    Abstract: The organic NTC composition according to the present invention is a mixture of a conjugated organic semiconductor polymer and a thermoplastic resin or thermosetting resin. For example, the mixed amount of the thermoplastic resin or thermosetting resin is preferably equal to or lower than two times the amount of the conjugated organic semiconductor polymer, and a conjugated organic semiconductor polymer selected from solvent-soluble polyaniline, polythiophene, polypyrrole and their derivatives is preferably used. This organic NTC composition makes it possible to provide an organic NTC device without using any expensive material and facilitates easy production at low temperatures.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: January 9, 2007
    Assignee: Shin-Etsu Polymer Co., Ltd.
    Inventors: Toshiyuki Kawaguchi, Masayuki Takahashi
  • Patent number: 7102483
    Abstract: An over-current protector comprised of multiple over-current protection devices each at various switching temperature and provided with positive temperature coefficient; all devices being stacked and segregated with an reinforced insulation layer and connected in parallel through a conducting mechanism each respectively provided at where in relation to both ends of the device; both conducting mechanisms constituting the terminal electrodes of the over-current protector as a whole for reducing initial resistance, increasing peak resistance, and in turn upgrading voltage withstanding performance.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: September 5, 2006
    Assignee: Protectronics Technology Corporation
    Inventors: Ren-Haur Hwang, Chien-Shan Huang, Rei-Yian Chen, Jui-Kuang Chang
  • Patent number: 7098768
    Abstract: A chip resistor includes: an insulating chip substrate 11 having an upper surface formed with a resistive film 12 and a pair of left and right upper electrodes 13 at two ends thereof; a cover coat 14 covering the resistive film; auxiliary upper electrodes 15 formed on upper surfaces of the upper electrodes 13 to overlap the cover coat 14; a left and a right side electrodes 16 formed on a left and a right end surfaces 11a of the insulating substrate 11; and metal plate layers formed on surfaces of the auxiliary upper electrodes and side electrodes. The cover coat 14 is formed with an uppermost over coat 19 covering a region where the auxiliary upper electrodes 15 overlap the cover coat 14, whereby the upper electrodes 13 and the auxiliary upper electrodes 15 are protected from migration caused by sulfur gases.
    Type: Grant
    Filed: November 28, 2002
    Date of Patent: August 29, 2006
    Assignee: Rohm Co., Ltd.
    Inventor: Masato Doi
  • Patent number: 7075408
    Abstract: A positive temperature coefficient thermistor has a non-heating portion which is not heated when a voltage is applied between first and second internal electrodes. The non-heating portion is provided in the approximate center of the positive temperature coefficient thermistor and is arranged to extend along a direction that is substantially perpendicular to a lamination direction of the positive temperature coefficient thermistor. The non-heating portion is arranged at least in the approximate center in the lamination direction of the portion of the laminate where the first and the second internal electrodes are arranged. Thus, a hot spot is reliably prevented from occurring inside the laminate when voltage is applied. As a result, the withstand voltage property is greatly improved. The non-heating portion may include a cavity provided in at least one thermistor layer or an opening or cut portion provided in the internal electrode.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: July 11, 2006
    Assignee: Murata Manufacturing Co, Ltd.
    Inventors: Kenjiro Mihara, Hideaki Niimi
  • Patent number: 7053749
    Abstract: A metal plate resistor includes a resistive body comprising a metal plate, and at least a pair of electrodes joined respectively to opposite ends of the resistive body, the electrodes being made of a highly conductive metal conductor. The resistive body has a main section positioned between the electrodes and a pair of electrode sections progressively wider than the main section in directions away from the main section. The electrodes are disposed respectively beneath the electrode sections and identical in shape to the electrode sections.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: May 30, 2006
    Assignee: KOA Corporation
    Inventors: Kazuhiro Ishida, Satoshi Chiku
  • Patent number: 7053748
    Abstract: A composite circuit protection device includes a laminar insulating member and first and second laminar circuit protection devices.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: May 30, 2006
    Assignee: Tyco Electronics Corporation
    Inventors: Justin Chiang, Shou-Mean Fang, William C. Beadling
  • Patent number: 7042331
    Abstract: A thick-film resistor component may include a thick film component formed between a thick-film resistor and an electrically conductive sheet, wherein a portion of the sheet is selectively removed to form resistor contacts while exposing a portion of the thick-film component. Electrical terminals to a thick-film resistor may be sized to reduce stress and/or be selectively positioned relative to the resistor to define a desired resistor value. A thick-film resistor may include one or more resistor segments configured to be selectively open-circuited to incrementally adjust the value of the resistor.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 9, 2006
    Assignee: Delphi Technologies, Inc.
    Inventors: Jiming Zhou, Dwadasi H. Sarma, Carl W. Berlin, John D Myers, M. Ray Fairchild
  • Patent number: 7026583
    Abstract: A surface mountable PTC device includes a PTC layer, first and second electrodes formed on the PTC layer, first and second insulating layers formed respectively on the first and second electrodes, and first and second terminals connected respectively and electrically to the first and second electrodes. Each of the first and second electrodes is formed with a hole. Each of the first and second insulating layers fills the electrode hole in the respective one of the first and second electrodes and is formed with an insulating hole surrounded by the electrode hole. Each of the first and second terminals extends through the insulating hole in the respective one of the first and second insulating layers.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: April 11, 2006
    Inventors: Ching-Fang Tu, Fu-Sen Liao, Hsueh-Huan Lo
  • Patent number: 6987440
    Abstract: An electrical device in which an element composed of a conductive polymer composition is positioned in contact with the first surface of a metal electrode, the first surface having a center line average roughness Ra and a reflection density RD, the product Ra times RD being 0.5 to 1.6 ?m. The conductive polymer composition preferably exhibits PTC behavior. In a second embodiment an electrical device has an element composed of a conductive polymer composition in contact with the first surface of a metal electrode produced by providing a base metal foil having an Ra of at most 0.45 ?m and depositing material onto the base metal foil to form a first surface having a product of Ra times RD of at least 0.14 ?m. Other embodiments include electrical devices with metal electrodes made by pulse plating processes, and metal electrodes made by electrodeposition under diffusion-limited conditions. The electrical devices may be circuit protection devices and have improved electrical and physical properties.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: January 17, 2006
    Assignee: Tyco Electronics Corporation
    Inventors: Paul N. Becker, Orion Jankowski, Cecilia A. Walsh
  • Patent number: 6935554
    Abstract: There is provided a method for producing a metal/ceramic bonding article, the method including the steps of: arranging a metal plate 12 of an overall-rate solid solution type alloy on a ceramic substrate 10; and heating the metal plate 12 and the ceramic substrate 10 in a non-oxidizing atmosphere at a temperature of lower than a melting point of the alloy to bond the metal plate 12 directly to the ceramic substrate 10. According to this method, it is possible to easily bond an alloy plate directly to a ceramic substrate, and it is possible to inexpensively provide an electronic member for resistance without causing the alloy plate to be deteriorated.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: August 30, 2005
    Assignee: Dowa Mining, Co. Ltd.
    Inventors: Masami Kimura, Susumu Shimada
  • Patent number: 6876291
    Abstract: The present invention relates to an electrical resistor (1), in particular for measuring alternating currents of high frequency, comprising connectors (2, 3) for feeding the current to be measured and connectors (4, 5) for tapping the voltage to be measured and having a layered structure including at least one resistive layer (10), a return conducting layer (11) and any possibly provided insulating layers (7, 12, 21, 22, 24). To obtain a measuring resistance having a particularly good frequency response, a high long-term stability and an efficient cooling and which, moreover, is inexpensive to produce, it is provided for the resistive layer (10) together with the return conducting layer (11) and the possible insulating layers (7, 12, 21, 22, 24) to be part of a multilayered printed circuit board and to comprise a plurality of conductive tracks (14) extending from a central region of the resistive layer (10) towards outside.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: April 5, 2005
    Assignee: Lem Norma GmbH
    Inventor: Wolfram Teppan
  • Patent number: 6873244
    Abstract: The present invention discloses a surface mountable laminated thermistor device which utilizes current-used double sided metal foil clad substrate as a base material and a PTC conductive composite that complies with circuit connection design combinations among electrodes to obtain a surface mountable laminated thermistor device with a parallel manner, and vastly simplify the fabrication process of the surface mountable laminated thermistor device.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: March 29, 2005
    Assignee: Protectronics Technology Corporation
    Inventors: Chien-Shan Huang, Ren-Haur Hwang, Chih-Yi Chang
  • Patent number: 6856234
    Abstract: A chip resistor includes an insulating substrate 2 in the form of a chip having an upper surface and an opposite pair of side surfaces, a resistor film 4 formed on the upper surface of the insulating substrate 2, a pair of upper electrodes 5 formed on the upper surface of the insulating substrate 2 to flank the resistor film 4 in electrical connection thereto, a cover coat 6 covering the resistor film 4, an auxiliary upper electrode 7 formed on each of the upper electrodes 5 and including a first portion 7a adjoining the relevant side surface of the insulating substrate 2 and a second portion 7b overlapping the cover coat 6, and a side electrode 8 formed on each of the side surfaces of the insulating substrate 2 and electrically connected to at least the upper electrode 5 and the auxiliary upper electrode 7.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: February 15, 2005
    Assignee: Rohm Co., Ltd.
    Inventors: Takahiro Kuriyama, Masato Doi
  • Patent number: RE39660
    Abstract: An electrical resistor has a surface mounted four terminal current sensor of a very low resistance value and capable of handling short pulses of high power. It comprises a flat metal late, 1 to 50 mils thick, of an alloy of high electrical resistivity, to which are welded, on two opposite sides, two flat metal plates of very high electrical conductivity which serve as terminations for electrical interconnection. A slot is cut, from the outside edge toward the center, into each of the two termination plates which divides them into a wide pad for connection of current carrying wires and a narrow one for voltage sensing. The depth of the slots is optimized to get the best stability of resistance readings with changing ambient temperature and under influence of the self-heating effect.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: May 29, 2007
    Assignee: Vishay Dale Electronics, Inc.
    Inventors: Joseph Szwarc, Joel J. Smejkal
  • Patent number: RE44224
    Abstract: A surface-mounted over-current protection device with positive temperature coefficient (PTC) behavior is disclosed. The surface-mounted over-current protection device comprises a first metal foil, a second metal foil corresponding to the first metal foil, a PTC material layer stacked between the first metal foil and the second metal foil, a first metal electrode, a first metal conductor electrically connecting the first metal foil to the first metal electrode, a second metal electrode corresponding to the first metal electrode, a second metal conductor electrically connecting the second metal foil to the second metal electrode, and at least one insulated layer to electrically insulate the first metal electrode from the second metal electrode. The surface-mounted over-current protection device, at 25° C., indicates that a hold current thereof divided by the product of a covered area thereof and the number of the conductive composite module is at least 0.16 A/mm2.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: May 21, 2013
    Assignee: Polytronics Technology Corp.
    Inventors: Shau Chew Wang, Fu Hua Chu