Serial To Parallel Patents (Class 341/100)
  • Patent number: 8169348
    Abstract: In a parallel-serial converter circuit of a multistage configuration, there is formed a clock propagation path so that when multistage connected data converters are operated according to the timing of a clock signal, a reference clock signal or a clock signal in which the reference clock signal has been frequency-converted, is given sequentially to the data converter of the first stage up to the data converter of the final stage. As a result, even in a case where variations occur in power supply voltage, timing deviation of data signals and clock signals input to the data converters of the second and subsequent stages can be suppressed, and parallel-serial conversion of high-speed data signals can be reliably executed.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: May 1, 2012
    Assignee: Fujitsu Limited
    Inventor: Yukito Tsunoda
  • Patent number: 8169347
    Abstract: A parallel data output device includes a first latch circuit that latches and outputs one of at least two data signals input in parallel in accordance with a first clock signal; a second latch circuit that latches and outputs another of the at least two data signals in accordance with a second clock signal; and a phase set circuit that shifts at least one of a phase of the first clock signal and a phase of the second clock signal based on the phase of the first clock signal and the phase of the second clock signal.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: May 1, 2012
    Assignee: Fujitsu Limited
    Inventor: Yukito Tsunoda
  • Patent number: 8166217
    Abstract: A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Theodore C. White, William W. Dennin, Angel G. Perozo
  • Patent number: 8166219
    Abstract: Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: April 24, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Sung Lee, Sung Nam Kim, Seong Woon Kim
  • Publication number: 20120075127
    Abstract: A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line.
    Type: Application
    Filed: December 6, 2011
    Publication date: March 29, 2012
    Applicant: Fujitsu Limited
    Inventor: Seishi Okada
  • Patent number: 8144038
    Abstract: A signal processing apparatus is provided, which generates a data signal having a signal waveform corresponding to a first bit value of a signal waveform transitioning from a high level to a low level or a signal waveform transitioning from a low level to a high level, a pre-transition signal level corresponding to a second bit value of one of a plurality of high levels and a plurality of low levels, and a post-transition signal level corresponding to a third bit value of the other.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: March 27, 2012
    Assignee: Sony Corporation
    Inventor: Takehiro Sugita
  • Patent number: 8144039
    Abstract: In one embodiment, a semiconductor integrated device includes a plurality of semiconductor chips each having a first internal circuit and a second internal circuit and being stacked while displaced from each other. The first internal circuit processes a data signal in accordance with a predetermined process. The second internal circuit receives a request signal from a transmission source and determines whether the request signal is a request to itself or not. When the request signal is the request to the second internal circuit itself, the second internal circuit receives a data signal from a transmission source and outputs the data signal to the first internal circuit. When the request signal is not the request to the second internal circuit itself, the second internal circuit transfers the request signal to a transfer destination, receives the data signal from the transmission source and transfers the data signal to the transfer destination.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: March 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Morimitsu
  • Publication number: 20120038497
    Abstract: A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.
    Type: Application
    Filed: August 12, 2010
    Publication date: February 16, 2012
    Applicant: MEDIATEK INC.
    Inventors: Wei-Cheng Ku, Chung-Hung Tsai, Chun-Nan Li, Yi-Hsi Chen
  • Patent number: 8106798
    Abstract: A parallel to serial conversion circuit makes output data normally swing even in a high-speed operation. The parallel to serial conversion circuit includes a main selection block configured to drive an output node sequentially in response to data on a first line and data on a second line, and a subsequent selection block configured to drive the output node sequentially in response to data on a subsequent first line and data on a subsequent second line, wherein the output node is driven by inverted data of the data on the subsequent first line and inverted data of the data on the subsequent second line.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 31, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Kyu Choi
  • Patent number: 8107575
    Abstract: A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: January 31, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Boomer, Oscar Freitas, Steven Macaluso
  • Patent number: 8102288
    Abstract: A data transmitting circuit that converts parallel data into serial data to output the serial data, includes a first data input port that receives first parallel data at a first data rate based on a reference input clock; a second data input port that receives second parallel data at a second data rate lower than the reference input clock, a data expansion unit that generates expanded data by expanding a bit number of the second parallel data to a bit number of the first parallel data, a serial data generation unit that performs a process for generating first serial data by performing a serial conversion on the first parallel data based on the reference input clock and a process for generating second serial data by performing a serial conversion on the expanded data, and a data output port that outputs the first serial data or the second serial data.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: January 24, 2012
    Assignee: Fujitsu Limited
    Inventor: Yoichi Koyanagi
  • Patent number: 8094047
    Abstract: Some embodiments include apparatus and methods having an output line, clock nodes to receive clock signals, the clock signals being out of phase with each other, and selector circuits to receive data in parallel. In at least one embodiment, the selector circuits are responsive to the clock signals to transfer the data serially to the output line. Such apparatus and methods can also include a control unit to influence a portion of a signal that represents at least a portion of the data at the output line. Additional apparatus and methods are described.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: January 10, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Greg King
  • Patent number: 8094116
    Abstract: The present invention relates to a serial-parallel conversion circuit of a display device. First latch circuits for sampling and latching a serial signal in accordance with sampling pulses outputted from a shift register (31) are provided in association with stages of the shift register (31). In addition, second latch circuits for latching signals outputted from the first latch circuits are provided in association with portions of the stages of the shift register (31). In this case, of all the stages of the shift register (31), the number of stages associated with the second latch circuits is less than the total number of stages of the shift register by two or more.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: January 10, 2012
    Assignee: Sharp Kabsuhiki Kaisha
    Inventors: Tamotsu Sakai, Tomoyuki Nagai, Kazuhiro Maeda, Shuji Nishi, Masakazu Satoh
  • Patent number: 8089381
    Abstract: An all-optical combined serial-to-parallel and digital-to-analog convertor using standard WDM technology is realized. The system is based on bit interleaving and cross-gain modulation (XGM) in a semiconductor optical amplifier (SOA). The optical system can operate on multiple-bit digital words at a very high bit rate. The analog output forms series of pulses with the amplitude of each pulse taking one of the eight discrete values. A low pass filter may be used to turn this bit stream into a continuous waveform, and thus arbitrary waveforms are generated. Unlike many current digital-to-analog converter designs, which double in size with each additional bit, the design presented here allows a linear growth in components, thus making higher bit systems practical.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: January 3, 2012
    Inventors: Azad Siahmakoun, Sergio Carlos Granieri, Michael Ryan Gehl
  • Patent number: 8085066
    Abstract: A microprocessor control unit (MCU) is mounted on a printed circuit board. The MCU includes first and second clocked serial interface (CSI) circuits. The first CSI circuit is configured to serially transmit a first xCP packet to a first encoder circuit, which in turn is configured to generate an encoded first xCP packet as a function of the first xCP packet and a first clock signal. A first low voltage differential signal (LVDS) circuit is coupled to the first encoder circuit and configured to serially receive the encoded first xCP packet therefrom. The first LVDS circuit is configured to generate a first differential signal as a function of the encoded first xCP packet.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics America Inc.
    Inventors: Jeremy W. Brodt, Amit Choudhury, Ben F. McCormick, II
  • Patent number: 8085173
    Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: December 27, 2011
    Assignee: Broadcom Corporation
    Inventor: Wael William Diab
  • Patent number: 8081094
    Abstract: A signal transmission system in which a serializer IC connected to first parallel signal wirings and a deserializer IC connected to second parallel signal wirings are connected by a transmission line. Among input terminals of the serializer IC, redundant input terminals which are not connected to the first parallel signal wirings are connected to one wiring obtained by branching off the first parallel signal wirings. When parallel signals are converted into a serial signal, their bit data is arranged into the serial signal which is temporally continuous. Thus, the number of transition times of the serial signal is reduced and radiation noises can be suppressed.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: December 20, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinichi Nishimura
  • Patent number: 8060654
    Abstract: A data communication network may include two or more master clocks, and a synchronization system connected to the master clocks. The synchronization system may determine a time-base for the master clocks. The synchronization system may control the master clocks according to the determined time-base. The data communication network may include one or more slave clocks. The slave clocks may be controlled by a slave clock time-base controller based on time information of a single selected master clock selected from the master clocks.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 15, 2011
    Assignee: Freescale Semiconductor, Inc
    Inventors: Florian Bogenberger, Mathias Rausch
  • Patent number: 8049649
    Abstract: A parallel-to-serial conversion circuit for converting pieces of parallel data into serial data, and a parallel-to-serial converting method thereof include: a shifter configured to sequentially shift an initiation signal to generate a plurality of transfer activation signals; a valid duration generator configured to define valid durations of the plurality of pieces of parallel data based on a clock and the plurality of transfer activation signals; and an output unit configured to receive the plurality of pieces of parallel data whose valid duration has been defined and to drive an output in response to a piece of data from among the received parallel data whose valid duration has begun.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jinyeong Moon
  • Patent number: 8044833
    Abstract: According to one embodiment, a high speed serializer for multiplexing 2N data inputs, N being a positive integer, comprises one less than 2N multiplexing cells arranged in N stages. The stages are numbered 1 through N, and the output of the Nth stage is a serial transmission and the inputs of the 1st stage are the 2N data inputs. Each stage comprises half as many multiplexing cells as the preceding stage. Additionally, each multiplexing cell comprises a multiplexer that comprises a pair of inputs and an output. 2N-2 of the multiplexing cells in the first stage further comprise a latch, and the output of the latch is coupled to an input of the multiplexer.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: October 25, 2011
    Assignee: Raytheon Company
    Inventor: Jeong-Gyun Shin
  • Patent number: 8028107
    Abstract: A serial to parallel I/O circuit apparatus includes M sequential logic circuits and each of them includes a first D-type flip-flop for receiving one bit of input data, and the output of each the first D-type flip-flop connects to the input of a first D-type flip-flop of a next stage. A second D-type flip-flop receives one bit of enable control signal, and the output of each of the second D-type flip-flops connects to the input of a second D-type flip-flop of a next stage. A multiplexer contains two input terminals and an enable control signal receiving terminal, wherein one input terminal is used to receive the input data received by the first D-type flip-flop, and the enable control signal receiving terminal receives the enable control signal received by the second D-type flip-flop. A D-type latch outputs the data, and the output data is fed back to another input terminal of the multiplexer so as to be selected as a data output when a next set of data are input.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: September 27, 2011
    Assignee: VIA Technologies, Inc.
    Inventor: Cheng-Tao Lee
  • Patent number: 8013764
    Abstract: In one embodiment, a method and apparatus for shifting the bits of a data word are disclosed. For example, a deserializer according to one embodiment includes an input register bank for capturing serial data comprising n bits, an intermediate register bank, and a strobe mux coupled to an input of the intermediate register bank. An input of the intermediate register bank is coupled to an output of the input register bank. The strobe mux comprises a single multiplexer configured to select a bitslip strobe signal that controls an order in which the n bits of the serial data are captured in the intermediate register bank.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: September 6, 2011
    Assignee: Xilinx, Inc.
    Inventor: John G. O'Dwyer
  • Patent number: 7994950
    Abstract: A physical layer (PHY) device including a first encoder, a second encoder, and a selector. The first encoder is configured to receive a first data stream at a first data rate, encode the first data stream using a first type of encoding, and output a first encoded data via a plurality of outputs. The second encoder is configured to receive a second data stream at a second data rate, encode the second data stream using a second type of encoding, and output a second encoded data via an output. The selector includes a first set of inputs and a second set of inputs. The first set of inputs is configured to receive the plurality of outputs of the first encoder, and each input of the second set of inputs is configured to receive the output of the second encoder.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: August 9, 2011
    Assignee: Marvell International Ltd.
    Inventors: William Lo, Calvin Fang
  • Patent number: 7990294
    Abstract: A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: August 2, 2011
    Assignee: Fujitsu Limited
    Inventors: Yoshiyasu Doi, Hirotaka Tamura
  • Patent number: 7990296
    Abstract: Techniques are provided to serialize and delay parallel input data signals and are particularly useful for low power applications. In one example, a device includes a plurality of data input ports adapted to receive N parallel single-ended input data signals, and a clock input port adapted to receive a clock signal substantially synchronized with the parallel single-ended input data signals. The device also includes a cell adapted to serialize the parallel single-ended input data signals to provide N/2 first serial differential output data signals in response to the clock signal, delay the parallel single-ended input data signals, and serialize the delayed parallel single-ended input data signals to provide N/2 delayed second serial differential output data signals in response to the clock signal. The delayed second serial differential output data signals are delayed relative to the first serial differential output data signals. The device also includes a plurality of output ports.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 2, 2011
    Assignee: SMSC Holdings S.a.r.l.
    Inventors: Heng Wang, Hongming An, CongQing Xiong
  • Patent number: 7990293
    Abstract: A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first flip-flop group is controlled by a first clock signal. The second flip-flop group includes a plurality of flip-flops, where the second flip-flop group is controlled by a second clock signal, and the flip-flops of the second flip-flop group are respectively connected to output nodes of the flip-flops of the first flip-flop group. The programmable frequency divider is coupled to each of the flip-flops of the second flip-flop group, and is utilized for receiving a control signal and generating the second clock signal by performing a frequency-dividing operation according to a frequency-dividing factor set by the control signal.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: August 2, 2011
    Assignee: MediaTek Inc.
    Inventor: Yan-Bin Luo
  • Publication number: 20110181556
    Abstract: The present invention relates to a serial-parallel conversion circuit of a display device. First latch circuits for sampling and latching a serial signal in accordance with sampling pulses outputted from a shift register (31) are provided in association with stages of the shift register (31). In addition, second latch circuits for latching signals outputted from the first latch circuits are provided in association with portions of the stages of the shift register (31). In this case, of all the stages of the shift register (31), the number of stages associated with the second latch circuits is less than the total number of stages of the shift register by two or more.
    Type: Application
    Filed: September 9, 2005
    Publication date: July 28, 2011
    Inventors: Tamotsu Sakai, Tomoyuki Nagai, Kazuhiro Maeda, Shuji Nishi, Masakazu Satoh
  • Patent number: 7982640
    Abstract: A digital signal transmitting apparatus includes an encoder which converts parallel input signals of multiple channels into serial data in a manner synchronized with a first clock signal, and a decoder which converts the serial data into parallel output signals of the multiple channels in a manner synchronized with a second clock signal operating in a manner asynchronous with the first clock signal. The serial data has a different period and a different duty factor corresponding to each combination of the logical values of the parallel input signals of the multiple channels.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: July 19, 2011
    Assignee: TDK Corporation
    Inventors: Reiji Okuno, Takakazu Imai, Takeo Gokita
  • Patent number: 7978108
    Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of ā€œLā€ in synchronous with the output control clock.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Isao Tottori, Masaru Hagiwara
  • Publication number: 20110156937
    Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.
    Type: Application
    Filed: March 10, 2011
    Publication date: June 30, 2011
    Applicant: Broadcom Corporation
    Inventor: Wael William Diab
  • Publication number: 20110156936
    Abstract: An optimized Mobile Industry Processor Interface (MIPI) includes a transmitter physical (PHY) layer configured to convert input data into serial data and transmit the serial data in synchronization with a high-speed clock, a receiver PHY layer configured to convert the serial data into 8-bit parallel data in synchronization with the clock received from the transmitter, a bit merge block configured to merge the parallel data received from the receiver PHY layer so as to form 32-bit data using multiple lanes and to transmit the 32-bit data to a receiver protocol layer, the receiver protocol layer being configured to decode and recognize the data received from the bit merge block.
    Type: Application
    Filed: September 30, 2010
    Publication date: June 30, 2011
    Inventors: Bo-Sung Kim, Seung Nam Park, Jae Il Cheon
  • Patent number: 7952500
    Abstract: A method of encoding data structures using compressed object encodings during serialization. A compressed representation of the data is generated directly while encoding. Serialization means converting a data structure to a string of bytes for external storage or communication.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: May 31, 2011
    Assignee: Tatu Ylonen Oy
    Inventor: Tatu J Ylonen
  • Patent number: 7948407
    Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: May 24, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Takemi Yonezawa, Kenichi Oe
  • Publication number: 20110109486
    Abstract: A pseudo-orthogonal code generator is provided. The pseudo-orthogonal code generator simplifies overall configuration and provides a more efficient operating speed by implementing a pseudo-orthogonal code generator using combined circuits instead of using a read only memory (ROM) circuit. The pseudo-orthogonal code generator reduces its overall size by reducing gate area.
    Type: Application
    Filed: December 24, 2009
    Publication date: May 12, 2011
    Inventors: Yongseong KIM, Kyeunghak Seo, Jinwoong Cho, Hyunseok Lee, Taigil Kwon, Yongseok Lim
  • Publication number: 20110090100
    Abstract: Passive signal combiners are employed to transform at least one signal from one domain to another. In some aspects the transformation comprises an NFL an IFFT, a DFT, or an IDFT. In some implementations the passive signal combiners comprise a set of planar waveguides (e.g., which may be referred to as beamformers or Rotman lenses) that have multiple inputs and outputs and are configured to provide orthogonal output signals. In some implementations an electrical signal (e.g., received via an antenna element) is coupled to passive beamformers that transform the electrical signal from one domain to another domain. Here, a transformation of the electrical signal by a given passive beamformer may have a first resolution, and outputs from the passive beamformers may correspond to orthogonal groups. A combiner circuit may be used to combine the outputs from the passive beamformers and produce a combined output having a second resolution and an associated error.
    Type: Application
    Filed: December 5, 2008
    Publication date: April 21, 2011
    Inventors: Mahdieh B. Shemirani, Farshid Aryanfar
  • Publication number: 20110090099
    Abstract: The present invention is to provide a method for encoding and decoding serial signals formed by a plurality of color lights, which is applied to an encoding/decoding system comprising an encoding device and a decoding device, and comprises steps of generating a driving signal corresponding to at least one first serial code set by the encoding device, so as to drive a multi-color LED to generate a plurality of color lights having different wavelengths and interval time of flash intervals; and receiving the color lights by the decoding device, decoding the color lights according to a decoding procedure of the decoding device for obtaining the first serial code set, and sending an actuation signal when determining that the first serial code set is identical to a second serial code set, so as to provide a variety of more sophisticated, safer and uneasy interfered encoding/decoding functions to various wireless control procedures.
    Type: Application
    Filed: December 1, 2009
    Publication date: April 21, 2011
    Applicant: MARKETECH INTERNATIONAL CORP.
    Inventors: Hsing-An Tsai, Kai-Hsiang Hsu, Yu-Hsin Wang, Jia-Zong Chen
  • Patent number: 7924184
    Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and a channel of high-speed serial data signal interface (e.g., transceiver) circuitry. To facilitate enabling the integrated circuit to support any of many possible different high-speed serial communication protocols, the channel is hard-wired to include a parallel data bus of fixed width for exchanging parallel data with the programmable circuitry. Regardless of the protocol being implemented, the full width of this bus is always used. A portion of the programmable circuitry is programmed to convert data between the block width and a group width, which can be different from the block width and which is used for the data elsewhere in the integrated circuit.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: April 12, 2011
    Assignee: Altera Corporation
    Inventors: Allen Chan, Sergey Shumarayev, Wilson Wong
  • Patent number: 7924185
    Abstract: A shift register SR configured to successively take in and hold input serial data on the basis of a first clock signal, a pattern detection section configured to detect a predetermined pattern contained in the serial data taken in the shift resister and a second clock generation section configured to determine timing of output of the serial data held in the shift register on the basis of a result of this detection are provided to detect the desired pattern contained in the serial data in the course of transferring the serial data for conversion from the serial data to parallel data to the shift resister, and to determine timing of conversion to the parallel data on the basis of a result of this detection, thus reducing the latency and achieving an improvement in communication speed and a reduction in circuit area.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: April 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroto Fukuhisa
  • Patent number: 7924187
    Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: April 12, 2011
    Assignee: Broadcom Corporation
    Inventor: Wael William Diab
  • Patent number: 7924186
    Abstract: A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: April 12, 2011
    Assignee: Broadcom Corporation
    Inventor: Wael William Diab
  • Patent number: 7920079
    Abstract: A serial signal receiving device, includes: a serial-parallel converter that converts a transmitted serial signal into a parallel signal, wherein the serialized signal is obtained by the plural signal; a storage unit that stores phase difference information indicating a phase difference among the plural signals; and a correcting unit that corrects a phase relation among the plural signals of the parallel signal output from the serial-parallel converter based on the phase difference information stored by the storage unit.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: April 5, 2011
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Hirokazu Tsubota, Toshio Hisamura, Atsushi Ugajin
  • Publication number: 20110057819
    Abstract: In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.
    Type: Application
    Filed: October 8, 2010
    Publication date: March 10, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Akira Ide, Ryuji Takishita
  • Publication number: 20110018747
    Abstract: A waveform memory 66 stores data streams with each data stream having M-bit parallel data. A sequence memory 60 stores sequence information and data discard information on the amount of data to discard from the last data in each data stream. A sequencer 62 and a waveform memory controller 64 access the waveform memory 66 to provide the data streams using the sequence information. A barrel shifter 68 shifts data in the data stream according to the number of effective data of the last parallel data in the previous data stream if the number of the effective data is less than M. A data shift controller 100 generates data enables indicating whether the data in the data stream are effective or not based on the data discard information. A combiner 72 combines the effective data in the data stream using the data enables.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 27, 2011
    Applicant: TEKTRONIX INTERNATIONAL SALES GMBH
    Inventor: Yoshikazu Shinoda
  • Patent number: 7876244
    Abstract: The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: January 25, 2011
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Robert Brunner, David Gordon, Martin Julien, Ludovic Beliveau
  • Patent number: 7876245
    Abstract: A parallel-to-serial converting circuit includes a first alignment unit configured to receive and serially align parallel data included in a first group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit also includes a second alignment unit configured to receive and serially align parallel data included in a second group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit further includes a third alignment unit configured to serially align and output the serially aligned parallel data that is output from the first alignment unit and the second alignment unit. The first alignment unit and the second alignment unit drive an output node in response to activated data of received parallel data.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Geun-Il Lee
  • Publication number: 20110012761
    Abstract: In one embodiment, a semiconductor integrated device includes a plurality of semiconductor chips each having a first internal circuit and a second internal circuit and being stacked while displaced from each other. The first internal circuit processes a data signal in accordance with a predetermined process. The second internal circuit receives a request signal from a transmission source and determines whether the request signal is a request to itself or not. When the request signal is the request to the second internal circuit itself, the second internal circuit receives a data signal from a transmission source and outputs the data signal to the first internal circuit. When the request signal is not the request to the second internal circuit itself, the second internal circuit transfers the request signal to a transfer destination, receives the data signal from the transmission source and transfers the data signal to the transfer destination.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 20, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki Morimitsu
  • Publication number: 20110006932
    Abstract: A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first flip-flop group is controlled by a first clock signal. The second flip-flop group includes a plurality of flip-flops, where the second flip-flop group is controlled by a second clock signal, and the flip-flops of the second flip-flop group are respectively connected to output nodes of the flip-flops of the first flip-flop group. The programmable frequency divider is coupled to each of the flip-flops of the second flip-flop group, and is utilized for receiving a control signal and generating the second clock signal by performing a frequency-dividing operation according to a frequency-dividing factor set by the control signal.
    Type: Application
    Filed: July 7, 2009
    Publication date: January 13, 2011
    Inventor: Yan-Bin Luo
  • Patent number: 7864084
    Abstract: A serializer includes a first stage configured to convert m-bit-wide parallel data into n-bit-wide parallel data, where n is 2x, m?2x+y, x is an integer of at least 1, and y is an integer of at least 1, where the first stage includes a memory unit configured to store the m-bit-wide parallel in response to a timing signal and a first multiplexer configured to output the n-bit-wide parallel data in response to a frequency-multiplied derivative of the timing signal, and a current mode logic (CML) multiplexer stage configured to convert the n-bit-wide parallel data into serial data on successive transitions of n phase-shifted versions of the frequency-multiplied derivative of the timing signal.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: January 4, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Muralikumar A. Padaparambil
  • Publication number: 20100328116
    Abstract: Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a serial data stream. A rotator circuit may receive the delayed serial data streams and rearrange bits in the serial data streams. Register circuits may receive the output of the rotator circuit and collectively output, in parallel, a number of bits of one of the serial bit streams.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Chung Kuang Chin, Prasad Paranjape
  • Publication number: 20100321573
    Abstract: An apparatus and a method for providing serialized HDMI data from an HDMI source to an HDMI sink. An HDMI transmitter may include inputs including control inputs, a deserializer, and a parser. The inputs may receive serialized HDMI data from an HDMI data source. A deserializer may deserialize the serialized HDMI data received on each of the respective inputs and outputting parallel data for each of the inputs. A parser may parse the parallel data output from the deserializer from each of the respective inputs into serial video data at a first clock rate and audio data at a second clock rate. Control inputs of the transmitter may be set to a first mode in which from the deserializer is caused to bypass the parser, and the parallel data is output from the HDMI transmitter.
    Type: Application
    Filed: November 5, 2009
    Publication date: December 23, 2010
    Applicant: ANALOG DEVICES, INC.
    Inventor: Christian Willibald BOHM