Abstract: A mixed signal device includes an analog circuit and a digital circuit coupled to the analog circuit. The digital circuit includes a component that samples a signal at a sampling rate that is dynamically variable by the digital circuit based on the bandwidth of the incoming signal. The digital circuit is to automatically assert a signal to the analog circuit to change a bias current of the analog circuit based on a change to the sampling rate in the digital circuit.

Abstract: A semiconductor device using analog-to digital (AD) conversion realizes reliable control so that, at the time of AD converting reference voltage, a low-voltage transistor in a reference voltage generating circuit is not destroyed by voltage held in a sample and hold circuit. In a semiconductor device, when an instruction of detecting a reference voltage value is received, a switch control unit controlling switching of an input signal of an internal AD converter temporarily automatically couples an input node of a sample and hold circuit and a ground node and, after that, couples the input node of the sample and hold circuit and an output node of a reference voltage generating circuit.

Abstract: An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.

Abstract: A switched-capacitor input circuit which receives an analog input signal, and samples and holds the analog input signal, comprising a differential amplifier, a first capacitor, one terminal of the first capacitor being connected to a non-inverting input terminal of the differential amplifier, a second capacitor, one terminal of the second capacitor being connected to an inverting input terminal of the differential amplifier, a first switch configured to connect the other terminal of the first capacitor to one of a first reference voltage and a second reference voltage, a second switch configured to connect the other terminal of the second capacitor to one of the first reference voltage and the second reference voltage, and a third switch configured to connect the other terminal of the first capacitor to the other terminal of the second capacitor.

Abstract: A Digital-to-Analog Cjonverter contains a digital shift register and a digital multiplexer. Durir g each input signal clock period, the Digital-to-Analog Converter is multiplexed in time to perform multiple conversions on samples stored in the shift register. In this way, a weighted average of seyeral signal samples is calculated, which corresponds to a FIR filter operation. Errors due! to Quantisation Noise, INL or DNL undergo the same FIR filter characteristic.

Abstract: An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at 1/4 or 3/4 of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step.

Abstract: An analog to digital converting system (200) includes an analog to digital converter (ADC) circuit that is formed by a plurality of parallel ADCs (ADC 1 ADC N) for continuous sequential processing of an input analog voltage signal. Each of the ADCs is a type that employs a capacitor digital to analog converter (DAC) (209, 701) therein. The system further includes a sample and hold circuit (220) coupled to the parallel ADCs by a conductive interconnect wiring pattern (203). The sample and hold circuit includes a sampling switch (207) and a hold capacitance formed by the parallel combination of a hold capacitor (205) and the distributed parasitic capacitance (204) of the conductive interconnect wiring pattern (203). During the hold phase of the sample and hold circuit, charge is redistributed from the hold capacitance to all of the capacitors (211) of the capacitor DAC, which serve as a secondary hold capacitance.

Abstract: A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.

Abstract: An A/D converter has an analog multiplexer stage which selects one of a plurality of first analog signals as a second analog signal, an amplifier stage which amplifies the second analog signal to generate a third analog signal, an A/D conversion stage which converts the third analog signal into a digital signal, and a sequencer which controls those stages. The sequencer performs input switching processing in the analog multiplexer stage on completion of sample hold processing by the A/D conversion stage, when performing a plurality of times of A/D conversion processing sequentially, without waiting for completion of the A/D conversion processing.

Abstract: A sampling circuit for ADC includes an external input terminal, a sampling circuit and an auxiliary circuit which are connected with the external input terminal, a clock circuit and an external output terminal which are connected with the sampling circuit, and a clock feedthrough circuit connected with the auxiliary circuit, wherein the clock feedthrough circuit is respectively connected with the clock circuit and the external output terminal. The sampling circuit for ADC of the present invention decreases the impact of clock feedthrough on signal sampling, improves linearity of sampling FET, reduces harmonic distortion of the sampling circuit and improves sampling speed thereof, and improves sampling accuracy of the sampling circuit for ADC.

Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.

Abstract: A system includes a first storage element to store an input signal for a first sampling lane for a SHA-less stage. A first switch is connected with the first storage element, the first switch to control when the first storage element stores the input signal for sampling on the first sampling lane. A second switch is connected in series with the first switch, the second switch to control an instance for sampling the input signal stored on the first storage element for the first sampling lane.

Abstract: A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle.

Abstract: Disclosed herein are example methods, systems, and devices for compressed sensing analog to digital conversion. In an example embodiment, a multiplication circuit is configured to multiply an input signal with a measurement signal to produce a multiplied signal, where the measurement signal includes data from a column of a measurement matrix. The measurement matrix may be generated by a linear feedback shift register (LFSR)-based measurement-matrix generator. An integration circuit may be coupled to the multiplication circuit and configured to integrate the multiplied signal for a predefined amount of time to produce an integrated signal. An analog to digital converter (ADC) circuit may be coupled to the integration circuit and configured to (i) sample the integrated signal and (ii) produce an output signal comprising at least one sample of the integrated signal.

Abstract: A successive approximation (SAR) analog-to-digital converter for generating a digital signal of N bits is provided. The converter includes a capacitive digital-to-analog conversion circuit including an (N?1)-th conversion unit to a first conversion unit. Each of the first conversion unit to the (N?2)-th conversion unit includes a capacitor. The (N?1)-th conversion unit comprises a number of sub-capacitors. Each of the sub-capacitors of the (N?1)-th conversion unit has substantially the same capacitance with corresponding capacitor of the first conversion unit to the (N?2)-th conversion unit. During the conversion process, the SAR control circuit, after generating the value of the most significant bit (MSB) of the digital signal, generates the value of the next bit by controlling the (N?1)-th conversion unit. Then, the SAR control circuit repeatedly uses at least one of the sub-capacitors of the (N?1)-th conversion unit to generate the value of other bits to perform self linear compensation.

Abstract: An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.

Abstract: A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches.

Abstract: An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.

Abstract: A method and system for monitoring an output of an electronic processing component which detects an out-of-range value in the output of the electronic processing component during one time period during which one channel of input channels of a time multiplexer provides an input signal to the electronic processing component. Corrective actions are performed based on the detected out-of-range value. The corrective actions including excluding further multiplexing of signals from the one channel of the input channels.

Abstract: Techniques pertaining to an analog sample circuit are disclosed. One embodiment of the analog sample circuit shows characteristics of low distortion and high linearity, which can be used in many circuits including integrated circuits (IC). In a switch circuit or an analog sample circuit of one embodiment, a constant voltage module is configured to stabilize the gate-source voltage of the PMOSFET switch as the sample switch, so that the gate-resource voltage of the PMOSFET switch doesn't vary with the input signal Vin; a switch circuit is configured to ensure that the switch circuit or the analog sample circuit is capable of processing the input signal lower than a minimum voltage in the circuit.

Abstract: A method for signal processing includes accepting an analog signal, which consists of a sequence of pulses confined to a finite time interval. The analog signal is sampled at a sampling rate that is lower than a Nyquist rate of the analog signal and with samples taken at sample times that are independent of respective pulse shapes of the pulses and respective time positions of the pulses in the time interval. The sampled analog signal is processed.

Abstract: A sensor circuit for obtaining physical quantities with a small margin of error even when the temperature varies is provided. The sensor circuit includes a sensor, a sampling circuit for obtaining a voltage value or a current value of a signal output from the sensor during a predetermined period and holding the value, and an analog-to-digital converter circuit for converting the held analog voltage value or current value into a digital value. The sampling circuit includes a switch for obtaining the voltage value or the current value and holding the value. The switch includes a transistor including an oxide semiconductor in a channel formation region.

Abstract: An Analog to Digital Converter (ADC), an analog-to-digital conversion method, and an integrated circuit including the ADC. The ADC includes an input adjustment buffer stage, a sub-ADC, and a sample switch. The sample switch is coupled between the output node of the input adjustment buffer stage and the input node of the sub-ADC. When the sample switch is opened, the input adjustment buffer stage is configured to switch between a first work state and a second work state according to a predetermined rule, and to adjust an input voltage signal of the input adjustment buffer stage based on transitions between the first and second work states. When the sample switch is closed, the input adjustment buffer stage is configured to provide an adjusted voltage signal to the input node of the sub-ADC, and the sub-ADC is configured to perform an analog-to-digital conversion onto the adjusted voltage signal.

Abstract: An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.

Abstract: An arithmetic operation circuit provided in a delta-sigma modulator of a delta-sigma A/D converter includes two reference capacitors which are respectively provided at a positive side input node and a negative side input node of an operational amplifier. When a signal corresponding to an output of the modulator is added or subtracted to or from an input signal, the amount of charge added to the input node of the operational amplifier is made to be always the same regardless of the reference voltage by complementarily switching the connection of the reference capacitors at the positive side input node and the negative side input node, and thereby the potential of the input node of the operational amplifier is made to converge to the common mode potential of the circuit.

Abstract: A method of reducing a water-wave noise for an analog to digital conversion includes performing sampling on an analog input signal; determining whether the analog input signal is interfered with by a periodic noise such that a water wave is generated; and executing one or both of the following steps when the analog input signal is interfered with by the periodic noise: adjusting a sampling frequency of the ADC, and adjusting a noise frequency of the periodic noise.

Abstract: A track and hold circuit has a main transistor for which the gate voltage is provided by a buffer circuit which is supplied with a different voltage supply than the circuit of the main transistor. This avoids the need for a bootstrap circuit.

Abstract: A method of reducing column fixed pattern noise including calibrating a readout circuit, wherein the readout circuit is electrically connected to at least one programmable gain amplifier and an analog-to-digital converter. Calibrating the readout circuit includes electrically disconnecting the readout circuit from a pixel output and electrically connecting a pixel reset input of the readout circuit to a pixel output signal input of the readout circuit. Calibrating the readout circuit further includes comparing a measured output of the readout circuit to a predetermined value and storing the comparison result in a non-transitory computer readable medium. The method further includes operating the readout circuit, the operating the readout circuit includes receiving a pixel sample signal and outputting a calibrated output based on an operating output and the stored comparison result.

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract: A sampling circuit, such as the sampling circuit of a successive approximation analog-to-digital converter (ADC), provides anti-aliasing filtering of a sampled input signal. The circuit samples the input signal using multiple capacitors, wherein each capacitor samples the input signal at a distinct time during a sampling time interval. The circuit combines the samples stored on different capacitors during a conversion time interval, and generates a digital output signal using the combined samples. In one example, a first bit of the output signal is generated using a sample stored on a first capacitor, and second bit of the output signal is generated using a sample stored on a second capacitor. In another example, the circuitry performs finite or infinite impulse response (FIR or IIR) filtering of the input signal, where a filter characteristic is determined by the relative sizes of the capacitors used for sampling.

Abstract: A reference voltage generator generates a reference voltage at the time of sampling a received input signal. A sampling time controller detects a change in the reference voltage. When the reference voltage rises to a determined threshold, the sampling time controller determines that sampling is completed, and generates a sampling clock in which sampling time is controlled on the basis of an external clock.

Abstract: A digital-to-analog converter (DAC) includes, in a segment of the DAC, a first switch and a second switch. The first switch includes a first pair of transistors having a first set of inputs and has a first output connected to an output of the DAC. The second switch includes second and third pairs of transistors having second and third sets of inputs, respectively, and has a second output that is connected to the output of the DAC. A driver module generates control signals to drive the first, second, and third sets of inputs based on data received by the DAC for conversion from digital to analog format at a conversion rate determined by a clock. The control signals toggle one of the first and second switches during each cycle of the clock.

Abstract: A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.

Abstract: A sample and hold circuit and the method thereof are disclosed. The sample and hold circuit may be applied in voltage regulators or other circuits. The sample and hold circuit comprises: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a control circuit configured to receive the input signal and the output signal, and wherein based on the input signal and the output signal, the control circuit generates a digital signal, and wherein the digital signal increases when the output signal is lower than the input signal, and maintains when the output signal is larger than or equal to the input signal; a digital-to-analog converter (DAC) configured to convert the digital signal to the output signal.

Abstract: Embodiments of the invention provide a pulsed signal detection system with reduced noise bandwidth in the frontend. Analog to digital conversion speed is decoupled from the pulsed duty cycle timing. This in turn reduces the power consumption of the ADC and the front end while providing a high dynamic range. The ADC may be a continuous time sigma delta converter to reduce the drive requirements of the front end.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: A successive approximation AD converter includes a DA converter that converts a higher conversion data greater than an approximate value into an analog higher converted voltage and converts a lower conversion data less than the approximate value into an analog lower converted voltage; a sample-and-hold circuit that samples and holds voltage differences between an input voltage and each of the higher converted voltage and the lower converted voltage; a comparator that outputs a first comparison result indicating whether the input voltage is greater or less than the higher converted voltage and a second comparison result indicating whether the input voltage is greater or less than the lower converted voltage; and an operation unit that changes the approximate value based on the first comparison result and the second comparison result, and changes a next higher conversion data and a next lower conversion data based on the changed approximate value.

Abstract: A circuit includes an input, two or more sampling capacitors each in a different channel, means for connecting each sampling capacitor to the input, means for discharging the sampling capacitors to a given voltage in a reset phase, and means to use the voltage across the sampling capacitor for further processing in a hold phase. The two sampling capacitors operate in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in the hold phase.

Abstract: An AD (analog-to-digital) conversion circuit includes a capacitor array formed of a plurality of capacitors; a sample hold circuit configured to apply an analog input voltage input through an input terminal to the capacitor array so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed; a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, and to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; and a sampling time adjusting circuit configured to measure a period of time when a voltage on an input side of the sample hold circuit reaches a threshold value defined in advance relative to the reference voltage, and to set a time determined according to the period of time as the sampling time.

Abstract: The discrete time analog circuit (100) is provided with: a rotate capacitor circuit (150); an amplifier (141) that is connected to the input line or the output line of the rotate capacitor (150), and amplifies the input potential or input charge; a coefficient circuit (140) that is positioned in series with the amplifier (141), and has two history capacitors (143-1, 143-2) positioned parallel to each other; a first active capacitor among the two history capacitors (143-1, 143-2) that is connected to and charges the amplifier (141); and a clock generation circuit (110) that is connected to the input line or the output line without the involvement of the amplifier (141), and that sequentially changes the pairing of the rotate capacitor circuit (150) a second active capacitor, which shares a charge with the rotate capacitor circuit (150).

Abstract: A sampling circuit for ADC includes an external input terminal, a sampling circuit and an auxiliary circuit which are connected with the external input terminal, a clock circuit and an external output terminal which are connected with the sampling circuit, and a clock feedthrough circuit connected with the auxiliary circuit, wherein the clock feedthrough circuit is respectively connected with the clock circuit and the external output terminal. The sampling circuit for ADC of the present invention decreases the impact of clock feedthrough on signal sampling, improves linearity of sampling FET, reduces harmonic distortion of the sampling circuit and improves sampling speed thereof, and improves sampling accuracy of the sampling circuit for ADC.

Abstract: An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.

Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.

Abstract: A switching scheme is used during a calibration mode for determining calibration coefficients of each calibrated stage of a pipeline analog-to-digital converter (ADC). A calibrated stage of the pipeline ADC includes an amplifier for amplifying a residue voltage of the stage and a sampling capacitor comprising a plurality of sub-capacitors. The plurality of sub-capacitors have a first terminal connected to an input of amplifier and a second terminal connected to one or more switches that selectively couple the second terminal to the input terminal of the stage, a first reference voltage or a second reference voltage lower than the first reference voltage. During foreground calibration, a number of measurements are taken at an output of the amplifier to determine the calibration coefficient of the calibrated stage.

Abstract: An apparatus and method of successive approximation analog-to-digital conversion for receivers comprising that during a sample mode, connecting an array of capacitors to a plurality of sampling switches coupled to a plurality of amplified input signals, and during a conversion mode, connecting in common the array of capacitors to a comparator and isolating the array of capacitors from the plurality of sampling switches. Additionally, filtering is done by the summation of samples at phase offsets.

Abstract: A digitally controlled variable capacitance integrated electronic circuit module (100) comprises a set of basic cells in a matrix arrangement. Each basic cell itself comprises a functional block (11) which can be switched between two individual capacitance values, a control block (12), and a control junction connecting the control block and the functional block of said basic cell. The functional blocks and the control blocks are grouped into separate regions (110, 120) of the matrix arrangement, to reduce capacitive interaction between output paths and power supply paths of the module. The functional blocks can still be switched in a winding path order within the matrix arrangement. A module of the invention can be used in an oscillator capable of producing a signal at 4 GHz.

Abstract: A method and system for implementing a gain control with fine resolution and minimal additional circuitry. The fine digital gain control may be deployed in conjunction with a coarse switched gain at the front end of a sampling receiver. The fine digital gain control mechanism is configured to receive an input signal and moderate gains applied to the received input signal. The output of a low noise amplifier (LNA) is connected to a switched attenuator which provides fine gain stepped gain control. The output of this stage is connected to the switch stage whose output is connected to a charge redistribution successive approximation register digital-to-analog converter (SAR ADC) configured to convert an analog waveform into a digital representation.

Abstract: An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal, wherein if the clock for the charge pump is running faster than an analog front end (“AFE”) video sampling clock, a state-machine control is configured to: skip the charge pump clock period right before a video sample signal falling edge, thereby recovering to a normal operation the next charge-pump clock period, wherein this duty cycle modulation of charge pump clock will not substantially impact charge pump output.

Abstract: A method for digitizing an analog signal through a pipelined analog-to-digital converter (ADC) may include pipelining a sample sub-stage, a quantization sub-stage and an amplification sub-stage to an ADC lane. Within a first of multiple pipelined stages, clock phases may be assigned to the ADC lane, including a sample clock phase, a quantization clock phase, and an amplification clock phase such that the quantization clock phase is non-overlapping with the sample clock phase and the amplification clock phase. The non-overlapping feature may be facilitated by generating multiple reference clock phases for the sub-stages of multiple ADC lanes, and interleaving assignment of the sample clock phase, the quantization clock phase, and the amplification clock phase to the reference clock phases among the multiple lanes.

Abstract: A two-channel time-interleaved analog-to-digital converter (TIADC) system that provides for estimation and correction of offset, gain, and sample-time errors. Error in the offsets of the two ADCs that form the TIADC produces a spurious signal at the Nyquist frequency that can be used to minimize the difference of offsets of the ADCs. The difference in gain between the two ADCs produces spurious signals reflected around the Nyquist frequency whose magnitudes can be reduced by minimizing the difference in signal power between the two ADCs. An Automatic Gain Control loop corrects the scaling of the input signal due to the average of the gains of the ADCs. Phase error produces spurious signals reflected around the Nyquist frequency that are ?/2 out of phase with those due to the gain error. Minimizing the difference between the correlation of consecutive signals from the ADCs reduces the magnitude of these image tones.