Having Variable Sampling Rate Patents (Class 341/123)
  • Patent number: 6037886
    Abstract: A read channel circuit (27) for a hard disk drive system (10) includes an analog-to-digital converter (38) having an output (39) which is supplied through a filter (41) to a detector (46) and to a band/error circuit (47). The band/error circuit extracts from the filter output a band value (48) and an error value (49). The band and error values are used by a timing recovery loop (51, 53) to control the operation of the analog-to-digital converter, and are used by a gain recovery loop (51, 54) to facilitate an automatic gain control function for an analog circuit (36). The band/error circuit uses targets and thresholds which are each a power of two, so that a predetermined number of the least significant bits from the output of the filter can be used as the error value, without modification. The band value is determined from the most significant bits of the output of the filter.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: March 14, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Gennady Feygin
  • Patent number: 6028542
    Abstract: A digital signal processing apparatus for matching the sampling frequency of an input digital signal to an internal sampling frequency. The digital signal processing apparatus has a sampling frequency converting unit for matching the sampling frequency of an input digital signal to an internal sampling frequency, a sampling frequency detection unit for detecting the sampling frequency of the input digital signa, a frequency difference calculating unit for finding the frequency difference between the inherent sampling frequency of the input digital signal and the sampling frequency detected by the sampling frequency detection unit and a pitch shifting unit for shifting the pitch of an output digital signal of the sampling frequency converting unit based upon said frequency difference. If the input digital signal has the sampling frequency slightly offset from the inherent sampling frequency, the signal of the inherent sampling frequency can be recovered, while the pitch can be restored to the inherent pitch.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: February 22, 2000
    Assignee: Sony Corporation
    Inventors: Takao Fukui, Kazutoshi Nomoto, Michimasa Sekiguchi
  • Patent number: 6005901
    Abstract: A communication system includes a data sampling rate converter that uses a closed-loop control arrangement to convert an input signal at a first sampling rate to a second, asynchronous, sampling rate without requiring extensive output buffering. A small number of data registers in a first-in-first-out output buffer is used to receive and store computed data samples at a controlled rate and to pass these data samples to the output at a second rate. The output buffer indicates, the current capacity of the output buffer for use by a frequency ratio estimator, which is arranged to respond by providing an estimate of the actual ratio between the first rate and the second rate. A controller responds to the frequency ratio estimator by generating the controlled rate at which the computed data samples are to be passed to the output buffer. In this manner, the processed data samples are passed to the output buffer at the controlled rate and are output at the second rate.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: December 21, 1999
    Assignee: Advanced Micro Devices
    Inventor: Alfredo R. Linz
  • Patent number: 5917438
    Abstract: A first data storing and outputting apparatus includes a coding unit for coding data of a program through N coding processes and generating N sets of coded data of the program, N being a natural number more than one, a memory for storing the N sets of coded data of the program, and a reading and outputting circuit responsive to a request for selectively reading and outputting one of the N sets of coded data of the program from the memory.
    Type: Grant
    Filed: June 25, 1996
    Date of Patent: June 29, 1999
    Assignee: Victor Company of Japan, Ltd.
    Inventor: Ichiro Ando
  • Patent number: 5900830
    Abstract: A customized album recording system is under the control of a central microprocessor or mini-computer. A master library or storage medium is filled with a repertoire of recorded information items (such as musical selections) which may originate with any suitable source, such as phonograph records, tapes, sound tracks, compact discs, or the like. Each information item is stored in the library under its own address. On read out, an operator keys in the addresses identifying the selected items which are read out of the library medium and stored in a large capacity memory, usually to provide about forty-five minutes of total listening time. Then, all of the music is read out of that large capacity memory and recorded at a high speed onto a suitable album size medium, such as a tape cassette, for example. The source music and the customized album music are usually recorded in an analog form. The music which is processed within the system is in a digital form.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: May 4, 1999
    Assignee: Magic Music Cassette Co., Inc.
    Inventor: Robert G. Scheffler
  • Patent number: 5893899
    Abstract: A method and apparatus for sampling an analog signal permits the identification of those samples in which data was lost in the sampling process. A data reference element is generated for each sample element, the data reference element having a corresponding sample element. A user friendly display technique is provided to permit the user to controllably display the sampled signal, clearly showing those portions of the signal in which information was lost contrasted with those portions of the signal that were sampled intact.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: April 13, 1999
    Inventors: William J. Johnson, Guillermo Vegatoro, Larry M. Lachman, David Flores
  • Patent number: 5847974
    Abstract: A method of measuring information related to an object, includes the steps of measuring a change of a measurement error with respect to time, and determining the frequency of measurements for measuring the measurement error, to be done during a measurement period, on the basis of the change in measurement error. Then, in the measurement period, a measured value is corrected by using a latest measurement error.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: December 8, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuzo Mori, Koichi Sentoku, Takahiro Matsumoto, Noriyasu Hasegawa
  • Patent number: 5835031
    Abstract: When digitized signals are transmitted from a digital transmission system (NET1), e.g. a PDH system, to another digital transmission system (NET2), e.g. a SDH system, which operate at different clock rates (f.sub.1, f.sub.2), the clock rate must be adapted during the transition. To that end, the digitized signals are converted into discrete-time and value-discrete signals in a decoding unit (D1) at the clock rate (f.sub.1) of the one digital transmission system (NET1). A conversion unit (UE1) converts the discrete-time and value-discrete signals into further discrete-time and value-discrete signals, whose pulse repetition rate is adapted to a clock rate derived from the clock rate (f.sub.2) of the other digital transmission system (NET2). This is achieved e.g. with a low-pass filter (FIL1) and a sample-and-hold device (AH1). An encoding unit (K1) converts the further discrete-time and value-discrete signals into digital signals, whose bit rate is adapted to the clock rate (f.sub.
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: November 10, 1998
    Assignee: Alcatel N.V.
    Inventor: Michael Wolf
  • Patent number: 5835032
    Abstract: A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency Fsi. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio R.sub.n between the input sampling frequency Fsi and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: November 10, 1998
    Assignee: Sony Corporation
    Inventor: Nobuyuki Yasuda
  • Patent number: 5832414
    Abstract: A new method of compensating for errors in phasor estimation due to oscillations caused by discrete fourier transforms used to estimate signal frequency is provided. The method uses a variable N-point DFT to compute one or more phasors based on data acquired from one or more sampled signals. At each sampling interval the change in phasor angle between the current sampling interval and the previous sampling interval is determined and used to estimate the instantaneous frequency of the signal. A non-oscillating phasor indicative of the instantaneous magnitude, angular frequency, and phase angle of the signal is generated based on the instantaneous frequency estimate. Instantaneous frequencies are averaged over a cycle of the signal to generate an average cycle frequency. In addition, a number of discrete frequencies and corresponding DFT windows based on a fixed sampling rate and a predetermined fundamental frequency of the signal are defined and used in estimating the instantaneous frequency.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: November 3, 1998
    Assignee: ABB Power T&D Company Inc.
    Inventors: David G. Hart, James D. Stoupis, Damir Novosel
  • Patent number: 5832413
    Abstract: A method for estimating phasors and tracking the frequency of a signal during frequency ramping is provided. The method uses a variable N-point DFT periodically to compute one or more phasors based on data acquired from one or more sampled signals. The period between DFT computations is a predetermined number of sample periods. After each DFT computation, the change in phasor angle between the current phasor estimate and the most previous phasor estimate is determined and used to estimate the instantaneous frequency of the signal. The current instantaneous frequency estimate and the most previous instantaneous frequency estimate are averaged to compute an average cycle frequency. In addition, a number of discrete frequencies and corresponding DFT windows based on a fixed sampling rate and a predetermined fundamental frequency of the signal are defined and used in estimating the instantaneous frequency.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: November 3, 1998
    Assignee: ABB Power T&D Company Inc.
    Inventors: Joseph P. Benco, Frederick P. Perfect, David G. Hart, James D. Stoupis
  • Patent number: 5815101
    Abstract: A system and method for separating aliased signals from non-aliased signals in a sampling system and method wherein the input signal includes frequency components above the Nyquist limit wherein the input signal is sampled at a first sampling rate to provide a first sampled signal, the input is sampled at a second sampling rate different from the first rate to provide a second sampled signal, and the spectral patterns of the first and second sampled signals are compared to separate the aliased signals from the real or non-aliased signals. The aliased signals can be eliminated by removing any spectral component which is not present with both of the sampling rates. While the difference in the sampling rates can be arbitrary, it also can be optimized. Additional samplings at different rates can increase the degree of the correction.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: September 29, 1998
    Inventor: Gerard C. A. Fonte
  • Patent number: 5805092
    Abstract: In apparatus that measures the characteristics of the read-out signals from memory media, in the prior art, phase control of the clock signals for synchronized sampling of the measurement apparatus was performed by using the read-out signals. Synchronization discrepancies and inability to perform synchronization were produced due to the quality of the read-out signals. In the invention, a Logical processing part generates selection signals that control the selection of samples with phase information, for performing synchronization, from test signals of a recording part, which records the same signal train as the test signal train written onto the memory medium. By the control of these selection signals, samples with phase information for performing synchronization are selected from the sample train output from an A/D converter through an equalizer; these samples pass through a selection part and a control clock generating part by means of the processing of a feed-back processing part.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: September 8, 1998
    Assignee: Hewlett-Packard Company
    Inventor: Yoshiyuki Yanagimoto
  • Patent number: 5790072
    Abstract: A multi-channel integrated circuit, which includes N processing channels and a functional circuit which is time-shared between each of the N channels for processing data in accordance with a first clock strobe. Also included is a time-division multiplexed bus for providing synchronized data to and receiving synchronized data from said circuit in accordance with a second clock strobe. The data are thereby processed within said shared circuit in synchronization with said first and second clock strobes.
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: August 4, 1998
    Assignee: Lucent Technologies, Inc.
    Inventors: Christine Mary Gerveshi, Nathaniel Grier, Taiho Koh
  • Patent number: 5748120
    Abstract: A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency Fsi. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio Rn between the input sampling frequency Fsi and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW. based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: May 5, 1998
    Assignee: Sony Corporation
    Inventor: Nobuyuki Yasuda
  • Patent number: 5721689
    Abstract: A method and system for estimating phasors and tracking the frequency of a signal is provided. The method uses a variable N-point DFT to compute one or more phasors based on data acquired from one or more sampled signals. At each sampling interval the change in phasor angle between the current sampling interval and the previous sampling interval is determined and used to estimate the instantaneous frequency of the signal. Instantaneous frequencies are averaged over a cycle of the signal. In addition, a number of discrete frequencies and corresponding DFT windows based on a fixed sampling rate and a predetermined fundamental frequency of the signal are defined and used in estimating the instantaneous frequency. Once the average cycle frequency is determined the DFT window is adjusted by setting it equal to the DFT window corresponding to the discrete frequency closest to the average cycle frequency.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: February 24, 1998
    Assignee: ABB Power T&D Company Inc.
    Inventors: David Hart, Yi Hu, Damir Novosel, Robert Smith
  • Patent number: 5712635
    Abstract: A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques In one embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. In another embodiment, the digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. The frequency signal selection number is modulated using an n-th order m-bit sigma-delta modulator.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: January 27, 1998
    Inventors: James Wilson, Ronald A. Cellini, James M. Sobol
  • Patent number: 5708432
    Abstract: A digitizing system coherently samples an input signal of frequency F.sub.t and generates an output data sequence representing magnitudes of N successive samples. The digitizing system generates a timing signal by frequency dividing a clock signal of frequency F.sub.MCLK by an integer factor K and supplies the timing signal to a digitizer. The digitizer coherently samples the input signal N times over M cycles of input signal to produce an N-term data sequence representing one cycle of the input signal. The timing signal frequency sets the digitizer sampling rate. The digitizing system includes a computer programmed to execute an algorithm for finding an appropriate value for K so that the system substantially achieves coherent sampling of the input signal despite limitations in allowable ranges of K, M and N. The algorithm searches a Farey series to locate terms of the form P/Q from which it may derive candidate values of K (K=Q.sub.i *J), M (M=P*J) and N (N=Q.sub.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: January 13, 1998
    Assignee: Credence Systems Corporation
    Inventors: David Dean Reynolds, Roman Aureli Slizynski
  • Patent number: 5663729
    Abstract: The AD conversion control section of the processor sets the clock generating circuit of the output port alternately to an L-level output condition and an H-level output condition to generate a clock signal. A chip select signal is caused to be output from the chip select circuit of the output port in synchronization with output of the first clock signal by the interruption signal. Furthermore, the bit data output in series bit by bit from the AD converter in synchronization with occurrence of a clock signal is incorporated bit by bit in synchronization with the interruption signal from the input ports to be stored in the register.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: September 2, 1997
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Wada, Akira Takuma
  • Patent number: 5652533
    Abstract: An electronic circuit suitable for sampling an incoming data bit stream in order to recover the information contained in the data stream contains an input section, a reference section, and a comparing section. The input section produces a ramp signal that switches between a first endpoint voltage and a second endpoint voltage in a periodic manner. The reference section furnishes a plurality of reference voltages between the two endpoint voltages. The comparing section compares the ramp signal to the reference voltages to produce corresponding sampling signals. Each sampling signal makes a first voltage transition as the ramp signal passes a corresponding reference voltage in going from the second endpoint voltage to the first endpoint voltage. Accordingly, the first transitions of the sampling signals occur in groups, each group being spread out in time during part of a period of the ramp signal. A data sampling portion of the circuit utilizes the sampling signals to sample the input data bit stream.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: July 29, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Hee Wong, Gabriel Li
  • Patent number: 5648777
    Abstract: A data converter for converting a signal either from analog form to digital form or from digital form to analog form includes a storage register. The storage register receives and temporarily stores digital data samples. The digital data samples are transferable out of the storage register in the same sequence in which they were received. A digital signal processor coupled to the storage register is interruptible to transferred digital data samples either to or from the storage register. In this manner, the digital signal processor transfers multiple digital data samples either to or from the storage register during each interrupt rather than transferring a single data sample per interrupt, thereby reducing the number of interrupts necessary to transfer a given number of digital data samples.
    Type: Grant
    Filed: December 16, 1993
    Date of Patent: July 15, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Laurence Edward Bays, Richard Muscavage, Steven Robert Norsworthy
  • Patent number: 5627718
    Abstract: A circuit interrupter samples waveforms in a protected circuit by taking samples in pairs spaced 90 electrical degrees apart. The sum of the squares of samples in each pair, which is representative of the RMS value of the fundamental frequency of the waveform, is used for instantaneous protection by comparing a running sum of the squares for the two most recent pairs of samples to a threshold representative of the instantaneous trip pick-up value. This sum of the squares of successive two pairs of samples is also used for short delay protection. A delay between successive pairs of samples is varied to produce a selected equivalent sampling rate after a given number of samples. Samples accumulated at this equivalent sampling rate, which is sixty-four samples per cycle in the preferred embodiment, are used for long delay protection and metering.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: May 6, 1997
    Assignee: Eaton Corporation
    Inventors: Joseph C. Engel, Gary F. Saletta, Richard A. Johnson
  • Patent number: 5625359
    Abstract: A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: April 29, 1997
    Assignee: Analog Devices, Inc.
    Inventors: James Wilson, Ronald A. Cellini, James M. Sobol
  • Patent number: 5619202
    Abstract: A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: April 8, 1997
    Assignee: Analog Devices, Inc.
    Inventors: James Wilson, Ronald A. Cellini, James M. Sobol
  • Patent number: 5617088
    Abstract: A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency F.sub.si. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio R.sub.n between the input sampling frequency F.sub.si and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW. based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: April 1, 1997
    Assignee: Sony Corporation
    Inventor: Nobuyuki Yasuda
  • Patent number: 5610825
    Abstract: A method and apparatus for sampling an analog signal permits the identification of those samples in which data was lost in the sampling process. A data reference element is generated for each sample element, the data reference element having a corresponding sample element. A user friendly display technique is provided to permit the user to controllably display the sampled signal, clearly showing those portions of the signal in which information was lost contrasted with those portions of the signal that were sampled intact.
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: March 11, 1997
    Inventors: William J. Johnson, Guillermo Vegatoro, Larry M. Lachman, David Flores
  • Patent number: 5602749
    Abstract: The present invention relates to a method and apparatus for monitoring machinery in which data is collected and stored based on application specific retention rules. Based on an alarm value, data records are adjusted by reducing the spectral resolution, coefficient precision and time intervals between records. An alarm is activated when the data value is greater than a predetermined alarm threshold value. Memory management can compare the memory availability to projected requirements. If the projected memory requirements exceeds memory availability, the data records can be interactively decimated. When decimation cannot make available sufficient memory for projected requirements within the retention rules, an alarm is issued. Collected data can be transferred with a removable nonvolatile memory or infrared communications with a computer device.
    Type: Grant
    Filed: January 12, 1995
    Date of Patent: February 11, 1997
    Assignee: MTC
    Inventor: Frederick Vosburgh
  • Patent number: 5600527
    Abstract: A circuit breaker with a digital trip unit has a protection mode and a waveform capture mode of operation. In the protection mode, an equivalent sampling technique based upon pairs of samples spaced 90 electrical degrees apart with a pattern of delays between pairs is used to digitize the waveforms in the protected electrical system. Synchronous sampling is used in the waveform capture mode. The value of each sample is monitored in the waveform capture mode and a transfer is made back to the protection mode if a threshold value indicating an overcurrent condition is exceeded. The percentage total harmonic distortion, and per harmonic distortion for harmonics, up to and including the 27th are sequentially presented on a display on the front panel of the circuit breaker and can be transmitted along with the raw waveform data to a remote processor.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: February 4, 1997
    Assignee: Eaton Corporation
    Inventors: Joseph C. Engel, Gary F. Saletta, Richard A. Johnson
  • Patent number: 5543792
    Abstract: A sampler develops a digital representation of an analog signal at a predetermined sampling rate. The highest frequency of a period of samples is determined and, if sampling rate of the sampler exceeds the Nyquist rate, indicating oversampling, redundant sample points are discarded from the period and the reduced record is stored. A multiplicity of periods make up a recorded session. To reconstruct the original signal, a common time domain is determined and the reduced records are expanded based upon the common time domain.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: August 6, 1996
    Assignee: International Business Machines Corporation
    Inventors: William J. Johnson, Guillermo Vegatoro, Larry M. Lachman
  • Patent number: 5544065
    Abstract: The frequency and sampling interval for synchronous sampling of an ac signal of unknown or varying frequency are accurately determined within one cycle by apparatus including an input circuit which generates a single input pulse for each cycle of the ac signal. The count of clock pulses maintained by a free running counter is recorded at each input pulse. The frequency of the ac signal is determined from the period of the ac signal calculated from the difference in the count stored at consecutive input pulses. This difference in the count is divided by the desired sampling rate to generate the sampling count which is repetitively added to the current running count to generate an interrupt count. A sampling interrupt utilized by an analog to digital converter to digitize the ac signal is generated when the running count equals the interrupt count.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: August 6, 1996
    Assignee: Eaton Corporation
    Inventors: Joseph C. Engel, Thomas J. Kenny
  • Patent number: 5532926
    Abstract: A control system employing a sample and early-off hold function implements the hold function in such a way as to effectively create a filter function. Instead of holding a constant value for the duration of a sample period, the control system turns the held sample value on and off multiple times during the sampling period. The notch filter is tunable by adjustment of the number, time and duration of the held sample intervals.
    Type: Grant
    Filed: January 11, 1995
    Date of Patent: July 2, 1996
    Assignee: Maxtor Corporation
    Inventors: Paul F. Dunn, Randall C. Bauck
  • Patent number: 5530341
    Abstract: A trigger system for a digital oscilloscope operating in external clock mode. Every n pulses, the trigger system generates a trigger signal. The trigger system therefore provides a trigger every n samples of the input signal waveform.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: June 25, 1996
    Assignee: Tektronix, Inc.
    Inventors: Pavel R. Zivny, Edward E. Averill
  • Patent number: 5528527
    Abstract: A sampling frequency converter capable of performing an operation of multiplications and additions at a lower speed and realizing with a small amount of hardware.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: June 18, 1996
    Assignee: Kabushiki Kaisha Kenwood
    Inventors: Toshio Iwata, Toshiaki Nishida, Tsuyoshi Tsumuraya
  • Patent number: 5512897
    Abstract: A method and apparatus for digital-to-analog conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional filtering techniques. In one embodiment, an oversampling modulator receives digital input samples and, responsive to a noise-shaped clock signal, modulates the digital input samples to produce modulated samples at an oversampling rate. The oversampling rate preferably is equal to an oversampling ratio times a preselected input sample rate. A DAC, coupled to the modulator, converts the modulated samples to an analog signal.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: April 30, 1996
    Assignee: Analog Devices, Inc.
    Inventors: James Wilson, Ronald A. Cellini, James M. Sobol
  • Patent number: 5483239
    Abstract: A microprocessor-based system includes a central processing unit (CPU) and a CPU memory coupled by a CPU bus. A DMA sampler is coupled to the CPU, the CPU memory and the CPU bus. The DMA sampler includes sampling circuitry which is implemented as a finite state machine to maintain a substantially exact sampling rate on at least one analog input signal provided to the DMA sampler. The DMA sampler also includes DMA circuitry implemented as a data flow machine, which requests bus mastership from the CPU when samples obtained by the DMA sampler are available for transfer to the CPU memory. In response to the request, the CPU relinquishes bus mastership to the DMA sampler which provides the sample to the CPU memory and returns bus mastership to the CPU.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: January 9, 1996
    Assignee: Westinghouse Electric Corporation
    Inventors: Wayne S. Arczynski, Stuart P. Broadwater, Larry D. Aschliman
  • Patent number: 5475390
    Abstract: An electronic musical instrument comprises a tone generator for generating a plurality of different digital waveform signals corresponding to different timbres, and a device for setting a plurality of ranges defined by two parameters, a first one of the parameters being a pitch parameter and a second one of the parameters being a key touch parameter. The parameters vary according to the musical performance, and a range for the pitch parameter in combination with a range for the key touch parameter respectively designating one of the plurality of different digital waveform signals having different timbres. An input device is provided for inputting the two parameters according to a musical performance.
    Type: Grant
    Filed: June 20, 1994
    Date of Patent: December 12, 1995
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shigenori Morikawa, Kohtaro Hanzawa, Hiroyuki Sasaki, Hiroshi Morokuma
  • Patent number: 5444459
    Abstract: A signal acquisition system using an ultra-wide time range digitizer with variable time interval data sampling and data storage includes signal conditioning and sampling stages, a digitizing stage for generating digital representations of a signal, and a memory for storing the digital representations. Timing circuitry controls sampling and digitizing which may be varied so as to acquire signals on linear, logarithmic, or other time bases. Signal compression may be obtained by digitizing information only when a desired change rate is observed. A display allows acquired signals to be displayed in linear, logarithmic or other manner.
    Type: Grant
    Filed: June 22, 1993
    Date of Patent: August 22, 1995
    Assignee: Zeelan Technology, Inc.
    Inventor: Hiro Moriyasu
  • Patent number: 5434564
    Abstract: Pulses are produced in accordance with physical quantity changes in order to express the amount of change by count of the pulses produced. The changes are input to a convertor which converts them to corresponding electrical output values which are made available to a sample and hold circuit and to a first input of a comparator. An output value accepted from the convertor is held, as a held value, in the sample and hold circuit and provided therefrom to a second input of the comparator. The comparator produces an output pulse, so as ultimately to provide a trigger pulse and to be counted, only when the first input of the comparator differs from the second input thereof by a preset reference amount. At each trigger pulse, the sample and hold circuit accepts the next available electrical output value from the convertor as the value to be hold and provided to the comparator.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: July 18, 1995
    Assignee: Koga Electronics Co., Ltd.
    Inventor: Tadashi Nakanuma
  • Patent number: 5398029
    Abstract: A sampling rate converter includes an arithmetic circuit for performing digital filtering processing for sampling rate conversion, and a circuit for calculating a sampling rate ratio. A memory circuit stores a plurality of groups of filter coefficients which are used in the digital filtering processing performed in the arithmetic circuit, corresponding to a plurality of sampling rate ratio ranges. A select circuit selects a filter coefficient group corresponding to the sampling rate ratio. The select circuit is arranged such that even if the sampling rate ratio is outside a sampling rate ratio range corresponding to a filter coefficient group selected at the present time, the select circuit continues to select the filter coefficient group selected at this time as long as the sampling rate ratio is within a predetermined range outside the sampling rate ratio range.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: March 14, 1995
    Assignee: Nippon Precision Circuits Inc.
    Inventors: Akira Toyama, Minoru Takeda
  • Patent number: 5315627
    Abstract: A pseudo-random repetitive sampling circuit which is capable of sampling fast signals, sampling negative and positive time around a trigger event, and rapidly building the waveform for display. The circuit accomplishes this by acquiring negative and positive time in two different ways. Positive time information is acquired using a modified form of sequential sampling, since sequential sampling can rapidly build the signal for samples that occur after the trigger event. The system also may take multiple samples for each trigger event. For samples occurring prior to the trigger event, the system uses a modified form of random repetitive sampling. The modification comprises sampling of the waveform prior to allowing any trigger events to occur, and qualifying each trigger event so that a trigger event is only recognized when it occurs in a programmable time window after a sample.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: May 24, 1994
    Assignee: Hewlett-Packard Company
    Inventor: Steven D. Draving
  • Patent number: 5302950
    Abstract: Method of, and apparatus for, providing automatic detection of potential information loss due to undersampling and automatic detection of potential storage waste due to oversampling based on automatic determination of an analog signal's Nyquist rate. The invention acquires an analog signal, determines a maximum frequency of the analog signal and a corresponding Nyquist rate, and allows a user to select a sampling rate based on either the automatically determined Nyquist sampling rate, a user specified sampling rate, a sampling rate determined by a user specified bandwidth, or a sampling rate determined by user specified available space. The invention also informs a user when a loss of information may occur due to a sampling rate being less than the Nyquist rate. The invention also informs a user when a waste of storage may occur due to a sampling rate being greater than the Nyquist rate.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: April 12, 1994
    Assignee: International Business Machines Corp.
    Inventors: William J. Johnson, Larry M. Lachman, Guillermo Vega, Marvin L. Williams
  • Patent number: 5291140
    Abstract: Aliasing and synchronization difficulties in determining transfer functions in mixed domain (analog and digital) systems are overcome by sampling the analog signal at a higher sampling frequency that the digital signal, and zero filling the set of sampled digital data (if necessary) so that the sampled digital data corresponds to the more densely sampled analog data. By so doing, a single fixed frequency anti-alias filter in the analog channel can be used to avoid aliasing problems in mixed domain measurements over any span of frequencies, up to the entire passband of the filter. The invention is particularly illustrated with reference to measurements both across digital-to-analog boundaries and across analog-to-digital boundaries.
    Type: Grant
    Filed: August 19, 1993
    Date of Patent: March 1, 1994
    Assignee: Hewlett-Packard Company
    Inventor: Douglas R. Wagner
  • Patent number: 5260647
    Abstract: An AC input signal is sampled with a plurality of sets of equally spaced samples, but whose sample interval between the samples does not exactly divide the period of the input signal. Nevertheless, and error cancellation technique allows ultra accurate measurements to be made. The samples in each set of the plurality of sets are supplied to a computational process that extracts some parameter; e.g., RMS voltage. The extracted parameter is in error, owing to the non aliquot nature of the sampling. The size of the error is related to, among other things, where on the input waveform the associated set began. The error is a period AC function of that starting location. By arranging for n-many sets to start at phase differences of 1/n apart on the input waveform, a series of n-many parameter.sub.i are obtained that are each of the form [result.sub.i +error.sub.i ]. Thus, the error.sub.i are sampled at aliquot locations along an error function, and therefore sum to zero. Thus, averaging the parameter.sub.
    Type: Grant
    Filed: September 18, 1991
    Date of Patent: November 9, 1993
    Assignee: Hewlett-Packard Company
    Inventor: Ronald L. Swerlein
  • Patent number: 5260705
    Abstract: An analog-to-digital (A/D) converter has a simple arrangement and achieves an accurate high-speed A/D converting operation. The A/D converter comprises an analog data input unit (2), an A/D conversion circuit (3), a controller (4) for controlling the A/D conversion circuit (3), and a digital data output unit (100). The controller (4) includes a sampling time controller (5) and a bit conversion time controller (6).
    Type: Grant
    Filed: March 19, 1992
    Date of Patent: November 9, 1993
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventor: Keizo Inukai
  • Patent number: 5250907
    Abstract: In this digital signal measurement apparatus, an approach is employed to deliver a measurement signal from a measurement signal generator to a measured circuit to transform the signal on the time base through the measured circuit to a signal on the frequency base by a frequency base transform circuit and to further obtain a signal on the time base by a time base transform circuit. Thus, a difference between the signal on the time base through the measured circuit and the signal on the time base from the time base transform circuit is employed. Thus, for example, even if the measured circuit is a linear system, a measured result in the digital region and a result of the analog measurement can be in correspondence with each other. Accordingly, gain correction of a measurement signal is unnecessary, thus making it possible to prevent an increase in an error of a measured result of S/N.
    Type: Grant
    Filed: April 16, 1992
    Date of Patent: October 5, 1993
    Assignee: Sony Corporation
    Inventor: Takao Fukui
  • Patent number: 5243343
    Abstract: A signal acquisition system using an ultra-wide time range digitizer with variable time interval data sampling and data storage includes signal conditioning and sampling stages, a digitizing stage for generating digital representations of a signal, and a memory for storing the digital representations. Timing circuitry controls sampling and digitizing which may be varied so as to acquire signals on linear, logarithmic, or other time bases. Signal compression may be obtained by digitizing information only when a desired change rate is observed. A display allows acquired signals to be displayed in linear, logarithmic or other manner.
    Type: Grant
    Filed: December 3, 1990
    Date of Patent: September 7, 1993
    Assignee: Zeelan Technology, Inc.
    Inventor: Hiro Moriyasu
  • Patent number: 5235287
    Abstract: This is a technique for extending the frequency range which employs a power divider having two outputs, one output being supplied to a first A/D converter, and the other output being supplied via a delay device to a second A/D converter. A processor receives the outputs of the two A/D converters. In operation, the input signal is subjected to a known delay .tau. and both original and delayed signals are sampled simultaneously. Both sampled signals are Fourier transformed and the phase and amplitudes calculated, using the expressions:.phi.(f)=tan.sup.-1 [I(f)/R(f)]A(f)=[R.sup.2 (f)+I.sup.2 (f)].sup.1/2where R(f) and I(f) are respectively the real and imaginary parts of the frequency transform. The phase difference between the original and delayed signals is calculated and an approximation to the true frequency for each peak observed in the amplitude spectrum is estimated using the expression.phi.=2.pi.f.tau.where .tau. is the delay.In general, one would expect that when f.tau.
    Type: Grant
    Filed: July 5, 1991
    Date of Patent: August 10, 1993
    Inventors: Richard B. Sanderson, James B. Y. Tsui
  • Patent number: 5227787
    Abstract: A system is provided for converting an input digital data sampled at a first sampling frequency to an output digital data to be sampled at a second sampling frequency. The input digital data is sampled to obtain sampling data with respect to an estimating data corresponding to a data at a sampling point of the output data. The sampling is performed within a period of the least common multiple between a period of sampling of the input digital data and a period of sampling of the output digital data. The estimating data is interpolated from the obtained sampling data.
    Type: Grant
    Filed: June 30, 1992
    Date of Patent: July 13, 1993
    Assignee: Pioneer Electronic Corporation
    Inventor: Hiroyuki Kurashina
  • Patent number: 5218363
    Abstract: Current switching apparatus including at least one current switching tree comprised of cascaded sets of switching circuits, with an input set operable with sampling clock pulses supplied at a fixed frequency and the remaining cascaded sets operable at different frequencies, and further including a sample skipping circuit interconnected between successive sets for reducing the effective sampling frequency of the switching tree while maintaining the fixed frequency at which the input set operates. The sample skipping circuit includes a dump circuit selectively energized to dump selected samples produced by the input set. When the apparatus is formed of plural switching trees of different phases, a sampling clock generator having an adjustable delay circuit is used to delay sampling clock pulses by adjustable amounts so as to establish predetermined phases of sampling clock pulses of the same frequency and different phases for use in each switching tree.
    Type: Grant
    Filed: September 16, 1991
    Date of Patent: June 8, 1993
    Assignee: LeCroy Corporation
    Inventors: Walter O. LeCroy, Jr., Brian V. Cake
  • Patent number: 5208545
    Abstract: In one embodiment, the sampling order of voltage/current data channels from a power transmission line is controlled so that the average sampling instant for each channel is the same. In one example involving a six-channel system, the sampling order will alternate between 1,2,3,4,5,6 and 6,5,4,3,2,1. The sampled data is applied through a digital filter which averages the sampling instant for each channel. In another embodiment, low-pass filters are positioned on each channel, the low-pass filter introducing a predetermined delay for each channel which compensates for the sampling delay on each channel where the channels are sampled in a particular sequential order, i.e. 1,2,3,4 . . . n. The shortest delay will be present in the low-pass filter associated with the first channel, a slightly longer delay will be present in the low-pass filter associated with the second channel and so on through the nth channel.
    Type: Grant
    Filed: March 27, 1991
    Date of Patent: May 4, 1993
    Assignee: Schweitzer Engineering Laboratories Inc.
    Inventor: Edmund O. Schweitzer, III