Abstract: A resistor string digital-to-analog converter includes a high-order resistor string, first high-order switches, a high-order decoder, a low-order decoder, and a conversion unit. The high-order resistor string includes a plurality of voltage acquisition points that are coupled through unit resistors. The high-order decoder generates a first high-order control signal in accordance with a high-order bit value, and operates in accordance with the first high-order control signal to bring into conduction a first high-order switch coupled to a pair of voltage acquisition points adjacent to each other through one or more voltage acquisition points. The low-order decoder generates a low-order control signal for controlling the conversion unit. The conversion unit divides a pair of high-order analog voltages output from a pair of voltage acquisition points.

Abstract: An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.

Abstract: A sound volume control circuit includes: a first operational amplifier; a variable resistor circuit connected between an output and an inverting input of the first operational amplifier and having a plurality of resistance values; an R-2R ladder circuit connected between a voltage source of an input voltage; and a control circuit controlling the variable resistor circuit and the R-2R ladder circuit; wherein when changing a resistance value of the variable resistor circuit from a first resistance value to a second resistance value, so as to change the output voltage in a step size where a difference between the output voltage corresponding to the first resistance value and the output voltage corresponding to the second resistance value is further segmented, the control circuit changes the magnitude of the electric current flowing to the variable resistor circuit by use of the R-2R ladder circuit.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: Representative implementations of devices and techniques provide a time delay based on an input value. A digital delay may be generated based on a coarse delay and a fine delay. The coarse delay may be selected based on the input value. The fine delay may be selected from an overlapping set of fine delay intervals, based on the selected coarse delay. In some implementations, a control component may be used to select the fine delay when more than one fine delay interval is indicated.

Abstract: A digital-to-analog converter for converting digital values to an analog output signal includes a first converter section and a second converter section operating at different conversion rates. A first analog signal provided by the first converter section and a second analog signal provided by the second converter section are combined to obtain the analog output signal. The concept may be used in fields of DAC applications where the sample rate is much higher than the signal bandwidth. The limited signal bandwidth means that the maximum change between two neighboring samples is a small fraction of the whole DAC range. The first converter section may cover a large range of values, whereas for the second converter section a relatively small range of values may be sufficient.

Abstract: Polarity compensating dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a secondary voltage divider of a dual-string DAC includes a switch logic unit. The switch logic unit is configured to compensate for polarity changes in the dual-string DAC to maintain monotonicity. Monotonicity means an output voltage of a DAC either increases or stays constant for monotonically increasing functions or either decreases or stays constant for monotonically decreasing functions given an incremental change in a DAC input code. The switch logic unit is configured to compensate for polarity changes in the input voltage from the primary voltage divider to the secondary resistor string. The switch logic unit is configured to select a secondary switch among the plurality of secondary switches in a secondary voltage divider, to divide an input voltage based on a polarity indicator and a DAC input code, to maintain monotonicity.

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the multi-string DAC is configured to use the voltage change at terminals of a first string separately to the voltage drop across a first switching network that couples the first and second strings to provide an analog output in response to a digital input to the DAC.

Abstract: A digital to analog converter (DAC) includes: first and second nodes; a first switching device; a second switching device; and a switch control module. The switch control module selectively configures the first and second switching devices such that: in a first configuration, the first switching device connects a first current to the first node and the second switching device connects a second current to the second node; in a second configuration, the first switching device connects the first current to the second node and the second switching device connects the second current to the first node; and in a third configuration, the first and second switching devices disconnect the first current and the second current from the first and second nodes.

Abstract: The present invention discloses a DAC circuit and a weight error estimation/calibration method thereof. In the method, an output switching circuit dynamically selects several conversion cells (at least containing know weight conversion cells (KWCC)) as a reference conversion cell group (RCCG) from all conversion cells, and dynamically selects at least one unknown weight conversion cell (UWCC) from all UWCCs. An ADC digitalizes the difference of the output of RCCG and the sum of the outputs of the UWCCs, and inputs the result to a digital controller. The digital controller controls the input of the RCCG according to the output of the ADC to make the output of the RCCG approximate the output of the UWCC. The digital controller uses the outputs of the ADC to work out the actual weights of the UWCCs and stores the actual weights in a calibration memory.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: An example digital-to-analog converter includes a reference scaling circuit receiving a first reference current and generating a second reference current. A first plurality of current sources is coupled to a summing node with a current of a first one of the first plurality of current sources proportional to the first reference current. A current of a second one of the first plurality of current sources is substantially equal to twice the current of the first one of the first plurality of current sources. A second plurality of current sources is coupled to the summing node. A current of a first one of the second plurality of current sources is proportional to the second reference current. A current of a second one of the second plurality of current sources is substantially equal to twice the current of the first one of the second plurality of current sources.

Abstract: An apparatus and method for digital-to-analog conversion. A digital-to-analog converter includes a sampler for resampling a digital signal and a DAC array. The DAC array includes a sequencer, a unit element activator, and an array of one-bit DACs (unit elements). The unit elements are activated in a cyclical sequence, based on the resampled digital signal. Unit elements in the sequence may be skipped, based on a disruption probability. The disruption probability may be determined randomly, or pseudo-randomly. Output signals of the unit elements are summed or averaged to form an analog signal. The converter may include a filter to filter the analog signal.

Abstract: Provided first and second reference voltage set wherein the first reference voltage set includes a part or all of reference voltages of the second reference voltage set, and a decoder including first and second sub-decoder sections that select Q reference voltages from first and second reference voltage sets according to upper bits of the input digital signal and transfer the so selected reference voltages to the first to Qth nodes, and third and fourth sub-decoder sections that select first and second voltages from the Q reference voltages transferred to the first to Qth nodes according to lower bits of the input digital signal and transfer the so selected voltages to the first to Pth nodes. The first and third sub-decoder sections are made up of first conductivity type transistors, while the second and fourth sub-decoder sections are made up of second conductivity type transistors.

Abstract: An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.

Abstract: Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.

Abstract: A digital-to-analog converter (DAC) includes, in a segment of the DAC, a first switch and a second switch. The first switch includes a first pair of transistors having a first set of inputs and has a first output connected to an output of the DAC. The second switch includes second and third pairs of transistors having second and third sets of inputs, respectively, and has a second output that is connected to the output of the DAC. A driver module generates control signals to drive the first, second, and third sets of inputs based on data received by the DAC for conversion from digital to analog format at a conversion rate determined by a clock. The control signals toggle one of the first and second switches during each cycle of the clock.

Abstract: Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal.

Abstract: A digital to analog converter and a method for controlling a current source array in a digital to analog converter relate to the field of electronics technologies, and are used to reduce a system error. The digital to analog converter includes: a decoding module, a switch array, and a current source array, where the decoding module is configured to generate a 2n?1-bit first temperature code by using high n bits of an input 2n-bit binary digital signal, generate a 2n?1-bit second temperature code by using low n bits of the 2n-bit binary digital signal, and control, by using the 2n?1-bit first temperature code and the 2n?1-bit second temperature code, a working sequence of 2n×2n?1 unit switches.

Abstract: An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.

Abstract: Hybrid digital-to-analog converter and method thereof are provided. The hybrid digital-to-analog converter (DAC) includes a data processor, at least one first type DAC, at least one second type DAC, and an output circuit. The data processor processes an input digital signal to output at least one of first and second digital signals which are related to a higher bit portion and a lower bit portion of the input digital signal, respectively. If the data processor outputs the first digital signal to the first type DAC, the first type DAC converts the first digital signal. The at least one second type DAC receives and converts the second digital signal outputted from the data processor. The output circuit receives at least one output signal of the first and the second type DACs to output an output analog signal.

Abstract: An interpolative digital-to-analog (D/A) converter is adapted to convert a N-bit digital signal into an analog signal, where N is a positive integer greater than 1. The interpolative D/A converter includes a router unit that outputs first and second router voltages based on the first and second bits of the digital signal, and an interpolation unit that receives the first and second router voltages from the router unit, and that performs interpolation operation on the first and second router voltages according to the first bit of the digital signal, so as to generate the analog signal having a voltage magnitude ranging from the first router voltage to the second router voltage.

Abstract: Apparatus implementing a monotonic output digital to analog converter (DAC). A high resolution monotonic DAC may be built from a lower resolution DAC using weighting functions that combine the outputs of the lower resolution DAC such that monotonicity is maintained across major carry transitions. The lower resolution DAC should have a true output and a complementary output with a half LSB bias in the output. An extended resolution DAC may be built of; cascaded low resolution DACs; a low resolution DAC in a recursive arrangement with an intermediate storage of its output; or a low resolution DAC with weighting functions that adjust at each of several major carry transition.

Abstract: An analog to digital converter generating a number of corresponding voltages in response to a number of values of a grey level is provided. The analog to digital converter includes a decoder and an operational amplifier. The decoder provides first to third output voltages having the same level when w most significant bits (MSBs) of the grey level correspond to the same value, provides first and second intermediate voltages in response to the x MSBs next to the w MSBs when the w MSBs correspond to different values, and selectively has the first to the third output voltages equal to one of the first and the second intermediate voltages. The operational amplifier obtains a pixel voltage by interpolating the first to the third output voltages, wherein the sum of w and x is smaller than or equal to the bit number of the gray level.

Abstract: A technique includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The technique includes generating the plurality of control signals based on the digital code, a random digital code having a number of bits based on a feedback signal, and an indicator of a second sequence of unit elements of the plurality of unit elements enabled in response to a prior digital code.

Abstract: There is provided a digital-to-analog converter including: a mirror circuit including a first transistor to copy a reference current at a predetermined mirror ratio, and a second transistor cascade coupled with the first transistor; and an analog switch coupled with a gate of the second transistor, the analog switch being configured to be controlled, by a digital signal input from outside, so as to be turned on or off.

Abstract: A differential resistor-based digital-to-analog converter (RDAC) can include a positive digital-to-analog converter (PDAC) stage and a negative digital-to-analog converter (NDAC) stage. A first network of resistors of the PDAC stage can be electrically coupled to a second network of resistors of the NDAC stage utilizing an intermediary network of resistors. Further, a differential receiver can include a first input and a second input. The first input can be electrically coupled to a first resistor of the intermediary network of resistors, and the second input can be electrically coupled to a second resistor of the intermediary network of resistors. Furthermore, a portion of the first network of resistors can be electrically coupled to a positive output of the RDAC, and another portion of the second network of resistors can be electrically coupled to a negative output of the RDAC.

Abstract: An N bit sub-binary radix digital-to analog converter (DAC) includes a radix conversion module that converts an m bit digital input signal to an N bit sub-radix DAC code. A ladder module having NL bits has a plurality of first circuit elements corresponding to first respective bits of the N bit sub-radix DAC code. A segment module having NS bits has at least one second circuit element corresponding to second respective bits of the N bit sub-radix DAC code. N>m, and N is the sum of NL and NS.

Abstract: Embodiments of a digital-to-analog conversion system that utilizes a specialized clock signal to reshape an analog impulse response of a digital-to-analog converter (DAC) are disclosed. Preferably, a shape of the specialized clock signal is such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner. In one embodiment, the digital-to-analog conversion system includes a DAC that converts a digital input signal into an analog output signal. A specialized clock signal is applied to the analog output signal of the DAC such that an analog impulse response of the DAC is reshaped according to a shape of the specialized clock signal, thereby providing a modified analog output signal. The specialized clock signal reshapes the analog impulse response of the DAC such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner.

Abstract: A system and method for testing digital to analog converters (DAC) in a serial interface having a comparator to receive an input signal and a local offset signal is disclosed. A first DAC selectably provides one of a global offset to the input signal during a normal mode of operation and a first test signal to the comparator during a test mode of operation. A second DAC selectably provides one of the local offset signals to the comparator during the normal mode of operation and a second test signal to the comparator during the test mode of operation. A test module may cause the first DAC to determine a first test signal to provide to the local offset input of the comparator and may cause the second DAC to incrementally change a test signal provided to the comparator.

Abstract: A resistor string type D/A converter includes a higher-order decoder to which a digital signal is input, a higher-order resistor string in which a plurality of resistors and a plurality of voltage drawing points are alternately connected between a first reference voltage and a second reference voltage, the higher-order resistor string being configured to output a plurality of first voltages, each from a respective one of the plurality of voltage drawing points, a plurality of first higher-order switches connected to the plurality of voltage drawing points in a one-to-one configuration, conductive states of the first higher-order switches being controlled based on the digital signal, and a conversion unit that outputs a second voltage based on the plurality of the first voltages supplied through the plurality of first higher-order switches. The higher-order decoder brings two first higher-order switches into conduction based on the digital signal.

Abstract: A system and method for generating an analog signal is disclosed. In one embodiment, system includes a first-in, first-out (FIFO) buffer configured to receive and store a plurality of digital values written to the FIFO buffer. The system further includes a digital-to-analog converter (DAC) coupled to read the digital values from the FIFO buffer and configured to convert the digital values to an analog signal. The FIFO buffer is configured to operate in a first mode in which writes to the FIFO buffer are inhibited and current digital values stored in the FIFO buffer are provided to the DAC in a repeating sequence.

Abstract: Correcting phase error in a two-channel TIADC system in a manner that is independent of the Nyquist zone(s) occupied by the input signal. In the preferred approach this is done using the gradient of a phase error estimate. The gradient may be determined from a simplified expression of linear regression; the direction of the adaptation is then controlled by the sign of the gradient. The adaptive algorithm converges to the optimal value regardless of the Nyquist zone occupied by the input signal.

Abstract: A DA conversion apparatus comprising a DA converting section that includes a plurality of analog elements; and a control section that generates first shift data and second shift data by shifting the input digital data by respective shift amounts of M bits and N bits, and controls the analog elements based on the first shift data and the second shift data, wherein the control section changes a control state for each of the common analog elements according to the bit shift amounts M and N in the control section, between at least two control states including a control state in which the common analog element is controlled according to higher-order bits of the first shift data and a control state in which the common analog element is controlled according higher-order bits of the second shift data.

Abstract: An apparatus implements analog-to-digital conversion with released requirement on the reference settling errors and improved immunity to the noise originated from the power supply, ground and the positive and negative references. It includes a comparator comparing the specified reference levels with the analog input, multi DAC sub-circuits with separate non-binary search schemes applied to and a digital control logic controlling the reference search process. No cross-talk occurs among the different non-binary search algorithms. Each redundancy scheme is localized in a respective DAC sub-circuit and covers the reference levels only in the current DAC. The non-binary search algorithms are fulfilled in the digital domain and trade the non-binary search step sizes with the number of the search steps to introduce redundancy to the reference levels.

Abstract: Embodiments of the present invention may provide string DAC architecture with multiple stages for efficient resolution extension. A first stage may include an impedance string (e.g., resistor string). A second stage may include a switch network with each switch having more than two states (impedance values). A third stage may include a string DAC with an impedance string with a set of corresponding switches. In multi-channel embodiments, multiple second and third stages may be provided for each channel while sharing the same first stage (i.e., impedance string). Each second stage switch networks may be controlled based on the relationship between the different channels such as MSB values. Thus, the second stage switch networks may provide different impedance values to compensate for loading effects in multi-channel, multi-stage string DAC designs.

Abstract: An analog to digital converter generating a number of corresponding voltages in response to a number of values of a grey level is provided. The analog to digital converter includes a decoder and an operational amplifier. The decoder provides first to third output voltages having the same level when w most significant bits (MSBs) of the grey level correspond to the same value, provides first and second intermediate voltages in response to the x MSBs next to the w MSBs when the w MSBs correspond to different values, and selectively has the first to the third output voltages equal to one of the first and the second intermediate voltages. The operational amplifier obtains a pixel voltage by interpolating the first to the third output voltages, wherein the sum of w and x is smaller than or equal to the bit number of the gray level.

Abstract: Dual digital to analog converters (DACs) with codeword parsing. With respect to a codeword that is provided to a DAC, a processing module (e.g., a rollover processor) operates to divide, partition, etc. the codeword into different respective sub-codewords as may be provided to two or more DAC's. Adaptation with respect to differently generated sub-codewords with respect to different respective codewords may be made in terms of any one or more of a variety of characteristics, including sub-codeword width (e.g., the number of bits included within a sub-codeword), quantization steps, etc. Moreover, such adaptation may be in consideration of any one or more local and/or remote operating characteristics of one or more devices, communication links, etc. within a communication system or network. Different respective sub-codewords undergo processing by different respective DAC's in generating respective analog signals for combination in generating a final or output analog signal.

Abstract: A dual resistor ladder DAC includes a coarse ladder including a plurality of coarse ladder resistors and a fine ladder including a plurality of MOS transistors coupled between first and second conductors. A first group of parallel-connected bit-shifting transistors is coupled between the first and third conductors. A second group of parallel-connected MOS bit-shifting transistors is coupled between the third and top conductors. A third group of parallel-connected bit-shifting transistors is coupled between bottom and fourth conductors. A fourth group of parallel-connected bit-shifting transistors is coupled between the second and fourth conductors. Parallel-connected bit-shifting transistors are turned either on or off in response to a plurality of bit-switching bits of a binary number to be converted. One of the bottom, first, second, third, and top conductors is coupled to a DAC output conductor in response to the plurality of bit-switching bits.

Abstract: A method and device for digital filtering of a digital signal in a radio frequency (RF) device front end are disclosed. In one embodiment, 2M+1 groups of N digital-to-analog converters (DAC) are grouped to emulate a (2M+1)*N tap finite impulse response (FIR) filter. Each DAC in a group receives a clock that differs in phase from the clocks of the other DACs in the group. The filter is implemented to suppress image spectra of the digital signal without increasing a clock rate by which the signal is sampled.

Abstract: A system and method for converting a digital signal to an analog signal is provided. The present disclosure provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. In accordance with an embodiment, a method comprises receiving portions of a digital signal by a plurality of sub-DACs; converting the portions of the digital signal to a corresponding analog signal by the plurality of sub-DACs; biasing one or more of the plurality of sub-DACs; and calibrating the portions of a digital signal by one or more calibration elements.

Abstract: An embodiment of the present invention provides a digital-to-analog converter including: a primary modulator; a secondary modulator, connected to the primary modulator; a delay unit, connected to the primary modulator; a subtractor, connected to the delay unit and the secondary modulator separately; a first processing module, configured to perform decoding, dynamic matching, and digital-to-analog conversion in sequence on a B-bit digital signal output by the secondary modulator, so as to obtain a first analog signal; a second processing module, configured to perform decoding, dynamic matching, and digital-to-analog conversion in sequence on an (N?B+1) -bit quantization noise signal output by the subtractor, so as to obtain an analog noise signal; and an adder, connected to the first processing module and the second processing module separately, and configured to add the first analog signal and the analog noise signal, so as to obtain and output a second analog signal.

Abstract: A digital-to-analog converter includes a clock driver, a first decoder, a second decoder, a current source matrix, a pseudo random mode generator and at least one multiplexer. The first decoder and the second decoder are coupled to the clock driver. The current source matrix is coupled to the first decoder, and the pseudo random mode generator is used to randomly output a set of selecting signals. Each multiplexer of the at least one multiplexer includes a plurality of input ends coupled to a plurality of output ends of the second decoder, an output end coupled to the current source matrix, and a select end coupled to the pseudo random mode generator for controlling the output end to output a bit signal inputted from the input ends of the multiplexer according to one selecting signal of the set of selecting signals.

Abstract: A system includes an NL bit digital to analog converter (DAC) ladder module having NL ladder resistors connected in parallel, NL series resistors connected in series between the NL ladder resistors, and a plurality of switches. NL is an integer greater than one. Adjacent pairs of the plurality of switches are connected in series with respective ones of the ladder resistors. On resistances of each of the plurality of switches are approximately equal. A switch control module provides a plurality of switch control signals to respective ones of the plurality of switches.

Abstract: Rollover operative digital to analog converter (DAC). With respect to a codeword that is provided to a DAC, a processing module (e.g., a rollover processor) operates to compare the codeword to threshold(s) in accordance with adaptively partitioning the codeword into one or more sub-codewords when the codeword has a magnitude greater than at least one of the thresholds. In instances that the codeword is less than a threshold, the codeword may be provided directly to a DAC for use in generating a first analog signal. However, if the codeword is a larger than a threshold, then that portion of the codeword which is greater than the threshold may be provided to an alternative component such as one or more auxiliary or additional DACs, one or more other circuitry components, etc. in accordance with generating at least one additional analog signal to be combined with the first analog signal.

Abstract: A digital-to-analog converter (DAC) implements a hybrid conversion architecture where the input digital data is oversampled and a flash converter is used to convert the M most significant bits (MSBs) of the oversampled data while a sigma-delta (?-?) converter is used to convert the remaining least significant bits (LSBs) of the oversampled data. In one embodiment, a merged flash converter is used to convert the M MSBs and the digital bit stream generated by the sigma-delta converter.

Abstract: A DAC for converting a sequence of digital words into a corresponding analog signal. The DAC includes: a thermometer code generator fed by the sequence of digital words for providing N parallel outputs, each one of the outputs having one of two discrete levels; and an amplifier section having a plurality of N amplifiers, each one of the N amplifiers being fed by a different one of the M outputs. Each one of the amplifiers is driven into saturation in response to one of the two discrete levels or pinched-off in response to the other one of the two discrete levels. A combiner sums outputs of the N amplifiers producing a sequence of analog signals having levels related to the decimal values of the sequence of the digital words. An interconnection network interleaves connections between the thermometer code generator and the plurality of amplifier sections.

Abstract: Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state.

Abstract: An organic electroluminescence display capable of reducing a size of a data driving unit by decreasing an area of a D/A converter, and a driving circuit thereof. The data driving unit includes a first decoder to generate a first selection signal to correspond to a data signal; a first switch unit to receive first voltages and second voltages and to select one of the first voltages or the second voltages to correspond to the data signal; a second switch unit to select first and second reference voltages from the selected first or second voltages in response to the first selection signal; a second decoder to generate a second selection signal to correspond to the data signal; and a grey level voltage generating unit to receive and distribute the first and second reference voltages, selected by the switch units, to generate grey level voltages and to select and output one grey level voltage to correspond to the second selection signal.

Abstract: A temperature dependence adjustable operational amplifier circuit which suppresses a change in a gain caused by a change in an input voltage is provided. In an operational amplifier including a first input terminal and an output terminal, an operational amplifier having an inverting input terminal and a non-inverting input terminal, an input resistance circuit, and a feedback resistance circuit, each of the input and feedback resistor circuits has a resistor and a trimming resistor, which are different in temperature coefficient from each other, connected in series with each other, and a source-drain path of a MOS transistor included in the trimming resistor circuit is disposed between resistance and an inverting input terminal, and a substrate potential thereof is set to a potential of the inverting input terminal of the operational amplifier.