Abstract: Methods, systems, and computer program products to combine multiple telemetry data signals to generate a single higher resolution signal. In embodiments, the method includes: modulating a sampling of telemetry data by at least two network devices; receiving telemetry data from the at least two network devices; combining the received telemetry data; and determining a status of the network and/or network devices based on a processing of the combined telemetry data.

Abstract: System and methods for implementing a multiply and accumulate (MAC) operation are described. In an example, a device can multiply an input digital signal with an input current to generate a current signal. The device can further divide the current signal into a plurality of currents. The device can further sample the plurality of currents sequentially using the same clock frequency. The device can further combine the plurality of sampled currents to generate an output current signal.

Abstract: A signal generator includes a processing unit. The signal generator is configured to generate at least one periodic output signal. The output signal comprises a triangular-waveform signal. A frequency and an amplitude of the output signal are adjustable. The signal generator is configured to receive an input parameter. The input parameter comprises at least one piece of information about a setpoint amplitude and a setpoint frequency of the output signal. The processing unit is configured to determine a signal direction of the output signal. The processing unit is configured to determine a step size. The processing unit is configured to apply the step size to an actual amplitude based on the signal direction for a number of clock cycles. The number of clock cycles is dependent on the setpoint frequency of the output signal.

Abstract: An aspect includes a direct digital synthesis system including a waveform generator with a waveform memory operable to store a plurality of waveform vectors and output a selected waveform vector. The direct digital synthesis system also includes a digital-to-analog converter operable to convert the selected waveform vector from a digital value to an analog signal responsive to a reference clock. The direct digital synthesis system further includes a controller operable to maintain phase continuity of the analog signal when an output of the analog signal is interrupted and restored.

Abstract: An apparatus comprises a wavefront muxing processor receiving first and second input signals to generate first and second output signals on first and second communication channels, respectively, the first and second output signals being at a common frequency slot and having relative differential amplitude and phase delays; and an amplitude and phase adjustment element located at one of the first and second communication channels to adjust the relative differential amplitude and phase delays using an adjustment amount to reduce interference in the first and second communication channels. The first output signal is a weighted sum of the first input signal and the second input signal that is phase shifted by a second phase shift. The second output signal is a weighted sum of the second input signal and the first input signal that is phase shifted by a first phase shift. The two output signals are transmitted to a transponder.

Abstract: A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.

Abstract: The present invention relates to a method for calibrating a receiver device or a stimulus-response system comprising a receiver device. The method comprises the steps of generating at least one tone with a repeatable and known phase value, said at least one tone being stepped in frequency to cover a given set of calibration tones, and applying the at least one tone to the receiver device or to the stimulus-response system, generating a reference signal, which is phase-coherent with the at least one tone, to measure in a phase-coherent way with the receiver device or with the stimulus-response system the at least one tone, measuring at least the phase of the at least one tone using the receiver device or the stimulus-response system, determining at least phase-related information for calibration coefficients at the given set of calibration tones by calculating a phase deviation of the measured phase from the known phase value of the at least one tone.

Abstract: A phase accumulator style circuit generates an output stream of pulses. The density of the pulse stream is proportional to the input data value relative to the maximum value supported by the bit width of an adder. The output pulse density is representative of the desired output voltage. The pulse stream may be filtered with a resistor-capacitor (RC) low pass filter to yield an analog voltage. Faster clock rates support the use of smaller output filters that reduce circuit cost. This circuit provides triangle wave generation wherein the DAC output ramps up and down at a user specified rate (slope) between user specified maximum and minimum amplitude values. The up and down triangle wave ramp rates (up and down slopes) may be different and independent or the same.

Abstract: An asymmetric hysteretic controller comprises an analog comparator coupled with a fast slew rate DAC, or a digital comparator coupled with an ADC plus some digital control logic. The comparator, analog or digital, operates as a sequential windowed comparator having high and low limits. The sense parameter is compared to a high or a low limit and when the sense parameter reaches the selected high or low limit, the controlled device is turned off or on, respectively. When the hysteretic controller state comparison reversal occurs: (a) the comparator output may be blanked by the control logic, (b) the comparator polarity may be reversed by the control logic, (c) the control logic may command the other process limit to be selected for comparison with the sense parameter, and (d) then the comparator output may be re-enabled.

Abstract: According to an embodiment, a power supply noise cancelling circuit includes a generator, a first multiplier, a subtractor and a digital-to-analog converter. The generator generates a sine wave signal. The first multiplier multiplies a digital input signal by a digital signal based on the sine wave signal to generate a first digital product signal. The subtractor subtracts a digital signal based on the first digital product signal from the digital input signal to generate a digital difference signal. The digital-to-analog converter performs a digital-to-analog conversion on the digital difference signal to obtain an analog output signal.

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. This slope compensation function may be provided by a digital slope compensation generator and a pulse density modulated digital-to-analog converter (PDM DAC) having a selectable response mode low pass filter.

Abstract: A D/A converter according to the present invention includes a wave-form data-array memory means for memorizing a wave-form data array configured of a plurality of digital values, a wave-form output-format data memory means for memorizing wave-form output-format data designating a wave-form output period, a digital value output means for sequentially reading out the digital values for each wave-form output period from the wave-form data-array memory means and outputting the values, and a D/A conversion means for converting the digital values outputted from the digital value output means into analog-data values.

Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/?1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.

Abstract: Input codes are sequenced at a lower-resolution linear DAC and the output is converted to a linear current waveform. A first of two interconnected analog current multipliers multiplies the linear current by itself and by the inverse of a first constant current source to create a quadratic current output. A second current multiplier multiplies the quadratic output current by the linear current and by the inverse of a second constant current source to generate a cubic current output. The quadratic and cubic currents are subtracted from the linear current to generate an approximation of the first 180 degrees of a sine wave current. Alternate (pi to 2*pi) positive-going one-half sine waves may be polarity reversed to create a complete positive-going and negative-going sine-shaped electrical current of higher resolution than is available from a sine DAC of resolution equivalent to that of the lower-resolution linear DAC.

Abstract: An integrated circuit device can include a plurality of analog blocks, including a plurality of programmable analog blocks configurable to provide different analog functions in response to configuration data, at least one programmable analog block including a programmable analog routing coupled to a plurality of external connections to the integrated circuit device; and a plurality of programmable digital blocks, at least one programmable digital block configurable into an analog block control circuit that configures the programmable analog routing.

Abstract: An RF-DAC cell is configured to generate an RF output signal based on a baseband signal, a first signal and a second signal. The first signal has a first duty cycle and toggles between first predefined amplitude values, and the second signal has a second duty cycle smaller than the first duty cycle and toggles between second predefined amplitude values.

Abstract: This disclosure describes techniques and apparatuses for low-memory-usage arbitrary waveform representation or generation. These techniques and/or apparatuses enable representation and/or generation of arbitrary waveforms using less memory than many current techniques, thereby reducing costs or memory size. Further, in some embodiments the techniques and apparatuses generate arbitrary waveforms without using processor resources.

Abstract: An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.

Abstract: This disclosure describes techniques and apparatuses for low-memory-usage arbitrary waveform representation or generation. These techniques and/or apparatuses enable representation and/or generation of arbitrary waveforms using less memory than many current techniques, thereby reducing costs or memory size. Further, in some embodiments the techniques and apparatuses generate arbitrary waveforms without using processor resources.

Abstract: Rollover operative digital to analog converter (DAC). With respect to a codeword that is provided to a DAC, a processing module (e.g., a rollover processor) operates to compare the codeword to threshold(s) in accordance with adaptively partitioning the codeword into one or more sub-codewords when the codeword has a magnitude greater than at least one of the thresholds. In instances that the codeword is less than a threshold, the codeword may be provided directly to a DAC for use in generating a first analog signal. However, if the codeword is a larger than a threshold, then that portion of the codeword which is greater than the threshold may be provided to an alternative component such as one or more auxiliary or additional DACs, one or more other circuitry components, etc. in accordance with generating at least one additional analog signal to be combined with the first analog signal.

Abstract: A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single adder. Values stored in the ROMs may produce one component of a sinusoid signal, and each of the ROMs may be of a different size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series expansion of a sinusoid function.

Abstract: A non-linear amplifier is linearized using interpolation-based digital pre-distortion (DPD). In one embodiment, the digital input signal is interpolated to generate a higher-sample-rate signal that is then pre-distorted. The resulting higher-sample-rate pre-distorted signal is then decimated to generate a final pre-distorted digital signal that is converted into an analog pre-distorted signal by a digital-to-analog converter (DAC) before being applied to the amplifier. In a polyphase embodiment, different versions of the original input digital signal are generated, where each version is then pre-distorted using a different DPD module to generate a different intermediate pre-distorted digital signal. The intermediate pre-distorted signals are filtered and combined to generate the final pre-distorted digital signal. In both embodiments, better linearization (e.g.

Abstract: A circuit for providing audio signals to a load such as a speaker is provided that uses the speaker or headphone amplifier structure as a current to voltage converter, thereby eliminating a separate current to voltage converter from the circuit. Such a design removes one of the elements that creates noise in the circuit architecture and improves the dynamic range for the audio signal. For example, the output of a digital to analog converter is a single ended output provided to the speaker or headphone amplifier. The digital to analog converter can include a series of current sources that are summed up to provide the single ended output. Where the current sources have positive and negative current source mismatch, a feedback mechanism is employed to correct for the mismatch and reduce introduction of harmonic noise into the signal through the digital to analog converter.

Abstract: In a method for improving resolution and for correcting distortions for a sigma-delta modulator, a modulator converts an analog input signal into a secondary output digital signal sampled at a frequency fe and coded on NB bits, a second main output digital signal s?(t) is represented on NMSB bits also being available at the output. At least three processings are applied successively to the outputs, a first processing carrying out a demodulation by a frequency f0 and a decimation of factor N in an independent manner, z second processing carrying out an improvement of the resolution and a third processing carrying out a correction of the distortions. These three processings are carried out after decimation. A sigma-delta modulator implements the method.

Abstract: A digital to analog conversion apparatus includes a plurality of gain/phase adjusters configured to receive a digital signal and to output a plurality of adjusted digital input signals, a plurality of digital to analog converters coupled to respective ones of the plurality of gain/phase adjusters and configured to receive the adjusted digital input signals and to generate respective analog signals representative of the adjusted digital input signals, a plurality of phase shift elements coupled to respective ones of the plurality of digital to analog converters and configured to shift the phases of the analog signals generated by the digital to analog converters, and a combiner coupled to the outputs of the plurality of digital to analog converters and configured to combine the respective phase-shifted analog signals to form an analog output signal.

Abstract: A transmission circuit for use with an ultrasonic probe including an ultrasonic transducer is provided. The transmission circuit includes a high voltage current DAC configured to output a drive current of an ultrasonic transducer to transmit and receive ultrasound, and a waveform generator configured to output a control signal from the high voltage current DAC to the high voltage current DAC with a predetermined timing. The control signal configured to output the drive current with a desired magnitude.

Abstract: A gamma voltage generator includes an RGB common gamma voltage generation section configured to generate RGB common gamma voltages using corresponding gamma reference voltages among a plurality of gamma reference voltages; and at least two of an RG gamma voltage generation section configured to generate RG gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, an R gamma voltage generation section configured to generate R gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, a G gamma voltage generation section configured to generate G gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, and a B gamma voltage generation section configured to generate B gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages.

Abstract: There is provided a digital signal processing device capable of suppressing occurrence of an unnecessary frequency component (spurious) in performing a reduction processing of a bit number of a frequency signal made of a digital signal. A signal output section 10 outputs a frequency signal by a digital signal made of bit data and an addition section 16 adds noise data for suppressing occurrence of an unnecessary frequency component to the bit data. A reduction processing section 11 performs a predetermined processing in correspondence with whether the bit data obtained in the addition section 16 is positive or negative, and thereafter, shifts each bit of the bit data to the right by m digits set in advance (m is an integer smaller than a bit number of the bit data) and cut off an m-bit portion to reduce the number, rounding down “0” and rounding up “1” for the most significant bit of the bits having been cut off.

Abstract: A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.

Abstract: An arbitrary waveform generator converts digital waveform data stored in a memory into an analog output signal by using a digital-to-analog converter. In order to make the frequency characteristics of the output signal flat, the created digital waveform data is modified in accordance with a predetermined S-parameter of the arbitrary waveform generator, and the modified digital waveform data is stored in the memory for generating the analog signal having the compensated frequency characteristics.

Abstract: The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC), a second DAC, and a control circuit to select which DAC to use for digital-to-analog conversion of a digital signal. Concerned with the noise level produced at a given out-of-band frequency, the control circuit bases its selection of DACs, at least in part, on a frequency distance between the given out-of-band frequency and the digital signal's frequency. The control circuit, for example, may select the DAC producing the lowest noise level at that frequency distance, or, if both DACs are able to reduce noise to a level below a noise tolerance specified for the frequency distance, the DAC consuming the least power. To reduce the chip area required for the digital-to-analog conversion circuit, the first and second DACs advantageously have topologies that permit them to share common components (e.g., DAC unit elements).

Abstract: Mechanisms for providing linear relationship between temperatures and digital codes are disclosed. In one method, at a particular temperature, a circuit in the sensor provides a temperature dependent reference voltage, and a compared voltage, to a comparator. The temperature dependent reference voltage depends on temperature in complement to absolute temperature or alternatively depends on temperature in proportion to absolute temperature. The compared voltage is generated corresponding to digital analog converter (DAC) codes as inputs. Another circuit varies the DAC codes until the temperature dependent reference voltage and the compared voltage are equal so that the dependent reference voltage corresponds to a DAC code.

Abstract: The purpose is to provide a waveform generator that generates signals with a frequency lower than the minimum sampling frequency of the DAC. In the waveform generator 10, the clock generator 106 generates a clock signal 140. The frequency divider 112 divides the frequency of the clock signal 140 and generates the frequency-divided clock signal 144. The reader 118 provides an address signal at the period of frequency-divided clock signal 144 for the waveform memory 120 and reads the pattern data from the waveform memory 120 into the DAC 130. The DAC 130 converts the data provided from the waveform generator 120 at the period of clock signal 140 into an analog value and outputs a waveform of arbitrary shape.

Abstract: A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.

Abstract: Disclosed are techniques for generating a precisely controlled analog signal. In one described implementation, a semiconductor circuit is mounted on a circuit board having a power and a ground etching. The circuit has a power terminal coupled with the power etching and a ground terminal coupled with the ground etching. The circuit includes a trapezoid shaped resistive strip coupled with the power terminal and the ground terminal. Contacts are connected along one edge of the strip to provide outputs at various voltage levels. Switches having a common output are coupled with the contacts on the strip. A control circuit activates the switches so that the common output generates an analog signal.

Abstract: Systems and methods synthesize a signal from the odd harmonic frequency components of an input signal. An exemplary embodiment synthesizes a first signal with a digital to analog converter (DAC), generates a second signal from the first signal, and filters a selected one of the odd harmonic frequency components through a band pass filter to produce an output signal. The first signal is defined by a first frequency. The second signal is defined by the first frequency and includes a fundamental frequency component and plurality of odd harmonic frequency components. The output signal has a frequency substantially equal to the frequency of the selected odd harmonic frequency component.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: A distributed arbitrary waveform generator (DAWG) synthesizes the target waveform using a series of narrow pulses generated by a number of pulse generators. To achieve this, it uses an input trigger signal to control all the pulse generators, each of which generates a narrow pulse (impulses) at a specific sample time, and then all the impulses are combined to generate the output waveform. The input trigger signal is distributed to each pulse generator by a trigger distribution network. Impulses generated by pulse generators can be tuned in both pulse amplitude and width, and the spacing between them can be tuned by the trigger distribution network. Therefore the waveforms generated are completely reconfigurable.

Abstract: The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.

Abstract: An embodiment of the present invention is a technique to design a DAC. A double-summed-to-zero (DSTZ) graph is created having a plurality of nodes linked by a plurality of directed branches. The DSTZ graph represents a finite state machine (FSM) that generates a sequence for a switching block used in a mismatch-shaping digital-to-analog converter (DAC). Each of the plurality of nodes represents a state in the FSM. The DSTZ graph has a total work function and a total potential energy summing to zero for a cycle traversal. A switching sequence is generated starting from a reference node in the plurality of nodes in response to an input sequence. The reference node has a zero potential energy.

Abstract: A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing the address after the trigger signal. A hexadecimal counter counts a clock that is faster than the divided clock as the counted number circulates every one period of the divided clock . A trigger information latch latches the counted number of the counter when the trigger signal arrives and provides it to a MUX. The MUX selects data in a pair of the parallel data provided at first and second inputs I1 and I2 to produce rearranged parallel data bits according to the latched counted number. A parallel to serial converter receives the rearranged parallel data to convert it to serial data according to the clock.

Abstract: Clock signal generation circuitry includes input circuitry for receiving a frequency control input signal and a clock signal and generating a memory address therefrom, a memory for storing digital data indexed by the memory address and representing real and imaginary parts of a complex digital waveform, and digital to analog conversion circuitry. The digital to analog conversion circuitry includes real-part digital to analog conversion circuitry for converting digital data retrieved from the memory and representing the real part of the complex waveform into a real-part analog signal and imaginary-part digital to analog conversion circuitry for converting digital data retrieved from the memory and representing the imaginary part of the complex waveform into an imaginary-part analog signal.

Abstract: The present invention relates to multi-bit to pulse width modulated signal conversion, with extensions to digital-to-analog conversion. In particular, it has application to conversion of pulse code modulated signals, such as used in CDs and DVDs, to audio output.

Abstract: A digital-to-analog converter supporting high speed operation is defined. The converter includes a plurality of sampler circuits in electrical communication with a digital signal source and a summation circuit in electrical communication with the plurality of sampler circuits. A sampler circuit of the plurality of sampler circuits is adapted to sample a bit of a plurality of bits from the digital signal source with a half-sinusoidal signal forming a sampled signal. The sampler may include a plurality of diodes and a sinusoidal signal source. The sinusoidal signal source toggles the plurality of diodes on and off thereby forming the sampled signal at a sampler output port. The summation circuit is adapted to combine the sampled signal from each of the plurality of sampler circuits to form an analog signal portion representative of the plurality of bits. Exemplary summation circuits include an R-2R resistance ladder and a Wilkinson power combiner.

Abstract: Systems and methods regarding the restoration of serialized data to parallel data with a low speed reference signal are provided. In exemplary embodiments, a phased lock loop receives a reference clock signal from a data source and generates a reference high speed clock signal based on the reference clock signal. A dynamic link library clock and data recovery module reads and writes data flows contained within serialized data onto parallel data paths at a modified high speed clock signal based on the reference high speed clock signal.

Abstract: An RF carrier generator comprises a circuit for sequentially counting as a function of a randomized offset and time interval, and a memory coupled to the sequential counting circuit. The memory stores samples of a desired Sigma-Delta modulator sequence bit stream. Responsive to an output of the sequential counting circuit, the memory sequentially outputs a single-bit output bit stream of a series of partial sequences of the desired Sigma-Delta modulator sequence bit stream. A method is also disclosed.

Abstract: A circuit for implementing tracking supply alternating current (“AC”) regeneration is described. In one embodiment, the circuit comprises a line synchronization device for converting an incoming AC signal to a square wave, wherein the square wave is precisely in phase with the incoming AC signal; a processor for processing the square wave to synthesize a sine wave therefrom; a digital to audio converter (“DAC”) to convert the synthesized sine wave into an analog signal, wherein the analog signal is precisely in phase with the incoming AC signal; and an amplifier for amplifying the audio signal to a desired voltage level for driving a load.

Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group.

Abstract: According to an exemplary embodiment, a circuit includes a power amplifier configured to generate an RF output signal. The circuit further includes a pulse shaping circuit coupled to the power amplifier, where the pulse shaping circuit is configured to receive a digital input signal and generate an analog output signal at a first node, and where the analog output signal controls the RF output signal. The analog output signal has a ramp-up portion having a first shape, where the first shape corresponds to a piece-wise-linear approximation of a sinusoid. The analog output signal also has a ramp-down portion having a second shape, where the second shape corresponds to the piece-wise-linear approximation of a sinusoid. The pulse shaping circuit does not require a clock reference to generate the analog output signal.