Using Charge Coupled Devices Or Switched Capacitances Patents (Class 341/150)
  • Patent number: 8928506
    Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: January 6, 2015
    Assignee: MaxLinear, Inc.
    Inventors: Raja Pullela, Curtis Ling
  • Publication number: 20140347203
    Abstract: Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Inventors: Franz Kuttner, Michael Fulde
  • Patent number: 8884797
    Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chow Peng, Jui-Cheng Huang, Ching-Ho Chang, Nang Ping Tu
  • Publication number: 20140328429
    Abstract: One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and a plurality of unit cells arranged in rows and columns. A row decoder and a column decoder provide respective control signals to respective rows and respective columns to selectively couple a number of the unit cells to an output of the DAC. The number of unit cells which are coupled to the output by the control signals is dependent on the multi-bit digital input signal. At least one of the control signals is modulated based on a local oscillator signal.
    Type: Application
    Filed: July 21, 2014
    Publication date: November 6, 2014
    Inventors: Franz Kuttner, Michael Fulde
  • Patent number: 8872691
    Abstract: A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 28, 2014
    Assignee: Keysight Technologies, Inc.
    Inventor: Dusan Stepanovic
  • Patent number: 8872686
    Abstract: The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Yu Chou, Wei Lun Tao, Shang-Fu Yeh, Yi-Che Chen, Calvin Yi-Ping Chao
  • Patent number: 8860600
    Abstract: Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: October 14, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Jun Yang
  • Patent number: 8860597
    Abstract: Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: October 14, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Matthew D. Sienko
  • Patent number: 8836559
    Abstract: Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 16, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Franz Kuttner, Michael Fulde
  • Publication number: 20140253354
    Abstract: A digital-to analog converter (DAC) of the charge transfer type can be used in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC. The DAC has a first capacitor switch unit receiving a reference voltage and a first digital input value to transfer first output charges, at least one second capacitor switch unit receiving the reference voltage and a second digital input value, wherein an output of the second capacitor switch unit is coupled in parallel with an output of the first capacitor switch unit to generate a sum of first and second transferred output charges; and a sequencer controlling switches of the first and second capacitor switch units wherein switching sequences according to individual first and second digital input values are provided for every DAC input value to generate the N output levels.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 11, 2014
    Inventor: Vincent Quiquempoix
  • Publication number: 20140253355
    Abstract: A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+1 output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 11, 2014
    Inventor: Vincent Quiquempoix
  • Patent number: 8830100
    Abstract: A digital-analog converter circuit includes sampling capacitive elements (111, 112, . . . , 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, . . . , DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, . . . , 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, . . . , 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: September 9, 2014
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Seiko Nakamoto, Junya Nakanishi
  • Patent number: 8830101
    Abstract: According to some embodiments, a digital to analog converter comprises an array of input data streams. An array of differential MOS switches are all biased by a common tail current source. A data stream combiner combines and selects at each clock cycle the correct bit. Only one transistor from the switches conducts current at any time. The duration during which a switch conducts current is independent upon the fronts of the bits from the input data streams, thus rendering the switching code independent.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: September 9, 2014
    Inventor: Ion E. Opris
  • Patent number: 8803721
    Abstract: A multiplying analog-to-digital converter (“MDAC”) that reduces the power consumption of the MDAC by at least 2.3 times by improving the feedback factor. The amplifier may include a feed forward approach in which the input capacitor (also referred to as “sampling capacitor”) is buffered by a common gate amplifier to improve bandwidth by removing input and parasitic capacitance terms from the global feedback loss. THe amplifier may also use an alternate form of local compensation, for example, cascode compensation. The amplifier may also further include an alternate way to reduce parasitic capacitance with a buffer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 12, 2014
    Assignee: Analog Devices, Inc.
    Inventors: William T. Boles, Michael R. Elliott
  • Patent number: 8773297
    Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal. The hybrid finite impulse response filter/digital to analog converter uses N-taps implemented digitally and N-tap weights implemented in analog using switched capacitors.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Martin Kinyua, Eric Soenen
  • Publication number: 20140184432
    Abstract: A method for evaluating capacitor weighting of an analog-to-digital (ADC) is provided. An equivalent weighting value of each composed capacitor in each sub-capacitor-array may be obtained by adding the switch device to the ADC which enables each sub-capacitor-array in a digital-to-analog (DAC) to be measured by each other. The ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and successive approximation result of each input signal.
    Type: Application
    Filed: March 18, 2013
    Publication date: July 3, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Xuan-Lun Huang, Hao-Jen Lin, Jiun-Lang Huang
  • Patent number: 8766839
    Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 1, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Seetharaman Janakiraman, Minkle Eldho Paul
  • Patent number: 8742964
    Abstract: An apparatus includes a capacitance-to-voltage converter circuit configured to be electrically coupled to a micro-electromechanical system (MEMS) sensor circuit. The capacitance-to-voltage converter circuit includes a differential chopping circuit path configured to receive a differential MEMS sensor output signal and invert a polarity of the differential chopping circuit path, and a differential sigma-delta analog to digital converter (ADC) circuit configured to sample the differential MEMS sensor output signal and provide a digital signal representative of a change in capacitance of the MEMS sensor.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: June 3, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jonathan Adam Kleks, Ion Opris, Justin Seng
  • Publication number: 20140146913
    Abstract: Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Inventors: Franz Kuttner, Michael Fulde
  • Publication number: 20140146914
    Abstract: One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and a plurality of cells arranged in rows and columns. Each cell includes a current source. A row decoder and a column decoder provide respective control signals to respective rows and respective columns to selectively couple a number of the current sources to an output of the DAC. The number of current sources which are coupled to the output by the control signals is dependent on the multi-bit digital input signal. At least one of the control signals is modulated based on a local oscillator signal.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Inventors: Franz Kuttner, Michael Fulde
  • Patent number: 8736478
    Abstract: A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 27, 2014
    Assignee: LSI Corporation
    Inventors: James A. Bailey, Abhishek Duggal
  • Patent number: 8736476
    Abstract: A technique includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The technique includes generating the plurality of control signals based on the digital code, a random digital code having a number of bits based on a feedback signal, and an indicator of a second sequence of unit elements of the plurality of unit elements enabled in response to a prior digital code.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: May 27, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Xue-Mei Gong, Douglas F. Patorello
  • Publication number: 20140097977
    Abstract: A digital-analog converter circuit includes sampling capacitive elements (111, 112, . . . , 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, . . . , DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, . . . , 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, . . . , 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).
    Type: Application
    Filed: October 31, 2012
    Publication date: April 10, 2014
    Applicant: ASAHI KASEI MICRODEVICES CORPORATION
    Inventors: Seiko Nakamoto, Junya Nakanishi
  • Publication number: 20140070973
    Abstract: A signal mixing circuit which mixes input signal(s) and oscillation signal(s) by mixer block(s) to provide a mixed signal. Each mixer block includes a summing node and a circuit unit; the summing node is arranged to provide a sum signal by summing an input signal and an oscillation signal, and the circuit unit is arranged to alternate between a first state and a second state in response to alternating of the oscillation signal; wherein the circuit unit is arranged to provide driving contribution to the mixed signal in response to the sum signal during the first state, and to stop providing driving contribution during the second state. An associated converter, e.g., a digital-to-analog converter, is also disclosed.
    Type: Application
    Filed: March 14, 2013
    Publication date: March 13, 2014
    Applicant: MEDIATEK Inc.
    Inventors: Wei-Hao Chiu, Ang-Sheng Lin
  • Publication number: 20140062747
    Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a Class D delta-sigma pulse width modulation control loop.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Martin KINYUA, Eric SOENEN
  • Publication number: 20140062748
    Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal. The hybrid finite impulse response filter/digital to analog converter uses N-taps implemented digitally and N-tap weights implemented in analog using switched capacitors.
    Type: Application
    Filed: November 26, 2012
    Publication date: March 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Martin Kinyua, Eric Soenen
  • Patent number: 8659459
    Abstract: Provided are a capacitor digital-to-analog (DAC), an analog-to-digital converter (ADC) including the capacitor DAC, and a semiconductor device. The DAC includes at least one dummy capacitor configured to cause capacitors included in a capacitor array to have a capacitance that is an integer multiple of the capacitance of a unit capacitor.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: February 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Woo Kim, Michael Choi, Jung-Ho Lee
  • Patent number: 8653999
    Abstract: A current steering Digital-to-Analog Converter (DAC), a video adapter including a current steering DAC, and a video circuit including a current steering DAC are described. In one embodiment, a current steering DAC includes multiple DAC unit cells that are connected in parallel with each other. Each of the DAC unit cells includes three output switches connected to a current source. The three output switches are configured to form two differential pairs of switches that are placed in parallel with each other and share a negative output switch of the three output switches. The current steering DAC also includes at least one switch control circuit configured to receive digital input data and to control the three output switches of each of the DAC unit cells to generate differential analog output data based on the digital input data and a current from the current source. Other embodiments are also described.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: February 18, 2014
    Assignee: NXP B.V.
    Inventor: Rene Verlinden
  • Patent number: 8653998
    Abstract: A D/A conversion circuit includes a first D/A converting section which is connected with an output node, a first serial capacitor which is disposed between the output node and a first node, a second D/A converting section which is connected with the first node, and a control circuit. The first D/A converting section includes a first capacitor array section and a first switch array section. The second D/A converting section includes a second capacitor array section and a second switch array section. The control circuit performs a switch control for dynamically changing allocation of the capacitors to the respective bits of input digital data for the first switch array section of the first D/A converting section.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 18, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Hideo Haneda, Takemi Yonezawa
  • Patent number: 8619013
    Abstract: A digital-analog converter (DAC) including: a gray scale generator having a plurality of switches for generating desired gray scale voltages through charge sharing between at least two data lines; a switching signal generator for providing operation control signals for the plurality of switches of the gray scale generator; and a reference voltage generator for generating reference voltages and for providing the reference voltages to the gray scale generator. In one embodiment, the charge sharing used by the DAC is executed by a holding capacitor and a sampling capacitor, and the holding capacitor and the sampling capacitor are formed using respective parasitic capacitance components existing in the at least two data lines, thereby reducing area and power consumption over an existing R-string type of DAC.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: December 31, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Oh Kyong Kwon, Byong Deok Choi
  • Patent number: 8593320
    Abstract: A method of converting a periodic pulse width modulated input signal into a voltage output signal wherein the input signal is in an active state for a first portion of each of successive time periods and in an inactive state for a second portion of each time period. A first and second input is supplied to an integrator circuit and a first capacitor is coupled between a first output of the integrator circuit and the first input and a second capacitor is coupled between a second output and the second input of the integrator circuit during a first time period of the pulse width modulated signal. A third capacitor is coupled between a first output of the integrator circuit and the first input and a fourth capacitor is coupled between a second output of the integrator circuit and the second input during a successive second time period of the pulse width modulated signal.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: November 26, 2013
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Saul Darzy
  • Patent number: 8581769
    Abstract: A multiplying digital-to-analog converter suited to maintain impedance balancing during phases. In an embodiment, an input signal may be sampled onto nodes of impedance elements during an initial phase. In a second phase the impedance elements are directly coupled either to a non-inverting reference input or the inverting reference input of an amplifier depending on an output of a related flash ADC output. The determination as to which capacitor is to be coupled to inverting or non-inverting input nodes may be directly programmed into the MDAC using switches, such that a thermometric to binary converter is not required in an example embodiment. Thus, the number of impedance elements coupled to the non-inverting reference input or inverting reference input REFM remains constant in each cycle such that there is no need to settle the non-inverting reference input or inverting reference input to full accuracy.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: November 12, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Ashish Kumar, Chandrajit Debnath
  • Patent number: 8570205
    Abstract: An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 29, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Maher Mahmoud Sarraj, Haydar Bilhan
  • Patent number: 8552897
    Abstract: A reference circuit for use with a charge redistribution analog to digital converter, having a capacitor array, the reference circuit comprising: an input for receiving a signal; an output for supplying a reference voltage to at least one capacitor of the charge redistribution capacitor array; a storage capacitor for storing the reference voltage; a voltage modification circuit for comparing the reference voltage stored on the storage capacitor with the reference signal, and based on the comparison to supply a correction so as to reduce a difference between the reference voltage and the reference signal, the correction being applied during a correction phase; and a first switch for selectively connecting the storage capacitor to the input during an acquisition phase.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: October 8, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Christopher Peter Hurrell
  • Patent number: 8547261
    Abstract: The present invention relates to the field of mobile terminal technology and describes a calibration device for a mobile terminal and an ADC module thereof, the ADC module being disposed inside a baseband chip. The calibration device includes a bandgap voltage reference inside the mobile terminal platform for generating a reference voltage; the device further includes a circuit for connecting the bandgap voltage reference, the circuit being connected with the ADC module for providing the reference voltage generated by the bandgap voltage reference to the ADC module. The present invention uses a bandgap voltage reference inside a mobile terminal platform to provide voltage to an ADC module, which, during the ADC module calibration, does not require an external reference voltage source to perform the ADC calibration, and therefore greatly reduces calibration errors and improves calibration efficiency.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: October 1, 2013
    Assignee: Huizhou TCL Mobile Communication Co., Ltd.
    Inventor: Jianliang Gu
  • Publication number: 20130249727
    Abstract: A reference circuit for use with a charge redistribution analog to digital converter, having a capacitor array, the reference circuit comprising: an input for receiving a signal; an output for supplying a reference voltage to at least one capacitor of the charge redistribution capacitor array; a storage capacitor for storing the reference voltage; a voltage modification circuit for comparing the reference voltage stored on the storage capacitor with the reference signal, and based on the comparison to supply a correction so as to reduce a difference between the reference voltage and the reference signal, the correction being applied during a correction phase; and a first switch for selectively connecting the storage capacitor to the input during an acquisition phase.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventor: Christopher Peter HURRELL
  • Patent number: 8537041
    Abstract: A non-linear amplifier is linearized using interpolation-based digital pre-distortion (DPD). In one embodiment, the digital input signal is interpolated to generate a higher-sample-rate signal that is then pre-distorted. The resulting higher-sample-rate pre-distorted signal is then decimated to generate a final pre-distorted digital signal that is converted into an analog pre-distorted signal by a digital-to-analog converter (DAC) before being applied to the amplifier. In a polyphase embodiment, different versions of the original input digital signal are generated, where each version is then pre-distorted using a different DPD module to generate a different intermediate pre-distorted digital signal. The intermediate pre-distorted signals are filtered and combined to generate the final pre-distorted digital signal. In both embodiments, better linearization (e.g.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: September 17, 2013
    Assignee: Andrew LLC
    Inventors: Rajiv Chandrasekaran, George P. Vella-Coleiro
  • Patent number: 8537045
    Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: September 17, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Ronald Kapusta
  • Publication number: 20130234874
    Abstract: A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Applicant: LSI CORPORATION
    Inventors: James A. Bailey, Abhishek Duggal
  • Publication number: 20130222168
    Abstract: Representative implementations of devices and techniques provide digital-to-analog conversion of signals while minimizing switching related errors. Digital to analog converter (DAC) cells may be arranged to include one or more operating states in addition to binary output states, and may employ a switching technique to “dump” the DAC cell between binary outputs. Further, an array of DAC cells may include a partial set of redundant DAC cells for implementation of the switching technique.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Inventors: Martin CLARA, Daniel GRUBER, Klatzer WOLFGANG
  • Publication number: 20130214944
    Abstract: A switched-capacitor digital-to-analog converter (DAC) circuit can include first and second sets of capacitors, an amplifier, a reference signal generator and interconnecting switches. The first and second sets of capacitors can be connected to first and second analog input signals responsive to a first clock signal, and to first and second reference voltages responsive to a second clock signal and digital control signals. The amplifier can be connected to the first and second sets of capacitors in response to the second clock signal. The reference signal generator can provide to the first and second sets of capacitors, responsive to the first clock signal, a common-mode reference signal to set a common-mode voltage at inputs of the amplifier, and can include components to replicate the operation of the first and second sets of capacitors. The switched-capacitor DAC circuit can be used to implement a multiplying DAC in a pipeline analog-to-digital converter.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventor: Stephen Robert KOSIC
  • Patent number: 8514117
    Abstract: A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: August 20, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Venkatesh Srinivasan, Patrick Satarzadeh, Victoria W. Limetkai, Baher Haroun, Marco Corsi
  • Publication number: 20130183920
    Abstract: There is provided with a residual signal generating circuit in which the capacitive DA converter generates a first difference signal with respect to an input signal based on a criterion voltage, the criterion voltage being indicative of an input range of the input signal, the reference voltage generating circuit divides the criterion voltage to obtain at least one partial voltage signal, the residual signal generating section generates 2N?1 first residual signal according to a difference between the first difference signal and 2N?1?1 first reference signal, the 2N?1?1 first reference signal being 2N?1?1 partial voltage signal among said at least one partial voltage signal generated by the reference voltage generating circuit, the comparator compares the 2N?1 first residual signal with a fixed voltage to obtain 2N?1 first comparison signal each indicative of a logical value, and the decoder decodes the 2N?1 first comparison signal to obtain first data of N bits.
    Type: Application
    Filed: September 7, 2012
    Publication date: July 18, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masanori FURUTA, Hirotomo Ishii
  • Patent number: 8456342
    Abstract: A digital-to-analog converter (DAC) uses thermometer coding over a certain code range. A switch array for the certain code range is implemented into a smaller area of the integrated circuit die so as to take advantage of the lower gradient inherent in the smaller area. By implementing the certain input code range into the smaller switch array area, further improved linearity in that input code range is achieved at the expense of worse linearity in the other input code ranges, but without increasing power consumption and/or chip-area of the integrated circuit die.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: June 4, 2013
    Assignee: Microchip Technology Incorporated
    Inventors: Honglei Wu, Mengchang Doong
  • Patent number: 8456348
    Abstract: An SAR ADC capable of reducing energy consumption, including a voltage selecting circuit for configuring a capacitor circuit to form a first equivalent capacitor having a capacitance of (2m?1)C, a second equivalent capacitor having a capacitance of (2n?2m?1)C, a fourth equivalent capacitor having a capacitance of (2m?1)C, and a fifth equivalent capacitor having a capacitance of (2n?2m?1)C, wherein, the first equivalent capacitor has one terminal coupled to a reference voltage or a ground voltage, and the other terminal coupled to a positive input end of a comparator; the second equivalent capacitor is coupled between a common mode voltage and the positive input end; the fourth equivalent capacitor has one terminal coupled to the ground voltage or the reference voltage, and the other terminal coupled to a negative input end of the comparator; and the fifth equivalent capacitor is coupled between the common mode voltage and the negative input end.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: June 4, 2013
    Assignee: National Taiwan Normal University
    Inventors: Chien-Hung Kuo, Cheng-En Hsieh
  • Patent number: 8456343
    Abstract: A switched capacitor type D/A converter receives m-bit (m represents an integer) input data, and outputs an analog signal that corresponds to the input data value. Switch circuits are provided to respective bits of the input data, and are classified into two groups: a first group configured to turn on when the corresponding input data bit is 1, and to turn off when the corresponding input data bit is 0; and a second group configured to turn on when the corresponding input data bit is 0, and to turn off when the corresponding input data bit is 1. Each switch of the first and second switch groups is configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The ground voltage 0 V is applied to the lower power supply terminal of each of the first and second inverters configured to supply a gate signal to each switch.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: June 4, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Kei Nakamura
  • Patent number: 8421784
    Abstract: In one embodiment of the present invention, a display for receiving m-bit display data includes a display driver including a switched capacitor digital/analogue converter including an n-bit input, where m is not greater than n. The upper plates of the capacitors of the switched capacitor digital/analogue converter may be connected, in the zeroing phase, to one of a plurality of reference voltages. The choice of which reference voltage is connected to the upper plates of the capacitors of the switched capacitor digital/analogue converter in the zeroing phase is independent of the input n-bit digital code, and is determined by a signal internal to the display. The output voltage range from the converter in a decoding phase may be a first range in which output voltages are above and below one reference voltage or it may be a second range in which output voltages are above and below another reference voltage, depending on which reference voltage was selected in the preceding zeroing phase.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Patrick Zebedee
  • Publication number: 20130069808
    Abstract: A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N?3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 21, 2013
    Inventors: Chandrashekar A. Reddy, Yagneshwara Ramakrishna Rao Vadapalli
  • Patent number: 8400339
    Abstract: Embodiments of apparatus and methods for applying a gain to an input signal are provided. An embodiment of a switched-capacitor gain stage circuit includes an input node, an output node, an operational amplifier, a correlated-double-sampling portion, a correlated-level-shifting portion, and a switching configuration. The operational amplifier has a first amplifier input, a second amplifier input, and an amplifier output. The correlated-double-sampling portion includes a plurality of sampling capacitors arranged in parallel and selectively coupled between the input node and a central node, and an offset storage capacitor including a first terminal coupled to the first amplifier input. The correlated-level-shifting portion includes a correlated-level-shifting capacitor including a first terminal coupled to the output node.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: March 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Douglas A. Garrity, Brandt Braswell
  • Patent number: 8400382
    Abstract: A digital-to-analog converter circuit is configured to convert an m-bit digital signal into an analog signal. The circuit includes a bit voltage generator convert each bit of segmented n-bit units of the digital signal into a first voltage or a second voltage, first capacitors each configured to store the voltage for each bit output from the bit voltage generator, switches connected to the first capacitors, a second capacitor connected to the switches, an output unit configured to output the voltage stored in the second capacitor as an analog signal, and a control unit configured to control the switches, connect in parallel the first capacitors with the second capacitor, and adjust the voltage stored in the second capacitor.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: March 19, 2013
    Assignee: Sony Corporation
    Inventor: Fumio Meno