Abstract: A generation method of an analogue signal generated by a PWM signal whose cyclic ratio and period are parametrizable is discussed. It is thus possible choose the pair formed from the cyclic ratio and the period producing an analogue value that is the closest to the value corresponding to the programmed command value. But the differences between the analogue values can be very great and generate zones of imprecision of variable width. Outside of these zones, the generated analogue signal is very precise. Therefore, when the command value associated with a pair is imprecise, a digital shift is applied to the command value at the same time as the application of an analogue shift means. Both shifts have the same amplitude and of opposite directions such that the cancel each other out, producing a precise analogue value. A device for generating an analogue signal implementing the method is also discussed.

Abstract: A current source is used to pre-charge a capacitor to a known value. The capacitor can then be connected to a unity gain buffer to provide a low cost DAC. The DAC can include a self-calibration stage to improve accuracy. The DAC can include two or more circuit branches, each including a current source and a capacitor, where each branch can be calibrated and operated separately to reduce mismatch and to provide a continuous analog voltage output.

Abstract: In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier.

Abstract: A timing signal generator circuit includes a DA converter converting an input digital value into an analog voltage, and a VT converter converting the analog voltage into a corresponding delay time. The DA converter includes a current source circuit, which supplies a current (n×Is) (“n” is a number corresponding to the input digital value) selected from a total supply current (N×Is) as a current Iout to the resistors, and supplies the remaining current (N?n)×Is as a current Idump to the resistors, outputs a voltage across the resistors as an analog voltage Vdac, and outputs a voltage across the resistor as a reset voltage Vreset. The VT converter charges the integration capacitor with a constant current from the constant current source by using the reset voltage as an initial voltage, and outputs a timing signal when the integral voltage exceeds the analog voltage.

Abstract: A control circuit for a multi-phase converter including an analog front-end circuit for receiving and processing an output voltage and current of the converter circuits and an average output current; a digital circuit for producing an output voltage reference for setting a desired output voltage of the converter; and an error circuit for comparing the output voltage reference and a parameter related to said output voltage and current for generating control signals for controlling the converter circuits, said error circuit including an Analog to Digital Converter circuit, further comprising a digital PWM generation circuit controlled by said Analog to Digital converter circuit for generating digital control signals for controlling the converter circuits.

Abstract: A digital analog convertor has a modulator which modulates a digital signal to generate a pulse signal having a pulse density corresponding to a digital value of the digital signal; a first RZ conversion circuit which RZ-converts the pulse signal based on a first clock signal to generate a first RZ pulse signal; a first integration circuit which integrates the first RZ pulse signal to output a first analog signal; a second RZ conversion circuit which RZ-converts a first level signal having a first level of the pulse signal based on the first clock signal to generate a second RZ pulse signal; a second integration circuit which integrates the second RZ pulse signal to output a second analog signal; and a clock duty control circuit which controls a duty ratio of the first clock signal so that the second analog signal approaches a given reference level.

Abstract: A method and exemplary apparatus that incorporate soft-start circuit together with adjustable output voltage control are introduced. By implementing a gradual increment of voltage steps/fast decrement, it can totally eliminate overshoot and limit in-rush current significantly at the initial startup and output voltage transition that happens after startup.

Abstract: A digital signal transmitting apparatus includes an encoder which converts parallel input signals of multiple channels into serial data in a manner synchronized with a first clock signal, and a decoder which converts the serial data into parallel output signals of the multiple channels in a manner synchronized with a second clock signal operating in a manner asynchronous with the first clock signal. The serial data has a different period and a different duty factor corresponding to each combination of the logical values of the parallel input signals of the multiple channels.

Abstract: Provided is an output apparatus for outputting a current from an output end, including: a plurality of current sources; a plurality of switches provided in association with the plurality of current sources respectively, and switching whether to supply a current of a corresponding current source to the output end; a time changing section that changes a propagation time of each of a plurality of control signals for controlling switching states of the plurality of switches respectively; and an adjusting section that adjusts the propagation time of each of the plurality of control signals to reduce glitch noise contained in a current supplied to the output end.

Abstract: An example digital-to-analog converter (DAC) for a power supply controller includes a first node, a second node, a current source, and a switch. The first node is to be coupled to provide a first analog signal to a variable oscillator of the power supply controller. The second node is to be coupled to provide a second analog signal to the variable oscillator of the power supply controller. The switch is coupled to the current source and configured to couple the current source to the first node to provide current to the first analog signal in response to a binary digit received by the DAC, where the switch is further configured to couple the current source to the second node to provide current to the second analog signal in response to a complement of the binary digit.

Abstract: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.

Abstract: Provided is a clock generator employed in a continuous-time sigma-delta modulator. The clock generator includes an oscillator configured to generate pulses in response to an enable signal, a counter configured to count the number of pulses generated by the oscillator and output the total pulse count, and an output circuit configured to output an inactivated output signal if the pulse count of the counter is equal to a pulse-width control bit. The oscillator includes an astable multi-vibrator. Since the astable multi-vibrator capable of generating a low-jitter pulse from a jittered clock is used as the oscillator, a signal-to-noise ratio is improved. A simple configuration using only digital circuits makes it easier to design a circuit and adjust pulse width. Moreover, according to the structure of the astable multi-vibrator, it is possible to design a circuit to optimally modulate pulse width in connection with process variations of resistors and capacitors used in the continuous-time sigma-delta modulator.

Abstract: A noise shaper truncates the widths of pulses it supplies to a pulse-width modulator whose pulse-width modulated signals control a tri-level amplifier. The amplifier is filterless and DC free. Pulses that are narrower than a predefined minimum width are eliminated by the noise shaper. Other pulses are subjected to an algorithm that includes a multitude of ranges, each range defined by a minimum pulse width characterizing a lower bound of that range and a maximum pulse width characterizing an upper bound of that range. Associated with each range is a number of clock cycles defining the modified width of a pulses whose detected width falls within that range. To ensure that delays associated with a feedback loop disposed in the amplifier are accounted for, the reference voltage of a comparator tracks an output voltage of an integrator. Both the comparator and integrator are disposed in the loop.

Abstract: Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.

Abstract: Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.

Abstract: A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

Abstract: In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal.

Abstract: A method for converting an N-bit digital value into an analog value is provided. N-M most significant bits of the digital value are converted into a first PWM signal whose period is a multiple of a base time period. M least significant bits of the digital value are converted into a second PWM signal whose period is a ½M fraction of the period of the first PWM signal. A third PWM signal is generated by inserting, during the pulse pause of the first PWM signal, the pulse of a selected single period of the second PWM signal into the first PWM signal. Further, the third PWM signal is low-pass filtered.

Abstract: An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at an analog output of the cascaded circuit. Each of the cascade circuits contains a noise-shaping circuit, a PCM (Pulse Code Modulation)-to-PWM (Pulse Width Modulation) converter and a 1-bit P-tap AFIR (Analog Finite Impulse Response) filter DAC. Noise at the output of the cascaded circuit may be further reduced by increasing the number of cascade circuits.

Abstract: A module (10) connects to a CAN bus in a motor vehicle and converts a CAN message into an analog signal that can be monitored by test equipment. The module also has wireless communication with a PDA (300) via a radio transceiver (28) to allow the PDA to display a converted CAN message and to select different messages for display.

Abstract: In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal.

Abstract: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.

Abstract: A high resolution digital-to-analog converter comprises a programmable n-bit current digital-to-analog converter (IDAC), an m-bit programmable counter/timer, an integrator that converts the IDAC constant current charging a capacitor over time into an a precision (high resolution) analog voltage, and a sample and hold circuit for storing the precision analog voltage. The constant current from the IDAC is applied to the integrator for a time period determined by the programmable counter/timer, then the sample and hold circuit will sample the final voltage on the capacitor and store it as an analog voltage. The analog voltage resolution of this high resolution digital-to-analog converter is n+m bits or binary 2n+m. In addition, a plurality of sample and hold circuits may be utilized for maintaining a plurality of analog output voltages.

Abstract: The present invention relates to a generation method of a variation form of an analogue signal generated by a PWM signal whose cyclic ratio and period are programmable. A signal can thus be generated whose evolution is linear over time. A succession of generation steps of a PWM signal during which different period and cyclic ratio values are applied, as well as pairs have different periods with the same cyclic ratio, thus enabling the analogue signal to be varied with great precision. According to an improvement, each generation step of a new PWM signal with different period and cyclic ratio values is applied over time slots of equal time. The present invention also relates to a generation system of a variable analogue signal implementing the method.

Abstract: A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.

Abstract: A noise shaper truncates the widths of pulses it supplies to a pulse-width modulator whose pulse-width modulated signals control a tri-level amplifier. The amplifier is filterless and DC free. Pulses that are narrower than a predefined minimum width are eliminated by the noise shaper. Other pulses are subjected to an algorithm that includes a multitude of ranges, each range defined by a minimum pulse width characterizing a lower bound of that range and a maximum pulse width characterizing an upper bound of that range. Associated with each range is a number of clock cycles defining the modified width of a pulses whose detected width falls within that range. To ensure that delays associated with a feedback loop disposed in the amplifier are accounted for, the reference voltage of a comparator tracks an output voltage of an integrator. Both the comparator and integrator are disposed in the loop.

Abstract: A method and a system are disclosed for transmitting an N-bit digital signal at a source. The N-bit digital signal representing a binary value is used to modulate an electrical current by using N discrete voltages representing each bit. The N discrete voltages are coupled to N corresponding switches to control the switches. The switches conduct a corresponding electrical current if the value of the corresponding discrete voltage is the binary value of 1. The currents from each of the closed switches are summed to form a current-encoded data signal in a single physical conductor representing the original N-bit digital signal. The current-encoded data signal is transmitted through the single physical conductor to a current decoder for decoding the current-encoded data signal and extracting the original N-bit digital signal at a destination.

Abstract: Disclosed is a D/A converter including: a delta-sigma modulator for subjecting a digital signal to delta-sigma modulation; a pulse-width modulator for outputting a pulse-width-modulated signal having a pulse width conforming to a digital value that is output from the delta-sigma modulator; and a distortion detector for detecting a distortion component produced in the pulse-width modulator. The distortion detector includes a delay controller for receiving the digital signal and correcting the phase thereof; a second delta-sigma modulator; a second pulse-width modulator; a subtractor for subtracting the output of the second delta-sigma modulator from the output of the second pulse-width modulator; and a second subtractor for subtracting the output signal of the first subtractor from the output signal of the delay controller.

Abstract: A multi-channel display driver circuit incorporating modified D/A converters has a plurality of digital comparators connected to a number generator. Each digital comparator has an output, a digital data input and a reference input. The reference inputs of all digital comparators are connected to the number generator and the outputs are respectively connected to corresponding data channels of a display. By the proposed technique, each digital comparator obtains a unique non-sequence reference signal, and then compares it with the input digital data signal. Since the non-sequential signals are input to the reference input of the digital comparator, the overshoot distortion, the harmonic distortion and the electromagnetic interference problems are prevented. Therefore, the precise imaging can be obtained with this signal modulation technique in small circuit size.

Abstract: Provided is a DA converter that converts an input digital signal into an analog signal, comprising an integrator that outputs an integration value of the digital signal for each cycle of a constant period; a level comparing section that makes a comparison to detect whether the integration value output by the integrator is in an excessive state of being greater than a prescribed reference value; a feedback section that subtracts a predetermined value from the integration value, based on the comparison result from the level comparing section; a timing information generating section that generates, for each cycle, timing information of a change point, at which a transition to the excessive state occurs, with units of temporal resolution shorter than the constant period, based on the integration value output by the integrator for the cycle and the integration value output by the integrator for an immediately prior cycle; a timing generating section that generates a pulse signal with units of temporal resolution s

Abstract: For a sigma-delta digital-to-analog converter (SD DAC) that includes a voltage output and a low-pass filter having a given order, methods and systems for reducing a sign-bit pulse at the voltage output of the SD DAC without requiring use of a higher order low-pass filter are disclosed. A method includes receiving a first waveform and a second waveform, the first and second waveforms having a first phase relationship; setting the first phase relationship between the first and second waveforms to a second phase relationship by aligning at least one of the first and second waveforms such that a transition of the second waveform is approximately half way between a rising edge and adjacent falling edge of the first waveform; upon setting the second phase relationship, multiplying the first and second waveforms to produce a digital input; and providing the digital input to the SD DAC.

Abstract: In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: An RFIC controller configured for executing multiple tasks. A serial interface is included having a serial bus for receiving a data stream having control bits and data bits. One or more registers are coupled to the serial bus for storing the control bits and data bits as they are received. Control circuitry is also included. The data stream is formatted such that the control bits are received before the data bits, the control bits specifying an operation. The control circuitry is configured to examine the control bits as they are received to determine the operation specified by the control bits before the data bits are received. A task corresponding to the operation specified by the control bits is then initiated before the data bits are received.

Abstract: The objective of the invention is to provide a class D amplifier that can reduce aliasing noise. The class D amplifier has D/A converter 10 that operates at the first sampling frequency, and PWM driver 3 that receives the output from D/A converter 10. Said PWM driver 3 operates at the second sampling frequency synchronized to the first sampling frequency. The second sampling frequency can be correlated to the delta wave frequency of the PWM driver. Also, synchronization of said first sampling frequency and said second sampling frequency can be carried out with one of said frequencies being an integer multiple of the other.

Abstract: In a pulse width modulation method of the present invention, a digital signal is modulated and a pulse width modulation signal is generated in a pulse width modulator by using a digital signal output unit and the pulse width modulator The pulse width modulation method includes: outputting to the pulse width modulator a first value corresponding to the input signal as a first digital signal at a first timing by the digital signal output unit; determining a limited value range based on the first value by the digital signal output unit; determining a second value corresponding to a new input signal by the digital signal output unit; judging whether or not the second value is included in the limited value range, and when the second value being judged to be included, outputting the second value to the pulse width modulator as a second digital signal, and when the second value being judged not to be included, outputting a value included in the limited value range to the pulse width modulator as the second digital s

Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.

Abstract: Methods and systems for digital control.

Abstract: For PWM (pulse width modulation), a counter generates a count signal by counting a clock signal 2n times for one period of the count signal. A PWM circuit generates a PWM signal from an n-bit pulse code modulation (PCM) data. The PWM signal includes a first pulse and a second pulse that are symmetric within one period of the count signal for positive and negative values of the n-bit PCM data. A same pulse width for the first and second pulses is determined by a respective value of each bit of the n-bit PCM data excluding the most and least significant bits of the n-bit PCM data.

Abstract: By using a selector, an output of a delta sigma modulator having a quantizer for quantizing a signal is selectively supplied to one of a first D/A converter having a linear amplifier and a second D/A converter having a digital amplifier. Further, the number of quantization levels of the quantizer, the sampling frequency, or the order of a transfer function of the delta sigma modulator is selected by a control signal selector in conjunction with the selector. An output of the first D/A converter is supplied to a line terminal, while an output of the second D/A converter is supplied to a headphone terminal.

Abstract: A multi-channel signal processing system reduces electromagnetic interference (EMI) by staggering pulse edges of one or more pulse-width modulated signals (PWM signals) to prevent pulse edge overlap with at least one of the other PWM signals and inverting at least one of the PWM signals. Staggering and inverting the PWM signals reduces the total EMI power at any given time generated by the multi-channel signal processing system. Pulse edges can be staggered by advancing or delaying a pulse edge for one or more channels. Pulses can be staggered and inverted using static interleave and inversion subsystems or dynamically using controllable interleave and inversion control systems. In at least one embodiment, the multi-channel signal processing system includes high power, half-bridge amplifiers for each channel. The timing and phases of the PWM signals can be determined to reduce EMI from the half-bridge amplifiers caused by the PWM signals.

Abstract: A system comprising includes a clock generator module, an analog-to-digital converter (ADC), and a correction module. The clock generator module receives a system clock and generates a digital clock that is derived from the system clock, wherein the digital clock has an average frequency. The clock generator module generates a deviation indication that indicates a deviation of the digital clock from an ideal clock of the average frequency. The ADC receives an analog signal, receives the digital clock, and generates a first stream of values by sampling the analog signal at intervals based on the digital clock. The correction module receives the first stream of values and generates a second stream of values that are corrected based on the deviation indication.

Abstract: A switching amplifier system and method is disclosed. In a particular embodiment, a pulse width modulation frame size is determined based on a sample rate of a digital input signal. Data associated with the first digital input signal is modified based on the pulse width modulation frame size. A pulse width modulation signal is generated in response to the modified data.

Abstract: A circuit for converting a duty cycle of a pulse width modulated signal to an analog value comprising a clock signal generator for generating a clock signal, a window generation circuit for generating a window signal synchronized with the pulse width modulated signal having a window having a window start and a window termination, a counter drive circuit receiving the clock signal, the pulse width modulated signal and the window signal and producing a counter input signal, a counter circuit for counting pulses of the counter input signal and providing a counter output, a reset circuit for resetting the counter at the termination of the window; and a digital to analog converter for converting the counter output at the termination of the window to the analog value.

Abstract: A multi-channel display driver circuit incorporating modified D/A converters has a plurality of digital comparators connected to a number generator. Each digital comparator has an output, a digital data input and a reference input. The reference inputs of all digital comparators are connected to the number generator and the outputs are respectively connected to corresponding data channels of a display. By the proposed technique, each digital comparator obtains a unique non-sequence reference signal, and then compares it with the input digital data signal. Since the non-sequential signals are input to the reference input of the digital comparator, the overshoot distortion, the harmonic distortion and the electromagnetic interference problems are prevented. Therefore, the precise imaging can be obtained with this signal modulation technique in small circuit size.

Abstract: A self-contained DAC that is especially suitable for use as an IP core, particularly for SOC (System on Chip) implementation. Techniques are applied to employ certain circuits (such as arithmetic element 302) to perform multiple functions in the DAC, thereby resulting in space saving. Techniques are also applied to employ fewer circuits per functional block to achieve further space saving. By employing multiple clock domains and turning on selective circuits on an as-needed basis, power saving is also realized.

Abstract: The invention concerns a control system for a servomechanism comprising a control member that can move between first and second positions defining a variable electric quantity respectively between a minimum quantity and a maximum quantity, characterized in that the control system further comprises low voltage powering means, voltage increase means connected to the terminals of the low voltage powering means and delivering a high voltage at output, means for measuring a value of the variable electric quantity, powered by the low voltage powering means when the high voltage is being generated, and means for regulating the voltage increase means arranged to increase the high voltage delivered for a variation in the measured electric quantity value lower than a variation threshold determined by the servomechanism, respectively to decrease the high voltage delivered for a variation in the measured electric quantity values higher than the determined variation threshold.

Abstract: A system and method generate a pulse width modulated signal having variable duty cycle resolution. A hardware uses minimal hardware to improve the PWM duty cycle resolution up to 0, such that highest possible resolution of a waveform can be obtained, including a sine wave. An embodiment of the invention uses a microcontroller, a divide by W counter, a delay circuit, a flip-flop, and a logic gate.

Abstract: A method for producing an analog output from a digital input is described. A digital pulse train is received having an average value which is proportional to a digital conversion value. The digital pulse train is driven at a periodic interval to produce a modulated tristate-gate output. The modulated tristate-gate output is averaged to produce an analog output. Optionally, the pulse train is also driven at an additional periodic interval having a duty cycle of more, or less, than less than 50%. The pulse train may also be driven steadily.

Abstract: A signal processing system matches, within a band of near out-of-band frequencies, the frequency response trends of a delta sigma modulator noise transfer function (NTF) and frequency response trends of a low pass finite impulse response (FIR) filter to provide noise attenuation in in-band frequencies and near out-of-band frequencies. More specifically, in at least one embodiment, the signal processing system matches, within the band of near out-of-band frequencies, a gradient trending toward increasing energy as the near out-of-band frequencies increase of the NTF with a gradient trending toward increasing attenuation by a FIR filter to improve attenuation of near out-of-band energy in an output signal of the signal processing system. Operation of the delta sigma modulator generates near out-of-band noise. Improving attenuation of the near out-of-band energy helps prevent the near out-of-band energy from being modulated into in-band frequencies, i.e. frequencies of a signal of interest.