With Intermediate Conversion Of Digital Value To Time Interval Patents (Class 341/152)
  • Patent number: 7301488
    Abstract: An apparatus and method for minimizing limit cycle oscillations within a switched power supply includes providing a programmable dither signal as an input to the digital control loop connected between an output and a control input of the switched power supply. The dither signal minimizes limit cycle oscillations from the output of the switched power supply.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: November 27, 2007
    Assignee: Silicon Laboratories Inc.
    Inventors: Ka Y. Leung, Jinwen Xiao
  • Patent number: 7298309
    Abstract: A digital-to-analog converter (DAC) for generating an analog output voltage according to a digital input value includes a plurality of pulse width modulation (PWM) units and a voltage generating unit. The digital input value includes a plurality of bit segments. The plurality of PWM units generates a plurality of PWM signals according to the plurality of bit segments of the digital input value. The voltage generating unit is coupled to the plurality of PWM units and generates the analog output voltage according to the plurality of PWM signals.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: November 20, 2007
    Assignee: MStar Semiconductor, Inc.
    Inventors: Shuang-Chin Wu, Wei-Kuo Lee
  • Patent number: 7292171
    Abstract: The invention relates to a method and device for the conversion of digital signals comprising a phase involving modulation with the aid of a vector lattice encoder. The inventive method comprises iterative steps which are performed on N output candidates, consisting in filtering (Hx, Hq), determining the difference between the filtered signals calculating two possible evolutions for said options, pre-selecting the candidates that minimise the difference, weighting the difference with a cost function (W), marking the candidates eliminated for a subsequent iteration, and selecting the best candidate over a period determined by a historical decision dimension. The invention also relates to the use thereof in relation to a digital audio signal amplifier.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: November 6, 2007
    Assignee: Anagram Technologies SA
    Inventor: Thierry Heeb
  • Patent number: 7283078
    Abstract: A converter of a digital signal into a pulse-width modulated signal, comprising a first conversion unit receiving, at a first frequency, successive digital signals each having one of a first determined number of values, and providing first intermediary signals, at the first frequency, each having one of a second determined number of values smaller than the first determined number; a unit performing a decimation of the first intermediary signals to provide second intermediary signals at a second frequency equal to the first frequency divided by the second determined number minus one; and a second conversion unit providing at the second frequency, from the second intermediary signals, a two-state pulse-width modulated signal having a minimum duration in one of the two states which is equal to the inverse of the first frequency, the first conversion unit receiving the pulse-width modulated signal.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: October 16, 2007
    Assignee: Dolphin Integration
    Inventors: Frédéric Poulet, Guillaume Cogniard
  • Patent number: 7271754
    Abstract: A digital pulse-width modulator is provided that receives a digital command input signal and a secondary control input signal and provides a pulse-width-modulated output signal. The pulse-width-modulated output signal comprises a pulse-width that corresponds to an integer number of slots each having a time duration. The integer number of slots corresponds to a value of the digital command signal, and the time duration is determined based upon the secondary control input signal. In one embodiment, the digital pulse-width-modulator comprises a plurality of delay cells arranged in series for propagating a clock signal through the plurality of delay cells. A time delay for each of the delay cells is determined by the secondary control input signal.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: September 18, 2007
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Dragan Maksimovic, Asif Syed, Ershad Ahmed
  • Patent number: 7271744
    Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: September 18, 2007
    Assignee: Ramtron International
    Inventors: Xiao Hong Du, Dennis C. Young
  • Patent number: 7242330
    Abstract: A system and method of dynamic offset compensation that is particularly adaptable to analog-to-digital conversion performed in control applications employing highly integrated Digital Signal Processor (DSP) devices. The system providing dynamic compensation of Analog-to-Digital Converter (ADC) zero level offset errors includes an integrated DSP device with a multi-bit ADC and a PWM waveform generator for producing at least one PWM output, and an external low pass filter. The ADC receives an analog input signal and converts it into a corresponding digital output signal. The DSP device measures the zero level offset of the ADC output signal, and dynamically controls characteristics of the PWM output based on the measured offset. The low pass filter receives the PWM output and applies a corresponding controlled DC output voltage to the low reference voltage input of the ADC to dynamically compensate for the zero level offset error.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: July 10, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: David Michael Alter
  • Patent number: 7236112
    Abstract: A self-tuning filter that is well suited for use as a output digital filter in a direct conversion delta-sigma transmitter is constructed as a high pass finite impulse response filter having a cutoff frequency of twice the desired carrier frequency. The filter is clocked using the same clock as used for the commutatation within the transmitter. The aliasing effect of the digital filter produces a passband centered around the carrier frequency which allows the information contained in the spectrum around the passband to be transmitted, while effectively filtering out the quantization noise produced by the commutation. When the commutator clock frequency is changed in order to change the carrier frequency, the passband automatically moves to track the new carrier frequency. The output filter may be constructed using series connected flip-flops with analog taps and an analog summer connected to respective Q and Q outputs, thereby producing an analog output.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: June 26, 2007
    Assignee: TechnoConcepts, Inc.
    Inventor: Ronald M. Hickling
  • Patent number: 7227487
    Abstract: An audio amplifier includes a digital signal processor (DSP) that contains a noise shaping quantizer having an integrating error amplifier. The integrating error amplifier contains integrators connected in a feedback loop, a summer supplied with an output of each of the integrators, and a saturation function module producing a saturation function. A multiplier is disposed between each pair of adjacent integrators. The multiplier receives a signal from one of the adjacent integrators and the saturation function and supplies a signal to the other of the adjacent integrators. The saturation function decreases the effect of all of the integrators except an integrator to which an input signal to the integrating amplifier is supplied using an input signal to and/or an output signal from the noise shaping quantizer. This permits the duty ratio of the output signal from the noise shaping quantizer to extend from 0% to 100%.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: June 5, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Pallab Midya, William J. Roeckner, John Grosspietsch, Anthony R. Schooler
  • Patent number: 7221297
    Abstract: A D/A converter in which distortion caused by PWM is favorably removed even if a sampling frequency is low relative to a signal frequency is provided. The D/A converter includes a pulse-width-modulated-signal outputting circuit for outputting a pulse-width-modulated signal having a pulse width in accordance with a digital value of an input digital signal.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: May 22, 2007
    Assignee: Sony Corporation
    Inventors: Kazunobu Ohkuri, Toshihiko Masuda
  • Patent number: 7215272
    Abstract: A digital system employing a multi-channel and multi-level PWM technique that allows for smoother transitions in the outputs of the multiple channels in response to variations in the level of a digital input signal. The system generates PWM and other digital control signals to control switching circuitry included in the multiple channels, in which the PWM control signals are generated from a number of LSBs of the digital input signal, and the other digital control signals are generated from the remaining MSBs of the digital input signal. The system provides selected ones of the PWM and other digital control signals to each channel for controlling the switching circuitry included therein. By providing both the PWM and the other digital control signals to the multiple channels in an interleaved manner, smoother transitions in the outputs of the various channels can be achieved, thereby reducing the occurrence of unwanted transients in the system output.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: May 8, 2007
    Inventor: Ying Lau Lee
  • Patent number: 7209064
    Abstract: The signal processing system includes a pulse width modulator (PWM) that receives a quantizer output signal from a delta sigma modulator. Each quantizer output signal represents one of N quantization levels. For at least one of the quantization levels, the PWM can generate multiple, different PWM patterns. Thus, each quantization level in at least a subset of the N quantization levels is associated with at least two PWM patterns. In at least one embodiment, the subset of quantization levels represents the quantization of low level samples of a quantizer input signal. By associating multiple PWM patterns to at least the subset of the quantization levels, the pulse edges of the PWM patterns in a frame are shifted in time with respect to subsequent PWM patterns, which spreads the spectrum of harmonic frequencies of the PWM output signal. Spreading the spectrum of harmonic frequencies of the PWM output signal can reduce electromagnetic interference (EMI).
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 24, 2007
    Assignee: Cirrus Logic, Inc.
    Inventors: Johann Gaboriau, John L. Melanson
  • Patent number: 7199744
    Abstract: A method of generating a pulse width modulated data stream includes providing a first clock signal having a first frequency and selecting a divisor from a set of divisors for dividing the first frequency to select a pattern rate of a pulse width modulated data stream and thereby shift in frequency noise generated at the pattern rate during pulse width modulation. The first frequency of the first signal is divided to generate a second signal at the selected pattern rate. Noise shaping and requantizing is performed on the second signal to generate a noise shaped and requantized second signal and the pulse width modulated data stream having patterns at the selected pattern rate is generated in response to the first signal and the noise shaped and requantized second signal.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: April 3, 2007
    Assignee: Cirrus Logic, Inc.
    Inventor: John Laurence Melanson
  • Patent number: 7183959
    Abstract: According to one aspect of the present invention, this invention implements a low latency, wide bandwidth method and system for converting a numeric digital values into a pulse density modulated analog output signals. Such output signals having their lowest output frequency much closer to the system clock frequency, thus enabling wider bandwidth and simpler implementations than with traditional approaches. This method is based in part on an adaptation of Bresenham's Line Drawing Algorithm.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: February 27, 2007
    Assignee: Honeywell International, Inc.
    Inventors: John A. Dickey, Paul B. DuPuis
  • Patent number: 7176824
    Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: February 13, 2007
    Assignee: Ramtron International
    Inventors: Xiao Hong Du, Dennis C. Young
  • Patent number: 7161519
    Abstract: The PWM modulation circuit according to the invention is connected to an input terminal for an analog baseband signal and a staircase generating circuit generating a staircase wave, and carries out PWM modulation to a staircase wave input from the staircase generating circuit based on an analog baseband signal input from the input terminal. The staircase generating circuit includes a plurality of constant current source circuits, a plurality of switches connected to the plurality of constant current source circuits on a one-to-one basis, a serial-parallel conversion circuit that carries out serial-parallel conversion to a clock signal input from a clock signal input terminal and outputs the result to the plurality of switches, and an output voltage control circuit that converts a constant current input from the plurality of constant current source circuits into a constant voltage at an arbitrary value and outputs the result.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: January 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideo Taniuchi
  • Patent number: 7161518
    Abstract: In one embodiment, a micro electromechanical system (MEMS) driver circuit receives a pulse-width modulated (PWM) signal and uses it to control a voltage at a MEMS cell. The driver circuit further includes a current source, a capacitor, and a reset circuit that can discharge the capacitor. The voltage at the MEMS cell can be controlled in proportion to the pulse width of the PWM signal. In another embodiment disclosed, a MEMS driver circuit receives a first PWM signal and a second PWM signal. Each PWM signal is coupled to a current source. One current source can provide a course current control and the other current source can provide fine current control. The driver circuit can further include a capacitor and a reset circuit for discharging the capacitor. The voltage at the MEMS cell can be controlled in proportion to a summation of the first and second current sources. According to another aspect of the embodiments, a method of controlling a voltage at a MEMS cell is disclosed.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: January 9, 2007
    Assignee: Silicon Light Machines Corporation
    Inventors: Douglas A. Webb, Stephen Gaalema
  • Patent number: 7142819
    Abstract: A method of controlling noise in a pulse width modulation circuit includes varying a sample frequency and a range of information levels, wherein each sample within a data sample stream at the sample frequency represents a level within the range of information levels, to shift in frequency noise generated at the sample frequency during encoding of the data sample stream into pulse width modulated patterns.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: November 28, 2006
    Assignee: Cirrus Logic, Inc.
    Inventors: Chang Yong Kang, John Laurence Melanson
  • Patent number: 7126510
    Abstract: An integrated circuit device includes one or more calibration paths including one or more devices. A signal generator is coupled to at least one calibration path and configured to provide the calibration path with a calibration signal having known characteristics. A controller is coupled to the signal generator and the calibration path and configured to adjust the signal generator and at least one parameter associated with at least one device in the calibration path.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: October 24, 2006
    Assignee: Rambus Inc.
    Inventors: Elad Alon, Bruno W. Garlepp, Vladimir Stojanovic, Andrew Ho, Fred F. Chen
  • Patent number: 7038606
    Abstract: An audio signal reproduction device of the invention has a seventh-order delta-sigma modulation circuit that receives a PCM signal and that performs delta-sigma modulation on the PCM signal, a PWM circuit that performs pulse width modulation on the signal outputted from the seventh-order delta-sigma modulation circuit to produce a one-bit digital signal, a switching amplifier that converts the one-bit digital signal into an analog signal and that then amplifies it, and a low-pass filter that eliminates high-frequency components of the analog signal. This configuration permits size and weight reduction.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: May 2, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tsunehiko Hongoh, Hirotoshi Yamamoto
  • Patent number: 7012556
    Abstract: An adaptive signal processing system (800) comprises a plurality of receiving elements (802a–n), a plurality of analogue to digital converters (ADC's) (806a–n) and a digital signal processor (808). Each of the receiving elements (802a–n) is arranged to receive an incoming signal and has an ADC (806a–n) connected thereto. Each ADC *(806a–n) is arranged to convert a first portion of respective incoming signal into a digital form at a sampling rate less than the temporal Nyquist rate of the incoming signal. The signal processing (808) means is arranged to calculate complex weighting coefficients to be applied to a second portion of the incoming signal using the digitized first portion of the incoming signals. A method of calculating complex weighting coefficients is also described.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: March 14, 2006
    Assignee: Qinetiq Limited
    Inventors: Michael Dean, Paul Nicholas Fletcher
  • Patent number: 6992610
    Abstract: A PWM signal generator and generating method for generating one or two pulses having a pulse width or a total pulse width corresponding to a value represented by a pulse code modulation digital signal and placed in a symmetric positional relationship with respect to the position of one half of a predetermined length. A first pulse and a second pulse are generated in accordance with a value represented by the digital signal. The difference in pulse width between the first and second pulses is output as a first pulse width modulation signal. When the value represented by the digital signal is zero, the first pulse and second pulse are equal in pulse width. When the value represented by the digital signal changes by one, one of the first and second pulses does not change in pulse width, while the other of the first and second pulse changes in pulse width by two slots.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: January 31, 2006
    Assignee: Pioneer Corporation
    Inventor: Mitsuya Komarura
  • Patent number: 6965335
    Abstract: A method of performing digital to analog conversion includes generating a pulse width modulated data stream and another pulse width modulated data stream, encoding patterns of the pulse width modulated data stream selected to minimize distortion in the another pulse width modulated stream caused by edges in the pulse width modulated data stream. The pulse width modulated data stream and the another pulse width modulated data stream are converted into an analog signal and another analog signal converting in corresponding digital to analog conversion elements and the analog signal and the another analog signal are summed to generate an analog output signal.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: November 15, 2005
    Assignee: Cirrus Logic, Inc.
    Inventors: Brian David Trotter, Bruce Duewer, John Laurence Melanson
  • Patent number: 6940437
    Abstract: A method of operating a delta-sigma modulator by providing a variable-level quantizer, which selectively enables an additional quantizer level(s) during a ramp up sequence of the modulator. The additional quantizer level(s) is/are disabled during normal operation. The quantizer truncates a summer output and selectively enables the additional quantizer levels by clipping the truncated sum within a first range of quantizer levels during the ramp up sequence and within a second range of quantizer levels during normal operation in which there are more quantizer levels in the first range than in the second range. The quantizer preferably enables at least two additional quantizer levels at a low end of the quantizer range. For example, the range of quantizer levels for normal operation of the modulator can be from ?6 to +6, while the range of quantizer levels for ramp up operation of the modulator can be from ?8 to +7.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: September 6, 2005
    Assignee: Cirrus Logic, Inc.
    Inventors: Brian David Trotter, Bruce Eliot Duewer
  • Patent number: 6933873
    Abstract: Methods and apparatus for varying and measuring the position of a micromachined electrostatic actuator using a pulse width modulated (PWM) pulse train are disclosed. One or more voltage pulses are applied to the actuator. In each of the pulses, a voltage changes from a first state to a second state and remains in the second state for a time tpulse before returning to the first state. The position of the actuator may be varied by varying the time ?tpulse. A position of the actuator may be determined by measuring a capacitance of the actuator when the voltage changes state, whether the time t is varied or not. An apparatus for varying the position of a MEMS device may include a pulse width modulation generator coupled to the MEMS device an integrator coupled to the MEMS device and an analog-to-digital converter coupled to the integrator. The integrator may measure a charge transferred during a transition of a pulse from the pulse generator.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: August 23, 2005
    Assignee: Analog Devices, Inc.
    Inventors: David Horsley, Robert Conant, William Clark
  • Patent number: 6914548
    Abstract: An efficient technique for generating accurate on-chip DC reference voltages is based on filtering a digital pulse modulated sequence in order to extract its average value encoding a DC level, A passive on-chip filter is used for simplicity with an all-digital modulator implementation. Modulation is proposed using pulse-width and preferably pulse-density modulation methods. The latter has the advantage of using a significantly smaller filter which translates into a smaller implementation and faster operational settling times. Many digital pulse modulation generators are proposed.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: July 5, 2005
    Assignee: McGill University
    Inventors: Gordon W. Roberts, Mohamed Hafed, Sébastien Laberge
  • Patent number: 6885330
    Abstract: A pulse width modulator includes at least one input for receiving an input signal and pulse width modulation circuitry for generating a pulse width modulated stream and another pulse width modulated stream. The pulse width modulated stream and the another pulse width modulated stream are nominally out of phase and together represent the received input signal. A summer sums the pulse width modulated stream and the another pulse width modulated stream to generate an analog output signal.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: April 26, 2005
    Assignee: Cirrus Logic, Inc.
    Inventors: Brian David Trotter, Bruce Duewer, John Laurence Melanson
  • Patent number: 6861815
    Abstract: Embodiments of present invention may provide a motor control drive circuit for driving a motor by receiving signals from a digital signal control device. The motor control drive circuit includes a switching unit receiving signals that have undergone pulse width modulation (PWM signals) in the digital signal control device, and converting a switching state based on the input signals; and a controller receiving from the switching unit switching operational signals that vary according to a duty ratio of the PWM signals, receiving digital signals from the digital signal control device, and varying a voltage gain for control of the drive motor. In the motor control drive circuit of one embodiment of the present invention, motor rotation is controlled by the duty ratio of digital signals without the use of a DAC. This allows for the design of an independent digital signal processing device, and enables compatibility with various digital signal processing devices.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: March 1, 2005
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Hyun-Min Cho, Yong-Bae Park
  • Patent number: 6856269
    Abstract: A D/A conversion method and D/A converter. First, an m-bit data is input, wherein the m-bit data includes upper n bit data and lower m?n bit data. Then, a first n bit data is obtained by transforming the upper n bit data. Finally, the upper n bit data is applied to an n-bit D/A converter for a first duration and the first n-bit data is applied to the n-bit D/A converter for a second duration, according- to the lower m?n bit data.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: February 15, 2005
    Assignee: Winbond Electronics Corp.
    Inventor: Ming-Yung Shih
  • Patent number: 6853325
    Abstract: In a digital amplifier, a time controller generates first and second selection signals for outputting any one of music data, a center output, and a lowest output to a P output and an N output based on a power ON/OFF signal and a start/stop signal, and also generates a third selection signal for determining whether a signal having the same phase as that of the P output is output to the N output or a signal obtained by inverting the P output is output to the N output. A data selection circuit determines data to be output to the P output and the N output based on the first and second selection signals. An output data register circuit converts parallel data determined by the data selection circuit into serial data to output the serial data into the P output. An output selection circuit determines the N output based on the third selection signal.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: February 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Masako Arizumi, Hiroyuki Harada
  • Patent number: 6853957
    Abstract: A process data capture and reporting system captures process data values at sensors. A client computer appends absolute-value time stamps to the values to complete records, which are uploaded to a server. The server writes the records to a persistent database. At a later stage, the server retrieves selected records, and performs a very fast conversion of the time stamps to a calendar format with “granular” values for units such as day, month, or minute. The conversion is performed in an optimised manner with use of look-up tables in memory. This minimises processor overhead, and is thus very advantageous where data volumes are high and/or near real time reporting is required.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: February 8, 2005
    Assignee: Automsoft R & D Limited
    Inventors: Austin Cagney, David McCormack, Ian Pepper
  • Patent number: 6850177
    Abstract: A method and circuit are provided for converting a digital signal to an analog signal in the form of a pulse width modulated (PWM) pulse (20). The PWM pulse is generated during an output cycle of a pulse generator to form a pulsetrain output of pulses at a fixed frequency whose widths are determined by dynamically changing digital input data. The method includes the steps of dividing the digital data signal into most significant bit (MSB) and least significant bit (LSB) portions. A PWM pulse is initiated at the beginning of an output cycle and continues while the MSB portion counts down in a counter (24). At the same time, the LSB portion of the digital data signal is converted to a precise phase delay signal which is a subcycle of an oscillator controlling the counter. This phase delay signal is generated after the termination of the MSB count, and halts the high period of the PWM pulse during the output cycle. When the output cycle ends, the process is repeated with the next digital signal.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: February 1, 2005
    Assignee: Xyron Corporation
    Inventors: Brian Donovan, Ray S. McKaig
  • Patent number: 6842134
    Abstract: Disclosed is a D/A converter including a DC processing circuit, an analog switching device, a bootstrap circuit, and a third order low-pass filter. The boots trap circuit substantially reduces loading created by the low-pass filter circuit and acting on the switching device. Cross-over discontinuities in the continuous analog signal are reduced by interposing between each two successive pulses a cross-over correction pulse having opposite polarity and a predetermined fixed pulse-width. The D/A converter provides fast and accurate response over a long period of time.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: January 11, 2005
    Assignee: Her Majesty the Queen in right of Canada, as represented by the Minister of National Defence
    Inventor: Francois J. Paquet
  • Patent number: 6831582
    Abstract: A digital to analogue converter with current output and a mixer with current input are used, and the entire circuit configuration operates within the current area. This means that the current output of the digital to analogue converter, if necessary, is directly connected to the current input of the mixer with intermediate insertion of a filter operating within the current area, without any conversion of the current signals occurring between the digital to analogue converter and the mixer into a voltage. Therefore, the circuitry cost can be reduced because various components are dispensed with and the signal quality improved, since distortions and noise are prevented due to current to voltage conversion at the end of the digital to analogue converter or voltage to current conversion at the input of the mixer.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: December 14, 2004
    Assignee: Infineon Technologies AG
    Inventors: Franz Kuttner, Peter Bogner
  • Publication number: 20040189502
    Abstract: A multi-level pulse width modulation (multi-level PWM) technique uses multiple voltage levels and/or multiple output channels to obtain improved resolution (also referred to as dynamic range) over ordinary PWM-based digital systems, in particular digital audio systems. A digital audio signal is converted to either (1) an N-level PWM signal which is output to a single channel including a filter and loudspeaker, (2) N components of an N-level PWM signal output to N corresponding channels, (3) some number of multi-level signals output to multiple channels or (4) some number of PWM signals output to multiple channels. The digital audio signal can also be divided into different frequency bands to be processed separately and output to different sets of loudspeakers, wherein fewer low frequency loudspeakers can be used than high frequency loudspeakers to produce equal effective resolution for the output of all frequency bands.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Inventor: Ying Lau Lee
  • Publication number: 20040189503
    Abstract: A digital to analog converter including a noise shaping modulator for modulating an input digital data stream, a plurality of output elements for generating a plurality of intermediate data streams from a modulated output stream from the modulator, and an output summer for summing the intermediate data streams to generate an output analog stream. The noise shaping modulator balances an edge transition rate of the output elements, such that the edge transition rate of two selected elements is approximately equal.
    Type: Application
    Filed: April 14, 2004
    Publication date: September 30, 2004
    Applicant: Cirrus Logic, Inc.
    Inventor: John Laurence Melanson
  • Patent number: 6798369
    Abstract: A system for generating an analog signal to produce sound using a precision multiple pulse width modulator circuit is disclosed. The system includes a control circuit, a pulse width modulation circuit, and a mixer circuit. The control circuit includes a memory for storing sound tables. The control circuit senses an event, accesses the sound table associated with the event, retrieves an entry value from the sound table, and communicates the entry value with the pulse width modulation circuit. The pulse width modulation circuit includes (I) number of pulse width modulators and the entry value is represented by a number having (I) places where each pulse width modulator represents a place of the number representing the entry value. The mixer circuit includes multiple resistors. Each resistor is connected to a pulse width modulator from the pulse width modulation circuit on one end and the common node of the mixing circuit on the other end.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: September 28, 2004
    Assignee: Visteon Global Technologies, Inc.
    Inventor: Charles F. Weber
  • Publication number: 20040174286
    Abstract: A method and circuit are provided for converting a digital signal to an analog signal in the form of a pulse width modulated (PWM) pulse (20). The PWM pulse is generated during an output cycle of a pulse generator to form a pulsetrain output of pulses at a fixed frequency whose widths are determined by dynamically changing digital input data. The method includes the steps of dividing the digital data signal into most significant bit (MSB) and least significant bit (LSB) portions. A PWM pulse is initiated at the beginning of an output cycle and continues while the MSB portion counts down in a counter (24). At the same time, the LSB portion of the digital data signal is converted to a precise phase delay signal which is a subcycle of an oscillator controlling the counter. This phase delay signal is generated after the termination of the MSB count, and halts the high period of the PWM pulse during the output cycle. When the output cycle ends, the process is repeated with the next digital signal.
    Type: Application
    Filed: April 12, 2004
    Publication date: September 9, 2004
    Inventors: Brian Donovan, Ray S. McKaig
  • Publication number: 20040130472
    Abstract: In a digital amplifier, a time controller generates first and second selection signals for outputting any one of music data, a center output, and a lowest output to a P output and an N output based on a power ON/OFF signal and a start/stop signal, and also generates a third selection signal for determining whether a signal having the same phase as that of the P output is output to the N output or a signal obtained by inverting the P output is output to the N output. A data selection circuit determines data to be output to the P output and the N output based on the first and second selection signals. An output data register circuit converts parallel data determined by the data selection circuit into serial data to output the serial data into the P output. An output selection circuit determines the N output based on the third selection signal.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 8, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Masako Arizumi, Hiroyuki Harada
  • Patent number: 6717540
    Abstract: A method and apparatus precondition an analog signal and convert the preconditioned signal into a digital representation. The method includes preconditioning the analog signal, generating a quantity N of reference signals, comparing an amplitude of the preconditioned signal to an amplitude of the reference signals to determine whether the preconditioned signal amplitude is greater than, less than or equal to reference signal amplitudes, and producing a timestamp at a time that the preconditioned signal and reference signal amplitudes are equal. The apparatus includes a preconditioner, a reference signal generator and a quantity N of comparators. A comparator of the quantity N of comparators receives the preconditioned signal from the preconditioner, separately receives a reference signal, and produces a digital signal. The preconditioned signal or the analog signal may be reconstructed from the digital representation.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: April 6, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Linda A Kamas, Jochen Rivoir
  • Publication number: 20040051654
    Abstract: A D/A converter in which distortion caused by PWM is favorably removed even if a sampling frequency is low relative to a signal frequency is provided. The D/A converter includes a pulse-width-modulated-signal outputting circuit for outputting a pulse-width-modulated signal having a pulse width in accordance with a digital value of an input digital signal.
    Type: Application
    Filed: June 30, 2003
    Publication date: March 18, 2004
    Inventors: Kazunobu Ohkuri, Toshihiko Masuda
  • Patent number: 6703957
    Abstract: When forming PDM pulses by a D/A converter in accordance with digital signals, the D/A converter causes at least one of the rising stage and the falling stage of each of the PDM pulses to change stepwise. In addition, when forming PWM pulses by another D/A converter, the D/A converter causes at least one of the rising stage and the falling stage of each of the PWM pulses to change stepwise.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: March 9, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Morimoto, Toshio Kumamoto, Takashi Okuda, Takahiro Miki
  • Patent number: 6674383
    Abstract: Methods and apparatus for varying and measuring the position of a micromachined electrostatic actuator using a pulse width modulated (PWM) pulse train are disclosed. One or more voltage pulses are applied to the actuator. In each of the pulses, a voltage changes from a first state to a second state and remains in the second state for a time tpulse before returning to the first state. The position of the actuator may be varied by varying the time &Dgr;tpulse. A position of the actuator may be determined by measuring a capacitance of the actuator when the voltage changes state, whether the time t is varied or not. An apparatus for varying the position of a MEMS device may include a pulse width modulation generator coupled to the MEMS device an integrator coupled to the MEMS device and an analog-to-digital converter coupled to the integrator. The integrator may measure a charge transferred during a transition of a pulse from the pulse generator.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: January 6, 2004
    Assignee: Onix Microsystems, Inc.
    Inventors: David Horsley, Robert Conant, William Clark
  • Patent number: 6653998
    Abstract: A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. The number of the plurality of digital signal lines on one side of the output can be odd number, such as 2n−1, or can be 2n−2.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: November 25, 2003
    Assignee: Winbond Electronics Corp.
    Inventors: Shi-Tron Lin, Yung-Peng Hwang
  • Patent number: 6651036
    Abstract: A circuit that provides the root-mean-square (RMS) value of an input signal and that detects and independently recovers from an output fault condition is provided. The circuit includes reconfigurable circuitry that changes from normal operating mode to fault recovery mode when an output fault is detected. During fault recovery mode, the circuit provides a modified output signal that allows independent recovery from an output fault condition. Once recovery is complete, the circuit returns to normal operating mode and provides a DC output signal proportional to the RMS value of an AC input signal.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: November 18, 2003
    Assignee: Linear Technology Corporation
    Inventor: Joseph Gerard Petrofsky
  • Patent number: 6628221
    Abstract: An analog signal amplifying method, an amplifier to output a first pulse of high level by comparing an input signal with a first sawtooth-wave having an amplitude greater than that of the input signal and determining that the first sawtooth-wave is greater than the input signal; to output a narrower second pulse of one short type at every starting point of the high region of the first pulse; to continuously extract an output voltage by corresponding the second sawtooth-wave having a period identical to that of the first sawtooth-wave with a high point of the second pulse and sampling the second sawtooth-wave voltage positions at the corresponded parts; to change the extracted voltage to a condenser by a high speed switch to maintain it constant; and to eliminate a valley of a waveform, thereby performing a convenient filtering process, whereby the invention can obtain good linearity of the first sawtooth-wave very easily, with neither restrictions to an input voltage range nor use of a negative feedback, to t
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: September 30, 2003
    Inventor: Ok-Sang Jin
  • Patent number: 6606046
    Abstract: A digital-to-analog converter including a signal generator, a low-weighted value manager, and a voltage smoothing circuit. The signal generator performs a pulse width modulation (pwm) based on a reference clock signal and upper nh bits of the n-bit digital data to generate a first pulse-width-modulated signal having first pulses having a first pulse width in response to a value of the upper nh bits of the n-bit digital data and a pwm cycle signal. The low-weighted value manager divides a pulse width in response to a value of the lower nl bits of the n-bit digital data into fraction pulse widths, respectively adds the fraction pulse widths to the first pulses, and generates a second pulse-width-modulated signal having second pulses including the first pulse width and one of the fraction pulse widths.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: August 12, 2003
    Assignee: Ricoh Company, Ltd.
    Inventor: Tohru Kanno
  • Publication number: 20030122692
    Abstract: A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventors: William J. Roeckner, Pallab Midya, Poojan A. Wagh, William J. Rinderknecht
  • Publication number: 20030117300
    Abstract: A PWM converting circuit includes a pulse generator for generating two pulse signals for each bit of a basic clock pulse train in response to the value of digital input data, and a differential amplifier for outputting a differential amplification component between the two pulse signals as a PWM signal. The pulse generator varies a pulse width of one of the two pulse signals on a bit-by-bit basis of the basic clock pulse train in response to the value of the digital input data, and holds a level of the other of the two pulse signals throughout the entire bits of the basic clock pulse train within the period of the pulse of the PWM signal.
    Type: Application
    Filed: June 11, 2002
    Publication date: June 26, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Harada, Masako Arizumi
  • Publication number: 20030090401
    Abstract: A &Dgr;·&Sgr; type DA converter is provided with a digital circuit 21 including a PWM circuit 26 and an analog circuit 22, wherein in order to make an output of the analog circuit 22 a predetermined value, the analog circuit 22 is driven at a predetermined direct current voltage V1 (for instance, 5 V), and the digital circuit 21 is driven at a direct current voltage V2 (for instance, 3.3V) that is set lower than the direct current voltage V1. Since the digital circuit 21 and the analog circuit 22 are driven at different power supply voltages, a level shifter 23 is disposed at a boundary portion of the digital circuit 21 and the analog circuit 22, the level shifter 23 steps up a level of the PWM signal outputted from the PWM circuit 26.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 15, 2003
    Inventor: Masayuki Yoshizawa