Parallel Type Patents (Class 341/159)
  • Patent number: 8866658
    Abstract: A resistor string digital-to-analog converter includes a high-order resistor string, first high-order switches, a high-order decoder, a low-order decoder, and a conversion unit. The high-order resistor string includes a plurality of voltage acquisition points that are coupled through unit resistors. The high-order decoder generates a first high-order control signal in accordance with a high-order bit value, and operates in accordance with the first high-order control signal to bring into conduction a first high-order switch coupled to a pair of voltage acquisition points adjacent to each other through one or more voltage acquisition points. The low-order decoder generates a low-order control signal for controlling the conversion unit. The conversion unit divides a pair of high-order analog voltages output from a pair of voltage acquisition points.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Hirai
  • Patent number: 8860591
    Abstract: An ADC which samples an analog input signal at a sampling frequency and converts the analog input signal to a digital output signal, has N analog digital converter (ADC) channels which convert the analog input signal into the digital output signal by time interleaving, a channel synthesizer which synthesizes channel digital signals output respectively by the ADC channels to generate the digital output signal, an adaptive filter provided at at least one output of the ADC channels, and a correction circuit which generates a coefficient of the adaptive filter in accordance with the digital output signal. The correction circuit calculates a DC component of an image signal component, from among an analog input signal component and the image signal component corresponding to error, both being included in the digital output signal, and calculates the coefficient such that the DC component is suppressed on the basis of the DC component.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takeshi Nozaki
  • Patent number: 8860592
    Abstract: A signal generating circuit, may include an analog signal generator having an output and a control input, the analog signal generator configured to generate at the output an analog output signal in accordance with a timing parameter; an analog-to-digital converter (ADC) having an input and an output, the input coupled to the output of the analog signal generator, the ADC configured to generate a sequence of signal values dependent on the analog signal received at the input; a configurable digital signal generator comprising an output and a control input, the digital signal generator configured to generate a digital output signal in accordance with signal parameters received at the control input; and a control circuit having an input coupled to the output of the ADC.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Heinz Mattes, Ralf Arnold, Hermann Obermeir
  • Patent number: 8860589
    Abstract: Examples are provided for a time-interleaved analog-to-digital converter (ADC) with built-in self-healing. The ADC may include multiple ADC slices. Each ADC slice may be configured to operate in one of a normal or a healing mode of operation. In the normal mode of operation, each ADC slice may convert an input analog signal to a single digital output signal in response to a clock signal associated with the ADC slice. In the healing mode of operation, each ADC slice may be operable to convert the input analog signal to two or more digital output signals in response to two or more clock signals. One or more of the digital output signals may replace one or more output signals of failed ADC slices. A first clock signal may be associated with the ADC slice. A second clock signal may be associated with another ADC slice of the plurality of ADC slices.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: October 14, 2014
    Assignee: Semtech Corporation
    Inventors: Krishna Shivaram, Sandeep Louis D'Souza, Craig Allison Hornbuckle
  • Patent number: 8854243
    Abstract: A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: October 7, 2014
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Masato Yoshioka, Yanfei Chen, Tatsuya Ide
  • Patent number: 8836376
    Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo
  • Patent number: 8830106
    Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Udayan Dasgupta, Ganesan Thiagarajan, Venugopal Gopinathan
  • Patent number: 8823573
    Abstract: System and method for converting a high bandwidth analog signal to a digital signal including: receiving the high bandwidth analog signal; splitting the high bandwidth analog signal to M parallel channels; delaying the split signal in each channel with N*T delays, respectively; sampling each M delayed signals by M relatively prime sampling rate, wherein the sampling rate for each M delayed signal is smaller than the Nyquist frequency of the high bandwidth analog signal; upsampling each M sampled signal, wherein the upsampling rate for each M sampled signal satisfies the Nyquist frequency of the high bandwidth analog signal; combining the M up sampled signals into a combined signal; and reconstructing the combined signal to generate a digital signal representing the high bandwidth analog signal.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: Raytheon Company
    Inventors: Tuan V. Nguyen, Oleg Brovko, Alison Kim, Trung T. Nguyen
  • Patent number: 8803724
    Abstract: An analog to digital conversion system is disclosed which converts an analog signal to a digital representation thereof at a first sampling rate by distributing the analog signal to at least two signal paths, at least one signal path including a limiting mixer to mix the signal with a respective selected square wave and a smoothing (low pass) filter to filter the mixed signal before providing the mixed and filtered signal to a subconverter, the subconverter having a sampling rate less than the first sampling rate, and a digital matrix filter to combine the digital output of each subconverter to form a digital representation of the analog signal as sampled at the first rate.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: August 12, 2014
    Assignee: Kapik Inc.
    Inventor: William Martin Snelgrove
  • Patent number: 8760329
    Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 24, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ganesan Thiagarajan, Udayan Dasgupta, Venugopal Gopinathan
  • Patent number: 8749421
    Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: June 10, 2014
    Assignees: The Trustees of Columbia University in the City of New York, Commissariat a l'Energie Atomique
    Inventors: Mariya Kurchuk, Colin Weltin-Wu, Yannis Tsividis, Dominique Morche, David Lachartre
  • Patent number: 8743254
    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage VX are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage VX, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become ?W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventors: Hayato Wakabayashi, Masaru Kikuchi, Hiroshi Iwasa, Yuuki Yamagata
  • Publication number: 20140132437
    Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.
    Type: Application
    Filed: August 28, 2013
    Publication date: May 15, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Takumi DANJO
  • Patent number: 8723713
    Abstract: There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by ā€œ2^nā€; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junya Matsuno, Tetsuro Itakura
  • Patent number: 8717037
    Abstract: A main microcomputer abnormality determination section checks whether or not a voltage value of Vcc based on digital data output from a main microcomputer analog-to-digital converter is equal to or higher than a threshold value to thereby perform abnormality determination for the main microcomputer analog-to-digital converter and Vref. A sub microcomputer abnormality determination section checks whether or not the voltage value of Vcc is equal to or higher than a threshold value based on digital data output from a sub microcomputer analog-to-digital converter to thereby perform abnormality determination for the sub microcomputer analog-to-digital converter and Vref. An abnormality identifying section identifies an abnormality occurring site by using both results of the abnormality determination performed by the main microcomputer abnormality determination section and the sub microcomputer abnormality determination section.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: May 6, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masayuki Maruyama, Hiroyuki Kozuki, Katsuya Ikemoto
  • Publication number: 20140118175
    Abstract: The successive approximation A/D converter includes: switch groups 105ā€”1 to 105ā€”x each of which is connected to the other end of each corresponding capacitor of capacitors 106ā€”1 to 106ā€”x to selectively switch a capacitor to be applied to a successive comparison in response to a switch group control signal Ct1; a comparator 104 for making a successive comparison of a comparison voltage VSN based on a holding voltage on each corresponding capacitor, selected through the switch groups from among the capacitors, with a predetermined reference voltage VC in synchronization with a timing control signal CLK to obtain a judgment output according to the comparison result; and a voltage application part 107 for applying a predetermined voltage to the comparison voltage based on a form-of-voltage application control signal Ct2 for a predetermined period when a predetermined time has elapsed after the successive comparison.
    Type: Application
    Filed: October 22, 2013
    Publication date: May 1, 2014
    Applicant: Asahi Kasei Microdevices Corporation
    Inventor: Junya NAKANISHI
  • Publication number: 20140104086
    Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.
    Type: Application
    Filed: January 30, 2013
    Publication date: April 17, 2014
    Applicant: Broadcom Corporation
    Inventors: Bo Zhang, Ali Nazemi, Mahmoud Reza Ahmadi, Afshin Momtaz, Heng Zhang, Hassan Maarefi
  • Patent number: 8614756
    Abstract: An apparatus for acquiring an i-bit digital code by a first stage AD conversion and a j-bit digital code by a second stage AD conversion includes a comparing unit which compares a reference signal and an analog signal in the first stage AD conversion; and an amplifying unit for outputting an amplified residual signal acquired by amplifying a difference between the analog signal and an analog signal corresponding to the i-bit digital code. The comparing unit compares the amplified residual signal and the reference signal in the second stage AD conversion.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: December 24, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Daisuke Yoshida
  • Patent number: 8599058
    Abstract: Systems, methods and computer program products for correcting polarity decision associated with a polarity comparator in an analog-to-digital converter are described. The polarity comparator may perform polarity decision to determine whether an analog signal is greater or smaller than zero. If the voltage difference is greater than zero, then the analog signal may be output to other comparators without polarity inversion. If the voltage difference is smaller than zero, then the signal polarity of the analog signal may be inverted before being output to other comparators. One or more redundant comparators also may be used to correct offsets of the polarity comparator to reduced errors associated with the polarity decision.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: December 3, 2013
    Assignee: Marvell International Ltd.
    Inventor: Yingxuan Li
  • Patent number: 8587707
    Abstract: A DA converter includes: a reference current generating circuit that generates a reference current; current sources that supply currents according to the reference current; a voltage output circuit that outputs a voltage according to a current to be supplied thereto; switch circuits provided for the current sources respectively to each switch a connection of each of the current sources to the voltage output circuit or a predetermined load; a control section that controls the switch circuits based on an input digital signal to select that of the current sources which is to be connected to the voltage output circuit, and outputs a voltage according to the digital signal from the voltage output circuit; and a switch that stops an operation of at least one of the current sources based on a control signal from the control section, without stopping an operation of the reference current generating circuit.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: November 19, 2013
    Assignee: Sony Corporation
    Inventors: Shizunori Matsumoto, Chikao Miyazaki
  • Patent number: 8552899
    Abstract: In one embodiment, a method includes receiving a first analog signal at a first input; receiving a second analog signal at a second input; mixing the first analog signal with a first oscillator signal having a first frequency; mixing the second analog signal with a second oscillator signal having a second frequency; converting a sum signal to a digital signal; generating a first control signal based on a first digital value of a first function and the digital signal; and generating a second control signal based on a second digital value of a second function and the digital signal.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: October 8, 2013
    Assignee: Atmel Automotive GmbH
    Inventors: Lourans Samid, Johannes Schaefer, Thomas Janz
  • Patent number: 8547269
    Abstract: An apparatus comprises: a coarse voltage level comparator that generates a coarse voltage level comparison; a folder, a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical; an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: October 1, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Manar Ibrahim El-Chammas
  • Patent number: 8542142
    Abstract: A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: September 24, 2013
    Assignee: Guzik Technical Enterprises
    Inventors: Anatoli B. Stein, Semen P. Volfbeyn, Valeriy Serebryanskiy
  • Patent number: 8519877
    Abstract: A circuit for providing audio signals to a load such as a speaker is provided that uses the speaker or headphone amplifier structure as a current to voltage converter, thereby eliminating a separate current to voltage converter from the circuit. Such a design removes one of the elements that creates noise in the circuit architecture and improves the dynamic range for the audio signal. For example, the output of a digital to analog converter is a single ended output provided to the speaker or headphone amplifier. The digital to analog converter can include a series of current sources that are summed up to provide the single ended output. Where the current sources have positive and negative current source mismatch, a feedback mechanism is employed to correct for the mismatch and reduce introduction of harmonic noise into the signal through the digital to analog converter.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: August 27, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Shailendra Kumar Baranwal
  • Patent number: 8508397
    Abstract: A device for expanding the dynamic range of a broadband analog/digital converter is provided. The device comprises a splitter module configured to split an analog input signal into a first analog signal output on a first signal branch, and a second analog signal output on a second signal branch. The device further comprises a first analog/digital converter configured to digitize the first analog signal into a first digital signal, a second analog/digital converter configured to digitize the second analog signal into a second digital signal, and a first switching module configured to switch one of the first signal branch and the second signal branch to an output of the apparatus. The device further comprises a first regulating module, disposed between the second analog/digital converter and the first switching module, wherein the first regulating module is configured to adaptively match amplitudes of the second digital signal to amplitudes of the first digital signal.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: August 13, 2013
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Martin Hisch
  • Patent number: 8508635
    Abstract: In a solid-state imaging device, each of a plurality of switches is connected between a pulse output terminal of each delay unit and a pulse input terminal of the next-stage delay unit. Each of a plurality of switches is connected between the pulse output terminal and the pulse input terminal of each delay unit. A plurality of switches is turned on and a plurality of switches is turned off in conjunction with an oscillation operation, and a plurality of switches is turned off and a plurality of switches is turned on in conjunction with a holding operation.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: August 13, 2013
    Assignee: Olympus Corporation
    Inventor: Takanori Tanaka
  • Patent number: 8508393
    Abstract: An analog-to-digital conversion apparatus includes: a first analog-to-digital converter configured to convert an input analog signal into a digital signal; a second analog-to-digital converter configured to convert an analog signal generated by multiplying the input analog signal by ? times with a coefficient ? into a digital signal; a first non-linear compensation part configured to compensate a non-linear distortion of a first output signal of the first analog-to-digital converter; a second non-linear compensation part configured to compensate a non-linear distortion of a second output signal of the second analog-to-digital converter; and a non-linear detection part configured to estimate how much the non-linear distortions of the first and second analog-to-digital converters are compensated by the first and second non-linear compensation parts depending on first and second signals by the first and second non-linear compensation parts.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: August 13, 2013
    Assignee: Sony Corporation
    Inventor: Yosuke Ueno
  • Publication number: 20130201048
    Abstract: There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by ā€œ2?nā€; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.
    Type: Application
    Filed: December 17, 2012
    Publication date: August 8, 2013
    Applicant: KABUSHKI KAISHA TOSHIBA
    Inventors: Junya MATSUNO, Tetsuro ITAKURA
  • Patent number: 8503515
    Abstract: An integrated circuit chip implements a high-speed switch that includes: a switch fabric; control logic that controls the transmission of digital signals through the switch fabric; a transceiver block comprising one or more transceivers, each transmitting digital signals between the control logic and a corresponding external device; a data converter physical interface comprising one or more data converters, each performing a conversion between analog and digital signals, wherein digital signals associated with the one or more data converters are routed through the switch fabric; and a signal processing engine coupled to the control logic, wherein the signal processing engine performs on-chip processing of digital signals received from the transceiver block and the data converter physical interface.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: August 6, 2013
    Assignee: Integrated Device Technology Inc.
    Inventor: Kiomars Anvari
  • Patent number: 8503514
    Abstract: A high-speed switch that includes a switch fabric, and both high-speed serial ports and data converter physical ports. A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric in accordance with a serial data protocol. A second set of data converter physical ports may perform digital-to-analog conversions, such that an internal digital signal received from the switch fabric may be converted to an analog output signal on the switch. The converted analog output signal may then be transmitted to an external destination in accordance with a serial data protocol.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: August 6, 2013
    Assignee: Integrated Device Technology Inc.
    Inventor: Kiomars Anvari
  • Patent number: 8502899
    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage Vx are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage Vx, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become ?W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: August 6, 2013
    Assignee: Sony Corporation
    Inventors: Hayato Wakabayashi, Masaru Kikuchi, Hiroshi Iwasa, Yuuki Yamagata
  • Patent number: 8497794
    Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 30, 2013
    Assignee: Sony Corporation
    Inventors: Shinichirou Etou, Yasuhide Shimizu, Kouhei Kudou, Yukitoshi Yamashita
  • Patent number: 8487600
    Abstract: The present invention is a voltage mode digital controller for low-power high-frequency dc-dc converters that has recovery time approaching physical limitations of a given power stage. It consists of a digital controller with load transient response approaching physical limitations of a given power stage that is suitable for low-power SMPS. In one aspect the invention is a method of utilizing a continuous-time digital signal processor (CT-DSP) for regulation of the operation of switch-mode power supplies. A CT-DSP can be used to instantaneously detect changes of voltage or current during transition periods and immediately perform control action that results in the fastest possible response. The invention may include current program mode controllers for SMPS where the input current is sensed as well as power factor correction rectifiers (PFC), where often input voltage, input current and output voltage are sensed.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: July 16, 2013
    Inventors: Aleksandar Prodic, Zhenyu Zhao
  • Patent number: 8466823
    Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 18, 2013
    Assignee: University of Macau
    Inventors: U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
  • Patent number: 8462037
    Abstract: An adaptive Analog to Digital Converter (ADC) that adjusts the representation levels used in the conversion process so as to optimize system performance. By establishing system performance criteria by which to select or adjust the signal value range associated with each digital representation and/or the digital representation, substantially fewer bits may be used in the ADC. The systems and methods described herein enable lower-power, smaller form-factor designs as well as very high-speed operation. In particular, this technology may be beneficial for use in communications systems because it enables ADC's to operate at speeds where traditional ADC designs simply cannot.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: June 11, 2013
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Andrew Carl Singer, Naresh Shanbhag
  • Patent number: 8456347
    Abstract: An analog-to-digital converter including a voltage generation unit and a plurality of sub ADCs, each including a selection unit for selecting a voltage generated by the voltage generation unit based on a number and forwarding the selected voltage to a comparator arrangement. The selection unit includes first and second switch layers. The first switch layer includes a plurality of switch groups, each including a plurality of switch devices, each connected to a unique output terminal of the voltage generation unit with a first terminal and to a common node of the switch group with a second terminal. The second switch layer includes a switch device between the common node of each switch group and the first output terminal of the selection unit and a switch device between the common node and the second output terminal of the selection unit. A control unit generates control signals for the switch devices.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: June 4, 2013
    Assignee: CSR Technology Inc.
    Inventor: Jacob Wikner
  • Patent number: 8432304
    Abstract: A thermometer coded line is configured to convert a time interval to a digital code for subsequent processing in order to output a value representative of said time interval. A digital peak detector is coupled to receive output from the thermometer coded line, the detector operating for correction of an undesired code of said digital code in order to ensure a valid output of said value. A majority logic circuit is coupled between the thermometer coded line and the digital peak detector, the logic circuit operating for correction of undesired code of said digital code in order to ensure the valid output of said value. The detector functions to correct any undesired code not corrected by, or introduced by, the logic circuit.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 30, 2013
    Assignee: STMicroelectronics (Research & Development) Ltd
    Inventor: Neale Dutton
  • Patent number: 8427353
    Abstract: Disclosed is at least one flash analog-to-digital converter embodiment having a linear voltage ladder, a set of comparators each of which is coupled to one or more operational amplifiers by a sampling switch. Each of the sampling switches samples the comparator output, using the parasitic capacitance of the operational amplifier to hold the voltage. The sampling switches may be single transistors. Some embodiments further include, for each comparator, multiple operational amplifiers each of which drives a binary latch via a gating switch. The gating switches operate in sequence to distribute sequential samples to different latches. At least some embodiments of the flash converter further include an automatic gain control (AGC) that has both differential input terminals and differential output terminals. In such embodiments the comparators compare the differential output of the AGC to a differential reference voltage, and may further provide the result as a differential signal.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: April 23, 2013
    Assignee: Credo Semiconductor (Hong Kong) Limited
    Inventor: Lawrence Chi Fung Cheng
  • Patent number: 8421891
    Abstract: An A/D conversion apparatus according to the present invention for comparing a reference signal with an analog signal, and when the reference signal matches with the analog signal, outputting a corresponding digital value, is provided, and the A/D conversion apparatus includes a gray code counter for generating the digital value from a reference clock or a reverse clock of the reference clock, and uses a gray code, in which a most significant bit to a second least significant bit of the digital value is a count value of the gray code counter and a least significant bit of the digital value is generated from the reference clock or the reverse clock thereof and defined as a least significant bit of the gray code counter.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshinao Morikawa, Makoto Shohho
  • Publication number: 20130076551
    Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.
    Type: Application
    Filed: June 27, 2012
    Publication date: March 28, 2013
    Inventors: Takao MARUKAME, Tetsufumi Tanamoto, Atsuhiro Kinoshita, Tomoaki Inokuchi, Masamichi Suzuki, Yoshiaki Saito
  • Patent number: 8390498
    Abstract: First and second resistor series divide a predetermined voltage range to generate first reference voltages and second reference voltages, respectively. First and second switch controlling circuits select respective ones of the first reference voltages and the second reference voltages. A comparing unit generates a logical signal representing a logical value by comparing a combined transistor current based on the selected first and second reference voltages with a transistor current based on an input signal. The first switch controlling circuit specifies two adjacent first reference voltages where the logical value is inverted by sequentially selecting the first reference voltages, and determines to select one of the adjacent reference voltages. Te second switch controlling circuit specifies two adjacent second reference voltages where the logical value is inverted by sequentially selecting the second reference voltages, and determines to select one of the adjacent reference voltages.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiko Ito, Tetsuro Itakura
  • Patent number: 8390499
    Abstract: An analog-to-digital converter includes an input terminal, a first comparator, a first output terminal, a second comparator, and a second output terminal. The first comparator generates a first logical signal and a control signal by comparing an input signal received by the input terminal with a first reference signal. A first transistor generates a first current based on the input signal. First and second switches are switched so as to be short-circuited/open-circuited in an opposite manner to each other based on the control signal. A second transistor supplies a second current based on a second reference signal to a terminal when the first switch is ON. A third transistor supplies a third current based on a third reference signal to the terminal when the second switch is ON. An output unit generates a second logical signal by comparing the first current with one of the second and the third currents.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomohiko Ito
  • Publication number: 20130044017
    Abstract: An A-type converter circuit compares an input voltage with multiple threshold voltages, judges which segment it belongs to, and generates first and second voltages with the input voltage segment between them. The A-type converter circuit generates third and fourth voltages by amplifying the differences between the first and the input voltages and between the second and the input voltages. A B-type converter circuit divides the range between the third and fourth voltages into multiple segments, and judges which segment includes the common voltage. Subsequently, the B-type converter circuit generates fifth and sixth voltages with the common voltage segment between them. The B-type converter circuit generates a seventh (the next stage's third voltage) and an eighth voltage by amplifying the differences between the fifth and the common voltages and between the sixth and the common voltages.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 21, 2013
    Applicant: TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Akira Matsuzawa, Masaya Miyahara
  • Patent number: 8378874
    Abstract: An analog to digital converter for operating at high speeds can be implemented with a micro-comparator/sampler, an encoder, and a selector. The micro-comparator includes an input from an antenna of a receiver/transceiver system; a transistor pair; reset transistor; cascaded inverters; an inverter circuit; a buffer; and a D flip flop circuit. Depending on the number of micro-comparator/samplers placed in parallel, a number of bits can be generated. For example, 15 bits from 15 different micro-comparator/samplers can be inserted into a 15 to 4 bit encoder to generate 4 bits.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: February 19, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Stephane Pinel, Joy Laskar
  • Patent number: 8373587
    Abstract: A semiconductor integrated circuit includes first to N-th comparators to compare an input voltage with a threshold value; and a control circuit to perform first and second operations, set a threshold value of the first comparator as a first threshold value, and set a threshold value of an M-th comparator as a second threshold value, wherein the first operation includes an operation where a value obtained by multiplying a value obtained by subtracting the threshold value of the M-th comparator from a threshold value of an (M+1)th comparator by a real number is added to the threshold value of the M-th comparator, and wherein the second operation includes an operation where a value obtained by multiplying a value obtained by subtracting the threshold value of the M-th comparator from a threshold value of an (M?1)th comparator by a real number is added to the threshold value of the M-th comparator.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: February 12, 2013
    Assignee: Fujitsu Limited
    Inventor: Sanroku Tsukamoto
  • Patent number: 8344927
    Abstract: Provided are an analog digital converting device and a reference voltage controlling method thereof. The analog digital converting device includes: a first reference voltage generating circuit generating a first reference voltage; a second reference voltage generating circuit generating a second reference voltage; a first sub analog digital converter receiving an analog input signal and converting the analog input signal into a first digital signal by using the first reference voltage; an amplifier converting the first digital signal into a voltage corresponding to the first digital signal by using the first reference voltage and amplifying a difference between a voltage level of the analog input signal and a voltage level corresponding to the first digital signal to output a residual signal; and a second sub analog digital converter receiving the residual signal and converting the residual signal into a second digital signal by using the second reference voltage.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 1, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Young-deuk Jeon
  • Patent number: 8330632
    Abstract: Calibration of an analog-to-digital converter (ADC) is accomplished via a reference comparator, a first and second multiplexer (MUX), and a finite state machine (FSM). By sampling an analog input with the reference comparator and comparing the results with those of the ADC using the FSM, all the comparators in the ADC can be calibrated without interrupting the ADC's normal operation. The first MUX provides a same reference voltage to the reference comparator as a comparator selected for the calibration, and the second MUX provides the FSM with the output of the selected comparator. The FSM then performs a comparison of the reference comparator and the selected comparator, extracts the polarity of the mismatch, and updates the contents of a memory with the extracted polarity. An offset control in the selected comparator receives a signal corresponding to the extracted polarity stored in the memory and injects offset current into the comparator.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: December 11, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Rizwan Bashirullah, Jikai Chen
  • Patent number: 8325073
    Abstract: In general, techniques are described for performing enhanced sigma-delta modulation. For example, an apparatus comprising a predictive filter unit, an amplifier, an oversampling unit and a sigma-delta modulation unit may implement the techniques. The predictive filter unit performs predictive filtering on an input signal to generate a filtered signal and computes an estimate of a predictive gain as a function of an energy of the input signal and an energy of the filtered signal. The amplifier receives the filtered signal and amplifies the filtered signal based on the predictive gain to generate an amplified signal. The oversampling unit receives the amplifies signal and performs oversampling in accordance with an oversampling rate to generate an oversampled signal. The sigma-delta modulation unit receives the oversampled signal and performs sigma-delta modulation to generate a modulated signal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: December 4, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Chong U. Lee, Yuriy Reznik, John H. Hong
  • Patent number: 8310387
    Abstract: A wide band analog-to-digital converter used in a frequency multiplexed communication system. The converter includes a plurality, M, of time-interleaved analog-to-digital converter subunits (ADC subunits). The sampling rate, FS1, of the M ADC subunits is selected to locate one or more integer multiples of a Nyquist frequency of a respective subunit ADC in one or more guard bands, and/or such that one or more integer multiples of FS1 are also located in the guard bands.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: November 13, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Brannon Harris, Sunder S. Kidambi, Michael P. Anthony
  • Patent number: 8284091
    Abstract: An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical response to the reference voltage (16) and the input signal and is due to an internally arising offset. An adder (25) determines a sum of the outputs of the set of comparators and conversion logic (27) generates an output digital signal dependent on the determined sum. Multiple sets of comparators can be provided, each set having a different respective reference voltage.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: October 9, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Hendrik Van Der Ploeg, Erwin Janssen, Konstantinos Doris