Abstract: A resistor-ladder voltage generator circuit is provided, which controls so that k switches among consecutive (k+1) switches out of a plurality of switches connected to the resistor ladder circuit are simultaneously set to an ON state, and which temporally switches the value of k. This allows voltage waveforms having different slopes to be arbitrarily obtained, ranging from a voltage waveform having a small slope to a voltage waveform having a large slope, thereby improving the resolution of a generated voltage waveform without increasing the numbers of resistors and switches, while A/D conversion time is not increased even if the number of bits is increased. In addition, by using this voltage generator circuit as a ramp generator circuit, and by dynamically switching the slope of the ramp wave, acceleration of an image sensor is achieved.

Abstract: An analog-to-digital converter generates an output digital value equivalent to the difference between two analog signals. The converter forms part of a set of converters. The converter receives a first analog signal and a second analog signal (Vreset, Vsig) and a ramp signal (Vramp). A clock is dedicated to the converter, or a sub-set of converters. A control stage enables a first counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. The converter can be calibrated by at least one reference signal (Vref1, Vref2) which is common to the set of converters.

Abstract: An integrated circuit comprises a plurality of sensing circuits (12), each for detecting whether a respective physical operating parameter is above or below a respective reference value. The integrated circuit contains a serial shift register (11) for shifting digital data signals that represent the respective reference values from a successive approximation update circuit (14) to the sensing circuits (12) and back to the successive approximation update circuit (14). Detection results of the sensing circuits (12) are shifted to the successive approximation update circuit (14) with the digital data signals. The successive approximation update circuit (14) is used to form the digital data so that the reference values form successive approximations of the physical operating parameter values during an analog to digital conversion process. In this way the successive approximation update circuit (14) is shared by a plurality of sensing circuits (12).

Abstract: A row scanner selects an arbitrary row in an pixel array unit. Per-column AD converters separately convert voltage signals respectively outputted from a column of a plurality of unit pixels in the selected arbitrary row into digital signals. A column scanner sequentially outputs the digital signals by a column-scanning operation thereof. An AD conversion result adjuster judges whether or not the digital signals reach a predetermined judgment value or the status equivalent to the digital signals reaching the predetermined judgment value is generated, and fixes the digital signals to digital pixel values set in accordance with the predetermined judgment value when a result of the judgment is positive.

Abstract: An analog-to-digital (ADC) converter is disclosed that uses aspects of a single-slope ramp ADC, but with jump steps in the ramp voltage to increase speed. A look-ahead controller can cause a ramped voltage level to jump step and detect the number of analog input signals impacted due to the jump step. If the detected number is below a predetermined threshold, the ramp can be maintained from the new voltage level after the jump. If the detected number is above the predetermined threshold, the ramped voltage level can be returned to its original voltage level and trajectory. Thus, jump steps can be used to increase speed, but dynamic testing can be performed to ensure that error rates due to the jump step are minimized.

Abstract: According to one embodiment, an A/D converter includes a determination circuit configured to determine whether a first analog signal is greater than a second analog signal or not, the first analog signal being a present A/D conversion target, the second analog signal being an immediately preceding A/D conversion target, a calculation circuit configured to add a reference voltage to a difference obtained by subtracting the second analog signal from the first analog signal, a generation circuit configured to generate a comparison voltage, a comparator configured to compare a calculated value of the calculation circuit with the comparison voltage, and a conversion circuit configured to convert a period into a digital signal, the period being required until the calculated value is identical with the comparison voltage by the comparator.

Abstract: The present invention provides a method in which a counting source is provided in data after analog/digital conversion to lessen a load placed when new and old data after the conversion are compared to each other. A log function is prepared in an A/D conversion controlling circuit. The log function latches the output of a counter in a 12-bit digital/analog converter at the timing of outputting a pulse from a comparator to determine data written into a data register group. In the case where a setting item related to log output in an ADCR is set at 1, not only the output of the 12-bit digital/analog converter, but also the output of a timer counter of an MTU is latched as a log.

Abstract: A system and method are disclosed for monitoring environmental conditions of a perishable product. The system includes an environmental sensor configured to sense one or more environmental conditions of the perishable product and an analog integrator in communication with the environmental sensor, the analog integrator being formed on a polymer substrate and including one or more tunable components. The system also includes a comparator in communication with the analog integrator and configured to change state when an output of the analog integrator reaches a selected threshold level, and a control module in communication with the comparator and the analog integrator. The control module is configured to control the operation of the analog integrator based on an output of the comparator.

Abstract: An image processing method for obtaining digital data comprising the steps of obtaining a plurality of image signals under a condition of different accumulation periods as an initial value for a counting operation, comparing, by using digital data for a first image signal of the plurality of image signals, an electric signal corresponding to a second image signal of the plurality of image signals with a reference signal, obtaining digital data for the second image signal, performing a counting operation in a mode having the same sign as the sign of digital data for the first image signal between a down-counting mode and an up-counting mode while the comparing step is being performed, and storing a count value.

Abstract: More accurate signal detection circuitry in serial interfaces, particularly on a programmable integrated circuit device, such as a PLD, includes a high-speed, high-resolution, high-bandwidth comparator, along with digital filtering, to reduce the effect of process, temperature or supply variations. The comparator is used to compare a direct input signal with a programmable reference voltage, and, in a preferred embodiment, can detect the signal level within 8 mV accuracy. The output of the comparator may then be digitally filtered. Preferably, both a high-pass digital filter and a low-pass analog filter may be used to eliminate glitches and low-frequency noise. Preferably, the digital filters are programmable to adjust the sensitivity to noise. The filtered output is then latched and output to indicate receipt or loss of signal. This signal detect circuitry can operate reliably at data rates as high as 7 Gbps.

Abstract: An analog-to-digital converter includes a ½ powered signal generator configured to generate divided signals by successively dividing a full scale signal by 2 and output one of the divided signals, an accumulator configured to update a reference signal according to a current divided signal and a current output bit, and a comparator configured to compare the updated reference signal with an input signal and generate a next output bit.

Abstract: A data processing apparatus and method is disclosed for obtaining digital data for a plurality of signals to be processed, comprising. The disclosed process includes comparing, by using digital data for a first signal of the plurality of signals, an electric signal corresponding to a second signal of the plurality of signals with a reference signal; obtaining digital data for the second signal based on the comparing step; performing a counting operation in one of a down-counting mode and an up-counting mode while the comparing step is being performed; storing a first count value; outputting the first count value as computed data at a predetermined time; generating normal data based on one of the plurality of signals to be processed; and outputting the normal data.

Abstract: A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC.

Abstract: In a solid-state imaging device with an AD converter mounted on the same chip, to enable an efficient product-sum operation while reducing the size of the circuit scale and the number of transmission signal lines. A pixel signal during an n-row readout period is compared with a reference signal for digitizing this pixel signal, and a counting operation is performed in one of a down-counting mode and an up-counting mode while the comparison processing is being performed, and then, the count value when the comparison processing is finished is stored. Subsequently, by using the n-row counting result as the initial value, a pixel signal during an (n+1)-row readout period is compared with the reference signal for digitizing this pixel signal, and also, the counting operation is performed in one of the down-counting mode and the up-counting mode, and then, the count value when the comparison processing is finished is stored.

Abstract: A solid-state imaging device including: an analog-digital converter unit in column parallel arrangement, the analog-digital converter unit having a plurality of pixels arranged to convert an incident light quantity to an electric signal, in which an analog signal obtained from the pixel is converted into a digital signal, wherein the analog-digital converter unit is configured of: a comparator operable to compare a value of a column signal line from which an analog signal obtained by the pixel is outputted with a value of a reference line, and a counter operable to measure a time period by the time when comparison done by the comparator is finished and to store the comparison result, wherein the solid-state imaging device further includes: a module for controlling an output of the comparator operable to control the output of the comparator depending on the output of the comparator.

Abstract: A peak detector provides repeatable and accurate measurements of the signal amplitude for variable frequencies of input signals. The peak detector includes a pulse edge generator circuit that generates a pulse edge signal in response to the signal peaks of an input signal and a sampler circuit that is triggered to sample the input signal by the pulse edge signal. The pulse edge generator circuit compares the input signal with a delayed version of the input signal to produce a differential signal and generates the pulse edge signal using the differential signal. An analog or digital sampler is triggered by the pulsed edge signal to measure the information, e.g., peak value, of the input signal. One or more delay circuits may be used to align the edges of the pulsed edge signal with the peaks of the input signal.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.

Abstract: Systems, methods, and devices are disclosed, such as an integrated semiconductor device that may include a data location coupled to an electrical conductor, a delta-sigma modulator coupled to the electrical conductor, a counter coupled to an output of the delta-sigma modulator, and an interfuser coupled to an output of the counter. In some embodiments, the interfuser is configured to receive two or more counts from the counter and read data conveyed by the data location based on the two or more counts.

Abstract: A circuit including a comparing unit for comparing a target voltage with a stepwise-varying tracking voltage, a counting unit for counting a code according to the comparison result of the comparing unit and a control signal generating unit for generating a signal for controlling a counting operation of the counting unit.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Abstract: Apparatus for the analog/digital conversion of a measurement voltage with an analog/digital converter, which has an integrating component with an operational amplifier, a resistor and a capacitor in a feedback loop, wherein a reference voltage is applied to the inverting input of the operational amplifier and wherein the measurement voltage is applied to the non-inverting input of the operational amplifier The capacitor is charged during a charging phase of time length (t1) and discharged during a discharging phase of time length, wherein the analog/digital converter further includes a comparator connected downstream from the operational amplifier, a memory element connected downstream from the comparator, a time generator producing the charging time and a counter, the counter detects the edges, or the period length of the pulse-width modulated output signal provided by the A/D converter on the output, and a synchronizing element is provided, which synchronizes the edges of the pulse-width modulated, output s

Abstract: A solid-state image pick up device including a pixel array unit having unit pixels arranged in a matrix pattern. Each unit pixel includes a photoelectric converter. Additionally, the solid-state image pick up device has column signal lines that correspond to the respective columns of the matrix pattern, a row scanning means for selectively controlling each unit pixel, and an analog-digital converting unit for converting analog signals output from the unit pixels in a row selectively controlled by the row scanning means. The analog-digital converting unit further includes an asynchronous counter which performs counting in two modes and the asynchronous counter includes a counter processor configured so that when switching between the count modes occurs, a running count value is broken and there is an interval between the count modes and when a mode begins the running count value is reset to the value before the running count value was broken.

Abstract: A time-to-digital converter (TDC) is disclosed, the TDC comprising: a plurality of parallel circuits for receiving a common first clock and for generating a plurality of delayed clocks; a plurality of sampling circuits for receiving and sampling said delayed clocks at an edge of a second clock to generate a plurality of decisions, respectively; and a decoder for receiving said decisions and for generating a digital output accordingly.

Abstract: An A/D converter comprises a ramp voltage generation circuit, a voltage comparison circuit comprising an arithmetic unit comparing an analog voltage to be converted with a reference voltage showing the voltage change of a ramp voltage, and changing an output when the reference voltage equals the analog voltage, a counter counting and outputting a digital value corresponding to the reference voltage, a latch circuit latching and outputting the digital value when the output of the voltage comparison circuit changes, an averaging process circuit to obtain an average noise voltage, a target noise voltage setting circuit setting a target noise voltage, and a control circuit adjusting at least one of a counting start timing of the counter with respect to a control reference timing, or the criterion level of the reference voltage at the counting start timing, based on a difference between the average noise voltage and the target noise voltage.

Abstract: An A/D conversion circuit includes: an input capacitance to which an input signal and a reference signal are sequentially applied; an operational amplifier; a first switch connected between the other end of the input capacitance and a first input end of the operational amplifier; a feedback capacitance connected to the first input end of the operational amplifier; a second switch connected between the other end of the feedback capacitance and an output end of the operational amplifier; a third switch selectively applying a predetermined voltage to the other end of the feedback capacitance; a fourth switch selectively causing a short circuit between the first input end and the output end of the operational amplifier; a fifth switch applying the predetermined voltage to a second input end of the operational amplifier; and a sixth switch applying a ramp reference voltage to the second input end of the operational amplifier.

Abstract: An analog-to-digital converter (ADC) is presented. The ADC includes an error amplifier, a ramp generator, and a counting circuit. The error amplifier is used for receiving an output voltage and a reference voltage, and amplifying a difference between the output voltage and the reference voltage, so as to obtain a first voltage and a second voltage. The ramp generator is used for generating a ramp voltage which is increased along with time. The counting circuit is used for starting counting a digital value when the ramp voltage is larger than or equal to the first voltage, and stopping counting and outputting the digital value when the ramp voltage is larger than or equal to the second voltage.

Abstract: A comparator with an input stage that selectively powers up an output stage provides an electronic device with a comparator that operates at low power. In an embodiment, an input stage produces a near decision and a true decision, where the near decision is provided to power up an output stage for the comparator to provide an output representative of the true decision.

Abstract: An on die thermal sensor (ODTS) in a memory device includes: a band gap unit for detecting a temperature of the memory device to output a first voltage corresponding to the temperature; and an analog-to-digital converting unit for outputting a digital code having temperature information based on the first voltage, the digital code having varied resolution according to temperature ranges.

Abstract: An A/D converter comprises a sample and hold circuit receiving a signal and operating based on a sampling clock, an A/D converting circuit converting an output signal of the sample and hold circuit to a digital signal, an A/D output determination circuit outputting a duty control signal based on the digital signal and a sampling clock generator adjusting a duty ratio of a sampling clock and applying the sampling clock to the sample and hold circuit.

Abstract: An analog-to-digital converter that converts an analog input signal into a digital signal includes a comparator configured to compare a reference signal with an input signal and, if the input signal matches the reference signal, inverts an output; a counter configured to count a comparison time of the comparator; a control circuit configured to monitor the output of the comparator; a voltage generating circuit configured to generate, if a monitoring result obtained by the control circuit indicates that the output of the comparator is at a predetermined level, a direct current voltage in accordance with the monitoring result; and an analog adder configured to add the voltage generated by the voltage generating circuit to the input signal and supply a sum signal to an input terminal of the comparator.

Abstract: An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.

Abstract: An analog to digital converter (ADC) with interference rejection capability and method thereof are disclosed. The ADC includes a threshold generator, a comparator circuit, a counter and an integrator. By comparing a signal with positive and negative threshold signals from the threshold generator, the comparator circuit converts the signal from analog to digital based on the result of the comparison. The counter counts a percentage of the digital signal and generates a bit signal based on the counted percentage. In response to the bit signal, the integrator supplies a control signal to the threshold generator to regulate the positive and negative threshold signals so as to maintain the counted percentage at a predetermined percentage threshold.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Abstract: A comparator is provided that outputs a comparison result obtained by comparing two signals.

Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that at low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: An analog voltage latch for use in a controller for controlling a motor equipped electric bicycle, includes a window comparator for comparing an analog voltage latch output and an analog input voltage to produce a comparison result, an S-R latch for producing HIGH or LOW according to the comparison result, a selector for selecting an operation, an up/down counter for counting up or down according to the HIGH or LOW from the S-R latch, and holding the counted result according to the selector result, and a DA converter for converting the counted result to analog signal.

Abstract: An On Die Thermal Sensor (ODTS) of a semiconductor memory device includes: a temperature detector for detecting an internal temperature of the semiconductor memory device to generate a temperature voltage corresponding to the detected internal temperature; a tracking ADC for outputting a digital code by comparing the temperature voltage with a tracking voltage and performing a counting operation to the result of comparison; and an operation controller for controlling operations of the temperature detector and the analog-to-digital converter, wherein the tracking ADC performs the counting operation using a first tracking scheme having a relatively large unit variation width of the digital code value during an initial tracking period and a second tracking scheme having a relatively small unit variation width of the digital code value after the initial tracking period.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: An analog to digital converter comprising a reference signal generator, a comparator, and a counter wherein the reference signal generator is operable to generate a reference for converting an analog signal into a digital signal. The reference signal generator is also operable to generate a plurality of the reference signals based on the change in a voltage. The comparator is operable to compare the analog signal with the reference signal generated by the reference signal generator. The counter is operable to count, in parallel with a comparison performed by the comparator, a predetermined count clock and to hold a count value at the time of completion of the comparison.

Abstract: A detector circuit having an integration capacitor coupled to an amplifier via a switch matrix and a comparator coupled to the amplifier, the integration capacitor operable in two or more phases, the switch matrix is configured to phase switch the integration capacitor, the comparator triggers the phase switch when the output voltage of the amplifier passes the threshold voltage of the comparator.

Abstract: In an analog-to-digital conversion method for converting a difference signal component representing a difference between a reference component and a signal component in an analog signal to be processed into digital data, in a first process, a signal corresponding to one of the reference component and the signal component is compared with a reference signal for conversion into the digital data. Concurrently with the comparison, counting is performed in one of a down-count mode and an up-count mode, and a count value at a time of completion of the comparison is held. In a second process, a signal corresponding to the other one of the reference component and the signal component is compared with the reference signal. Concurrently with the comparison, counting is performed in the other one of the down-count mode and the up-count mode, and a count value at a time of completion of the comparison is held.

Abstract: A detector comprises an analog-to-digital converter. The analog-to-digital converter comprises an input for an analog receive signal and an output for a digital signal. The detector further comprises an edge detector. The edge detector comprises an input for a digital signal and an interface for an edge detection information. The edge detection information indicates the presence of an edge, if the digital signal indicates a change which is larger than or equal to a change threshold value.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.

Abstract: An analogue-to-digital converter comprises a window comparator. The window comparator comprises an input for an analogue input signal and an output for a comparison result indicating a result of a comparison of the analogue input signal with an upper bound and a lower bound of a level window. The analogue-to-digital converter further comprises a level window position signal generator. The level window position signal generator comprises an output for a level window position signal adjusting a position of the level window based on an information derived from the comparison result and indicating whether the level window should be increased, decreased or maintained. The analogue-to-digital converter further comprises an output for a digital information based on the comparison result.

Abstract: An analog-to-digital converter with calibration is provided. The converter includes at least one conversion unit. The conversion unit includes a comparator, a control unit, a count unit, and a calibration unit. The comparator compares the voltage of the first input terminal with the voltage of the second input terminal and outputs a comparison result. The control unit outputs a control signal according to a comparison result of the comparator and a selecting signal. The count unit performs a count operation according to the control signal and outputs a count result. The calibration unit provides a reference voltage to the second input terminal of the comparator, and adjusts the level of the reference voltage according to the count result of the count unit. Thus, reference voltage is included inside each conversion unit and conventional resistor ladder producing reference voltage can be removed.

Abstract: An A/D converter has a first voltage generation circuit, a second voltage generation circuit, a comparator, first and second switch circuits connected in series between an input terminal of an analog input voltage and an output terminal of the first voltage generation circuit, a first capacitor inserted between a connection node between the first and second switch circuits and the first input terminal, a second capacitor inserted between an output terminal of the second voltage generation circuit and the second input terminal, a third switch circuit, a fourth switch circuit, an A/D converter which generates a digital signal in accordance with signal level of the first output terminal, and a voltage setting circuit which sets a voltage to be outputted from the first and second voltage generation circuits based on the digital signal.

Abstract: An analog level meter and a method of measuring an analog signal level may be provided. The analog level meter may include a comparator, a duty counter, an analog level detector and/or a digital to analog converter (DAC). The comparator may compare a voltage level of the analog signal with a reference voltage and generate an up-down signal. The duty counter may count a duty value of the up-down signal. The analog level detector may output a duty error value obtained by subtracting a target duty value from the duty value of the up-down signal. The analog level meter may output the reference voltage as a measured value of the analog signal when the duty error value is a desired or predetermined value.

Abstract: In an analog-to-digital conversion method for converting a difference signal component representing a difference between a reference component and a signal component in an analog signal to be processed into digital data, in a first process, a signal corresponding to one of the reference component and the signal component is compared with a reference signal for conversion into the digital data. Concurrently with the comparison, counting is performed in one of a down-count mode and an up-count mode, and a count value at a time of completion of the comparison is held. In a second process, a signal corresponding to the other one of the reference component and the signal component is compared with the reference signal. Concurrently with the comparison, counting is performed in the other one of the down-count mode and the up-count mode, and a count value at a time of completion of the comparison is held.

Abstract: An image processing circuit for reducing noise. The image processing circuit includes a CDS circuit for taking a potential difference between a pixel signal at a reset of an image pickup device and a pixel signal after exposure, and an AD conversion circuit. The AD conversion circuit includes an increment counter and AD conversion clock provided for the AD conversion of the potential difference of the image pickup device between at a reset and after exposure, and an averaging ADC control circuit for averaging a plurality of digital code values obtained through the AD conversion repeated a plurality of times.