Bit Represented By Pulse Width Patents (Class 341/53)
  • Patent number: 6184916
    Abstract: Multiple pulse width and position modulation methods and systems use multiple pulse width and position modulation (PWPM) circuits driven from the same system clock and video data to provide multiple video pulses per clock period. The multiple pulse width and position modulation methods and systems separately provide extremely fine halftone structures from n-bit per pixel video data words. The halftone structures can be provided without the need for extremely high resolution raster output scanners, associated optics and high speed electronics. The multiple pulse width and position modulation system (PWPM) can produce video pulses of variable width and position within a pixel period with extremely high addressability. The pulses output from multiple, independent pulse width and position modulation (PWPM) channels can be combined to form structured multiple video pulse patterns within the video clock or pixel period from a given n bit video data word.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: February 6, 2001
    Assignee: Xerox Corporation
    Inventor: Michael S. Cianciosi
  • Patent number: 6150963
    Abstract: A method and system produce a PWM signal using a comparator having first and second input terminals and an output terminal at which the PWM signal is produced. The method includes powering the comparator with a supply voltage and receiving a modulating signal at the first input terminal. The method creates a carrier signal with a constant frequency and a maximum amplitude equal to the supply voltage. The comparator receives the carrier signal at the second input terminal and compares the carrier signal to the modulating signal, thereby producing the PWM signal at the output terminal. By creating and using a carrier signal with a maximum amplitude equal to the supply voltage, the PWM signal produced by the method is immune from changes in the supply voltage.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: November 21, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Boscolo, Ezio Galbiati, Marco Vitti
  • Patent number: 6133858
    Abstract: A method for decoding pulse-width modulated signals, such that a sawtooth signal is generated. The sawtooth signal is synchronized with a signal to be decoded. By comparing the sawtooth signal with a reference, a temporal center of a time period reserved for transmission of a bit can be measured, thus reducing a demodulation of the signal to a measurement of the signal level. Furthermore, a data bus for an activation system utilizing this method is also provided.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: October 17, 2000
    Assignee: Robert Bosch GmbH
    Inventors: Otto Karl, Joachim Bauer, Guenther Ott, Dietmar Koehler
  • Patent number: 6118390
    Abstract: An apparatus is provided for processing a pulse signal. The apparatus includes (1) a pulse-shrinking circuit for shrinking a specific quantity of a pulse width of the pulse signal; and (2) a feedback circuit electrically connected to the pulse-shrinking circuit for repetitively feeding the output pulse signal back to the input end of the pulse-shrinking circuit, the shrunk output pulse signal being further shrunk by the pulse-shrinking circuit in order to obtain a feedback number of the pulse signal before the pulse signal is vanished.
    Type: Grant
    Filed: October 10, 1997
    Date of Patent: September 12, 2000
    Assignee: National Science Council
    Inventors: Poki Chen, Shen-Iuan Liu, Jing-Shown Wu, Hen-Wei Tsao
  • Patent number: 6061005
    Abstract: The invention provides a method of encoding data, which includes defining a cell with a predetermined width and defining a plurality of internal signal positions within the cell, wherein the number of internal signal positions relates to the order of a symbology utilised. The invention also relates to an encoding means for encoding data, a method of decoding data, a decoding means for decoding data and a carrier with data encoded thereon.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: May 9, 2000
    Assignee: Microcorp Technologies (Proprietary) Limited
    Inventors: Hendrik Jacobus Van Rooyen, Wilfried Erhard Otto Ilgmann
  • Patent number: 6037884
    Abstract: A technique for encoding multiple digital data streams in a limited bandwidth for transmission in a single medium is described. A pulse tuned to an assigned frequency is generated each time a data stream makes a transition. The polarity of each pulse represents the direction of the corresponding transition. In one aspect, a different length pulse is assigned to each incoming data stream to be encoded such that each incoming data stream will generate pulses of different length, thus occupying a different part of the frequency spectrum. These different pulse lengths create a group of "channels" each representing the activities of a different data stream. in each case, the length of the data pulse is shorter than the length of the fastest individual bit to be processed. The pulses are then summed in an analog summer and transmitted as the new, combined data stream.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: March 14, 2000
    Assignee: INT Labs, Inc.
    Inventor: Barry Thornton
  • Patent number: 6020834
    Abstract: Briefly, in accordance with one embodiment of the invention, a method of transmitting coded data signals over a bus having a limited bandwidth includes: transmitting a first edge of a data pulse and transmitting a second edge of the data pulse. The time period between the transmitted first edge and the transmitted second edge approximates one of a set of different predetermined time periods. Selected different predetermined time periods of the set of different predetermined time periods respectively correspond to unique pluralities of binary digital signals.Briefly, in accordance with another embodiment of the invention, a system comprises a first device, a second device and a bandlimited bus coupling the first device with the second device. At least one of the devices includes the capability to code data signals for transfer over the bus and at least the other device includes the capability to decode the data signals.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: February 1, 2000
    Assignee: Intel Corporation
    Inventor: Scott M. Rider
  • Patent number: 6014093
    Abstract: A pulse coding system is disclosed that includes an encoder for encoding the received analog signal as a series of output pulses, and a decoder for receiving the pulses output from the encoder and for generating an output signal corresponding to the analog signal received by the encoder. The encoder includes a first decaying signal source for generating a decaying reference signal, and a pulse-generating comparator circuit for receiving the analog signal to be encoded as well as the decaying reference signal. The pulse-generating comparator circuit compares the amplitudes of the received analog signal and the reference signal and generates and outputs a pulse whenever the amplitude of the decaying reference signal falls below that of the received analog signal. The first decaying signal source receives the generated pulses and responds to the pulses by increasing the amplitude of the decaying reference signal a predetermined amount each time a pulse is received.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: January 11, 2000
    Inventor: Adam T. Hayes
  • Patent number: 5969646
    Abstract: An improved decoder for recovering Non-Return-to-Zero Interface (NRZI) digital data from a multiple layer transition (MLT-3) encoded signal in a 100BASE-TX Ethernet (IEEE Standard 802.3u) uses multiple comparators to minimize jitter in the decoded signal. A CMOS-based biasing circuit receives the differential MLT-3 encoded input signals and control signals from a signal amplitude detection circuit. The biasing circuit adjusts for any DC offset, and also generates offset signals based on respective mid-peak voltage values of the respective differential input signals. Four comparators are then used to detect a prescribed edge transition (e.g., a positive edge) coinciding with the respective mid-peak voltage value in the respective signals. The detected edge transitions are then used by edge decoding logic to generate the NRZI bilevel signal.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: October 19, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yi Cheng, Zhenhua Liu, Kris Martin Holt
  • Patent number: 5959501
    Abstract: A class D amplifier includes a scaled clock generator for generating a scaled clock signal based upon an N bit pulse code modulation (PCM) signal and a K most significant bits (MSBs) PCM signal from the N bit PCM signal; and a PCM to pulse width modulation (PWM) converter for converting the K MSBs signal to a PWM output signal based upon the scaled clock signal. The amplifier preferably includes an input circuit for generating the N bit PCM signal from an input signal, and a truncation circuit for truncating the N bit PCM digital signal to the K MSBs PCM signal. The PWM output signal may be coupled to a switch driver which, in turn, is coupled to one or more output switches. The amplifier uses a practically implemented reference clock without the drawbacks associated with a conventional noise shaping filter.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: September 28, 1999
    Assignee: Harris Corporation
    Inventor: David B. Chester
  • Patent number: 5930303
    Abstract: A method for transmitting "biphase" encoded digital signals including the steps of setting an aperture corresponding to a data bit; dividing said aperture into a plurality of segments; setting a first segment, selected from said plurality of segments of said aperture, dependent upon whether the bit is a digital one or zero; setting a second segment, selected from said plurality of segments of said aperture, so as to fit the remaining aperture of the data bit; and, transmitting said first and second segments of said data bit; wherein a narrow spectrum results containing no low frequency components and separated from 0 Hz by an amount equal to the data rate or 1/2 the data rate.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: July 27, 1999
    Inventor: Harold Walker
  • Patent number: 5859669
    Abstract: A system for encoding control data onto a clock signal includes at least one clock cycle in the clock signal; a first transition in the at least one clock cycle, the first transition is from a first voltage level to a second voltage level, the first transition is in a first location in the at least one clock cycle; a second transition in the at least one clock cycle, the second transition is from the second voltage level to the first voltage level, the second transition has a variable location in the clock cycle; and an encoder circuit for positioning the second transition in the variable location in response to the control data.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: January 12, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Richard Mark Prentice
  • Patent number: 5793315
    Abstract: A bit-serial digital expandor includes a bit-serial dual scaler block (340), a bit-serial rectifier block (320), a bit-serial lowpass wave digital filter block (350), a bit-serial scaler with overflow detection block (360), a bit-serial multiplier block (380), and a bit-serial scaler and clipper block (395). This bit-serial expandor can be used in an AMPS cellular telephone receiver to produce a receiver having a lower silicon area, gate count, and current drain compared to equivalent parallel architecture receivers.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: August 11, 1998
    Assignee: Motorola, Inc.
    Inventor: James Clark Baker
  • Patent number: 5764165
    Abstract: A pulse width modulated, digital-to-analog converter (PWM DAC) that includes a pulse generator for generating width modulated pulses in accordance with a digital control value is set forth. The generator includes a clock for generating a clocking signal, a counter responsive to the clocking signal for generating repeating sequences of N-bit counts, each sequence representing a count interval. The PWM DAC further includes a bit rotator for receiving the sequences of N-bit counts and for rotating the bit position of at least a most significant one of N-bits. A latch holds a digital control value, whereby a comparator compares the digital control value with each one of the rotated bit counts to put out the width modulated pulses during the count interval. The rotated bit counts increases the frequency of the comparator, in a substantially linear manner, such that subsequent filtering can be accomplished with minimum time requirements.
    Type: Grant
    Filed: May 3, 1996
    Date of Patent: June 9, 1998
    Assignee: Quantum Corporation
    Inventor: Bruce D. Buch
  • Patent number: 5739969
    Abstract: A storage system for storing information on a magnetic media is embodied within a conversion device. The system is operable to store data within a bit cell by receiving data from a controller board (14), which data is generated by a Central Processing Unit (CPU) (52). This data is convened from an ordinary Modified Frequency Modulation (MFM) format received on a bus (32) and then convened to a Super High Density (SHD) data format. In the SHD format, a counter is provided for counting down from an initial starting time corresponding to a reference pulse (102) to an end count value corresponding to the value of a data word. The time between the reference pulse and the end of count value constitutes the length of time from the beginning of the bit cell to the position in the bit cell at which a data pulse is recorded. During a decode operation, i.e.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: April 14, 1998
    Assignee: Inwave Technologies, Inc.
    Inventor: Ricardo R. Garza
  • Patent number: 5684838
    Abstract: In a receiving device, when a communication signal, which changes between low level and high level, is received via a filter circuit, an occurrence of an edge of the filtered received signal is monitored. Upon detection of the edge, a type of the edge, that is, whether the edge is a leading or trailing edge, is determined. Depending on the type of the edge, one of preset times prestored corresponding to types of the edges, is selected and starts to be measured. When the selected preset time elapses, the filtered received signal is sampled. With this arrangement, even when a filtering time of the filter circuit differs depending on a type of the edge of the communication signal, a constant sampling timing relative to the communication signal can be achieved irrespective of whether the detected edge is the leading or trailing edge.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: November 4, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yasushi Kanda, Akihiro Sasaki, Nobutomo Takagi, Hideaki Ishihara, Kouichi Maeda, Tengo Fujii
  • Patent number: 5682153
    Abstract: A recording medium for a computer contains sectors, each of which represents a section of data that has originally been supplied by a user. As the user data is sent to the recording medium from the memory of the computer, an adjust bit determining circuit determines the adjust bit for a block of the write data. The adjust bit-value is such that the sum of the DC levels for the write data at a given point is equal to zero or approaches zero. The user data is converted using RLL(1,7) codes and PWM is performed to derive the write data. The circuit includes an encoder for receiving the user data two bits at a time. The encoder outputs DSV values for the 2-bit user data. A first circuit group for accumulating the DSV values from the encoder is used acquire block DSV values of data belonging to the plurality of blocks of the data section. A second circuit group accumulates these block DSV values computed by the first circuit group and calculates a temporary sector DSV value.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: October 28, 1997
    Assignee: Fujitsu Limited
    Inventor: Masayuki Ishiguro
  • Patent number: 5640160
    Abstract: A binary code is divided into 2-bit data units. Pulse position modulation is performed on each unit rather than on each bit. Since a pulse is not formed for each bit, the transmission interval and transmission frame interval for the modulated signal is shortened, thus enabling high speed transmission. Since the pulse interval of the signal contains the information of the 2-bit data unit, only the leading edge of the pulse needs to be detected. This feature allows reliable demodulation even under adverse conditions such as a long-distance transmission route or a noisy transmission route. Since there is no need to demodulate by comparing each bit with an immediately preceding bit, complex demodulation schemes and decoding registers are not needed on the receiving side. Since the width of the pulse does not contain any transmission information, the pulse width is made as short as possible, thereby reducing battery consumption within the transmitter.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: June 17, 1997
    Assignee: SMK Corporation
    Inventor: Kenichi Miwa
  • Patent number: 5588023
    Abstract: The system is used for tranmsitting information comprising message units each having multi-bit equivalent information content wherein each possible message unit in a set, (e.g. the alpha-numeric sybmol set, or other digital data) is defined by a specific half-cycle duration and messages are transmitted by conversion to half-cycle wavelet signals at the specific half-cycle durations at one message unit per half-cycle wavelet. The half-cycle wavelets are transmitted as a series of alternating half-cycle signals. The half-cycle signals are received by a receiver which measures the half-cycle duration, matches it with the pre-defined half-cycle duration and outputs that message unit. A computer program can be utilized for automatically encoding or decoding. The system has the advantages that it is relatively simple and immune to noise, it demands fewer waveform switching and affords a transmission rate of muti-bits per half-cycle wavelet. The system has advantageous compatible resollution properties.
    Type: Grant
    Filed: April 18, 1995
    Date of Patent: December 24, 1996
    Inventor: Kit-Fun Ho
  • Patent number: 5524121
    Abstract: Disclosed is an improved digital data modulating method appropriate for stable and high-speed communication. It comprises the step of allotting each of N sequential digital data bit combinations to a corresponding period-and-phase discriminating signal, thereby providing a modulated signal in the form of a series of different single-periods, which modulated signal is insensitive to noise signals appearing in communication mediums.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: June 4, 1996
    Assignee: SMK Corporation
    Inventor: Mototoshi Nambu
  • Patent number: 5481560
    Abstract: A digital-to-analog converter includes a digital-to-pulse width converter that converts a desired digital set-point value to a corresponding signal having a pulse width indicative of the desired set-point value. The desired set-point value is fed to a comparator which compares that value to the current count value from a counter that is counting up in ascending integer order. However, instead of presenting the counter output signal lines to the comparator in a normal conventional manner wherein the count value of the counter is presented to the comparator in the conventional ascending integer order, the current value of the counter is presented to the comparator in other than a conventional ascending order. The result is a comparator output signal that transitions more than one time between binary logic levels. This effectively increases the frequency of the comparator output signal.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: January 2, 1996
    Assignee: United Technologies Corporation
    Inventors: Richard J. Potetz, William B. Adamec
  • Patent number: 5475381
    Abstract: An infrared communication system for transmitting a digital bit stream by telemetry in the presence of background radiation wherein each bit in the data stream is represented by a signature set of pulses designating either a binary one or a binary zero. A receiver detecting an infrared signal filters the signal to detect the signature sets of pulses generated by the transmitter. The pulses are transmitted according to a specific communications protocol.
    Type: Grant
    Filed: January 28, 1992
    Date of Patent: December 12, 1995
    Assignee: Servio logic Corp.
    Inventors: Richard A. Williamson, Jon M. Knight, Roger W. Biros
  • Patent number: 5459751
    Abstract: A demodulation circuit of the communication control system is disclosed, in which the rising edge and the falling edge of a symbol or a one-bit data subjected to pulse width modulation as inputted from a transmission path are detected. The time width of a high-level section or a low-level section of the symbol or the one-bit data is measured on the basis of the result of edge detection. The time width thus measured is compared with a reference time width set in advance. According to the result of comparison, the sampling timing for the high-level section and the low-level section is adjusted respectively. The sampling timing thus adjusted is used to demodulate the data requiring demodulation including the symbol and the one-bit data.
    Type: Grant
    Filed: January 6, 1994
    Date of Patent: October 17, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasushi Okamoto
  • Patent number: 5400022
    Abstract: A method and apparatus for demodulating a pulse width modulated (PWM) signal previously modulated with either a first or second data value comprises sensing an actual duration of the first period of the bit cell, and generating an actual first signal value that is proportional to the actual duration of the first period of the bit cell. Using the actual first signal value and an expected first signal value, a first adjustment amount is determined and used for adjusting the actual first signal value. Then, an actual duration of the second period of the bit cell is sensed. The adjusted actual first signal value is further adjusted by a second adjustment amount to produce a final adjusted signal value, the second adjustment amount being proportional to the actual duration of the second period of the bit cell. Finally, a signal is generated which alternatively has a first value or a second value in correspondence with the final adjusted signal alternatively being greater than or not greater than a reference value.
    Type: Grant
    Filed: October 15, 1993
    Date of Patent: March 21, 1995
    Assignee: Apple Computer, Inc.
    Inventor: Raymond B. Montagne
  • Patent number: 5374927
    Abstract: A method and apparatus for decoding a specially encoded bit stream without the use of an external clock. A bit stream is encoded so that the relative lengths of the pulse widths between the transitions in the bit stream are indicative of the type bit being transmitted. A decoder receives the bit stream, measures the lengths of the pulses between the transitions, determines the type of bit by comparing the lengths, and stores the bit in a shift register. The bits can then be output in parallel form.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: December 20, 1994
    Assignee: Honeywell Inc.
    Inventors: Iain R. MacTaggart, David E. Tetzlaff
  • Patent number: 5337338
    Abstract: A pulse density modulation circuit has a counter which produces a most significant bit through a least significant bit output based on a clock input. The circuit also has a comparator with two sets of most significant bit through least significant bit inputs that produces an output based on a comparison of the two sets of inputs. The first set of comparator most significant bit through least significant bit inputs receives respectively a most significant bit through a least significant bit of an input reference signal. The second set of comparator most significant bit through least significant bit inputs receives the counter most significant bit through least significant bit output in a non-sequential bit order. The non-sequential bit order can be a bit reversed order wherein the counter most significant bit through least significant bit output are respectively connected to the comparator least significant bit through most significant bit input.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: August 9, 1994
    Assignee: Qualcomm Incorporated
    Inventors: Todd Sutton, Sherman Gregory, Joan T. Waltman, Katherine W. White
  • Patent number: 5315299
    Abstract: A data communication apparatus applicable to an automotive vehicle is disclosed in which a transmission data having a combination of bit data of "1" and/or "0" is coded into a communication signal based on an interval of time on a rising edge and/or a falling edge and the communication signal is transmitted via at least one signal transmission line. At least one of the intervals of times at a beginning of which a predetermined rising or falling edge occurs and at an end of which the subsequent rising or falling edge occurs is measured at a signal reception side and the communication signal is then decoded into the bit data of either "1" or "0" according to the result of the measured interval of time.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: May 24, 1994
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Takashi Matsumoto
  • Patent number: 5257288
    Abstract: A data transmission system and method in which digitalized information is transmitted via a data transmission link in complete binary words from a transmitter to a receiver. For data transmission, a complete binary word with a defined total bit number is subdivided into one or more partial binary words, with the respective bit numbers of the partial binary words being variable. The individual partial binary words are allocated all binary bit sequences that can be formed with the total number bits of the respective partial binary words, the various bit sequences being coded at respectively different positions within a partial binary word In each partial binary word exactly one binary bit sequence is transmitted from the transmitter to the receiver.
    Type: Grant
    Filed: April 9, 1991
    Date of Patent: October 26, 1993
    Assignee: Telefunken electronic GmbH
    Inventor: Helmut Moser
  • Patent number: 5177481
    Abstract: A data generator generates input data for a pulse generator from source data corresponding to a desired pulse width in order to make the pulse generator generate an output pulse having the desired pulse width. In the data generator, the source data are converted into the input data for the pulse generator based on a predetermined conversion relation; the predetermined conversion relation is varied; the width of an output pulse of the pulse generator is compared with that of a calibration pulse having a predetermined pulse width; and a conversion relation between calibration source data corresponding to a pulse width of the calibration pulse and the input data is maintained when the width of the output coincides with that of the calibration pulse.
    Type: Grant
    Filed: July 25, 1991
    Date of Patent: January 5, 1993
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Yoshihisa Ikuta, Souichi Matsuyama, Takuji Okumura
  • Patent number: 5140256
    Abstract: A PWM signal demodulation method measuring the leading edge period of a modulated signal and a time between adjoining leading and trailing edges of the signal and finding the modulation factor in terms of the ratio of the period to the time. Reliable demodulation is ensured even if the carrier frequency of the modulated signal varies significantly. This novel method eliminates one disadvantage of the prior art demodulation method encountered when a varying carrier frequency exceeds the linearity domain of an integrator in its integrating characteristic, causing unreliable demodulation.
    Type: Grant
    Filed: January 10, 1991
    Date of Patent: August 18, 1992
    Inventor: Kojiro Hara
  • Patent number: 5053769
    Abstract: The digital interface divides a digital number (N.sub.o) representing the sensor reading into a most significant part (MSB) and a least significant part (LSB). The most significant part is used to determine the pulse width of a sequence of pulses and the least significant part is used to selectively modify the pulses by increasing the pulse width of selected ones of the pulses. A lookup table (54) is used to evenly distribute the lengthened pulses throughout the pulse train. The resulting waveform has a DC component representative of the original digital number which is extracted by low pass filtering. The energy in the non-DC spectral components is appreciably attenuated as compared to the spectrum of a standard pulse width modulated waveform. This makes it possible to use a filter (28) with considerably higher cutoff frequency and with considerably improved response time for a given resolution.
    Type: Grant
    Filed: February 12, 1990
    Date of Patent: October 1, 1991
    Assignee: Borg-Warner Automotive, Inc.
    Inventor: Wolf S. Landmann
  • Patent number: 5025328
    Abstract: Electrical circuits suitable for decoding binary information, in accordance with a novel modulation method. The novel modulation method is referenced in the instant case, and it is explained that the method may be used when an encoding or decoding information transfer rate may be dependent on unpredictable and variable transfer rate velocities and accelerations. The present electrical circuits provide a novel means to realize the utility of the modulation method.
    Type: Grant
    Filed: March 22, 1989
    Date of Patent: June 18, 1991
    Assignee: Eastman Kodak Company
    Inventor: Fernando G. Silva
  • Patent number: 4931751
    Abstract: An apparatus is provided which is responsive to a multiple bit sample of digital information for producing a pulse width modulated signal, the apparatus comprising: a first signal match detector, responsive to a first subset of the multiple bit sample, for producing a first signal that can transition between first and second logical states; a second signal match detector, responsive to a second subset of the multiple bit sample, for producing a second signal that can transition between the first and second logical states; and a voltage summing circuit for producing a first voltage that is substantially proportional to a magnitude of the first signal in one of the first logical state and the second logical state and for producing a second voltage that is substantially proportional to a magnitude of the second signal in one of the first logical state and the second logical state and for producing an output voltage that is substantially proportional to a sum of the first voltage and the second voltage.
    Type: Grant
    Filed: June 2, 1989
    Date of Patent: June 5, 1990
    Assignee: Epyx, Inc.
    Inventors: Glenn J. Keller, Javier A. Solis
  • Patent number: 4912467
    Abstract: Electrical circuits suitable for encoding a binary data stream into a tri-bit code format. The circuits are particularly valuable for situations where the encoding or information transfer rate is dependent on unpredicable and variable transfer rate velocities and accelerations. The circuits provide "self-clocking", which, in turn, permit velocity insensitive encoding.
    Type: Grant
    Filed: June 14, 1988
    Date of Patent: March 27, 1990
    Assignee: Eastman Kodak Company
    Inventors: Arthur A. Whitfield, Michael L. Wash
  • Patent number: 4868569
    Abstract: A method and apparatus for digitally decoding a biphase encoded transmission signal, which combines both clock and data signals with a high degree of noise immunity. The decoding method has a skew tolerance nearly equivalent to using conventional decoding methods with twice the sampling rate. The method utilizes a unique look-ahead feature to resolve otherwise ambiguous signals.
    Type: Grant
    Filed: September 12, 1988
    Date of Patent: September 19, 1989
    Assignee: Schlumberger Well Services
    Inventor: Michael A. Montgomery