To Or From Minimum D.c. Level Codes Patents (Class 341/58)
  • Patent number: 7489258
    Abstract: Devices and methods, record carrier and signal for embedding, extracting, carrying and representing secondary signal such as a copy protection signal embedded in a primary signal such as a blu ray disc signal modulated by a 17PP RMTR runlength limited modulation code. Each frame comprises a frame sync patterns followed by DC control blocks each including a DC control bit. Two modulation tables are used. Each bit of the secondary signal is represented by a relationship between the polarity of the frame sync signal and the values of the DC control bits in a fashion which complies with the constraints of the modulation code and the DC control algorithm.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: February 10, 2009
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Peter Bentvelsen, Willem Marie Julia Marcel Coene, Bart Van Rompaey
  • Patent number: 7486208
    Abstract: An unencoded m-bit data input sequence is divided into a block of n bits and a block of m?n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m?n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Evangelos S. Eleftheriou, Thomas Mittelholzer, Paul J. Seger, Keisuke Tanaka
  • Patent number: 7486206
    Abstract: In order to reduce the cross talk between data recorded in adjacent tracks on a record carrier the encoding of the data stream into code words is controlled using control points. The code words in a first track are altered by selecting that value of the control point that results in code words that differ in as many bit positions as possible from the corresponding bit positions in a second track, where the first track and second track are both adjacent to the same third track. Having opposite bit values in corresponding bit positions on the first and second track results in the lowest contribution of these bit positions to the code words stored in the third track.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: February 3, 2009
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Josephus Arnoldus Henricus Maria Kahlman
  • Publication number: 20090027239
    Abstract: Presently known codes have long trains consisting of consecutive 2T runs that reduce the performance of the bit detector. By using a code with an RMTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an RMTR constraint of 2 is presented. Several variations of such a code are disclosed where one or more sub-codes are used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index Tmax+1?t.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 29, 2009
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Willem Maria Julia Marcel Coene
  • Patent number: 7479904
    Abstract: An encoder comprises a buffer that stores data associated with a communication signal. A DC-Check circuit generates a metric as a function of the data. A DC tracking block generates an invert signal as a function of the metric. An inverter unit controls an inverter bit of an output of the buffer based on the invert signal such that an average DC value of the data approaches zero. The metric is selected from a group consisting of a maximum absolute value of a running digital sum of the data, a maximum DC offset introduced by a filtering operation, a maximum DC offset of a DC correction circuit, a maximum absolute value of a filtered output of the data, a maximum DC offset slope change of the running digital sum of the data, a count of the quantity of times the metric is above or below a threshold, and combinations thereof.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: January 20, 2009
    Assignee: Marvell International Ltd.
    Inventors: Mats Oberg, Pantas Sutardja, Gregory Burd
  • Patent number: 7477169
    Abstract: Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronization, transmitter/receiver synchronization or for other control signalling.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: January 13, 2009
    Assignee: ATI Technologies ULC
    Inventors: Collis Q. Carter, Nicholas J. Chorney, James R. Goodman
  • Publication number: 20090009369
    Abstract: Disclosed herein is a data identification method for identifying, from within a readout signal from a recording medium on or in which user data of k bits are recorded using a recording modulation code wherein m bits from among n bits which compose one codeword have a value of “1” while the remaining n-m bits have another value of “0”, the data, n and m being integers including, a first step of delimiting the readout signal in a unit of a codeword and adding, with regard to one of the n-bit codewords obtained by the delimiting, an amplitude of the readout signal of the bits of “1” to 2k different codewords which may possibly be recorded and setting results of the addition as evaluation values, and a second step of finding a maximum value among the 2k evaluation values and outputting the maximum value as an evaluation result.
    Type: Application
    Filed: April 28, 2008
    Publication date: January 8, 2009
    Inventors: Masaaki Hara, Kenji Tanaka
  • Patent number: 7471217
    Abstract: The field of the invention is that of serial digital data transmissions. Such digital data is, in particular, of video type. In certain types of transmission, the links used cannot pass direct current. Such is the case in particular with the so-called “AC-coupled” links used in aeronautics for transferring video signals between computers. In this case, it becomes essential to transmit binary words comprising, if possible, similar quantities of zeroes and ones. The subject of the invention is an encoder or a decoder of 9-bit binary words into 10-bit binary words, said 10-bit binary words being designed to be transmitted over links that cannot pass direct current, said binary words comprising between four ones and six ones regardless of the initial 9-bit binary word.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: December 30, 2008
    Assignee: Thales
    Inventors: Yves Sontag, Michael Guffroy
  • Patent number: 7460035
    Abstract: Embodiments of an encoding circuit to communicate a sequence of words are described. This encoding circuit includes an encoding module that is configured to receive a first sequence of words and to generate a DC-balanced second sequence of words based on the first sequence of words, where communicating the second sequence of words consumes less energy than communicating a third sequence of words that includes words in the first sequence of words alternating with words in the inverse of the first sequence of words. In addition, the second sequence of words includes substantially twice as many words as the first sequence of words.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: December 2, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Ronald Ho, Danny Cohen, Robert J. Drost
  • Patent number: 7460034
    Abstract: A method and a device for generating codes in the transmission of data via a communications system having at least two subscribers, in which a first subscriber receives at least one data word and forwards the data word or an at least partially changed data word to at least one second subscriber, the data being represented as bits which are able to assume two different values, and at least two bits of a data word are coded in at least three bits in such a way that in the three coded bits always at least two bits of the same value follow each other and that, after the reception of one or two of the three coded bits, one may already be able to decide which first code bit is to be emitted.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: December 2, 2008
    Assignee: Robert Bosch GmbH
    Inventors: Michael Boehl, Eberhard Boehl
  • Patent number: 7443319
    Abstract: A coding scheme for data is presented in which data is encoded and decoded such that a sequence of unconstrained input binary symbols, such as 1's and 0's, is encoded into a representation according to an alphabet comprising allowable time intervals between adjacent input binary symbols according to a precision parameter p, a minimum resolution parameter ?, and resolution restriction functions L(t) and R(t), thereby defining a precision-resolution (PR) constrained code, and is modulated into an output signal comprising a waveform having signal peaks corresponding to the representation and separated according to the PR-constrained code for transmission of the output signal over the data channel. In this discussion, the minimum resolution parameter is denoted as a and is not limited to integer values.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: October 28, 2008
    Assignee: California Institute of Technology
    Inventors: Moshe Schwartz, Jehoshua Bruck
  • Patent number: 7436331
    Abstract: A run-length limited (RLL) encoder includes a problematic-block detection module that receives a data block and that generates coding bits that indicate whether at least one of N portions of the data block include one of all ones and all zeros, where N is an integer greater than one. A mapping module generates an RLL codeword based on the data block and the coding bits. The RLL codeword includes N portions. One of the N portions of the RLL codeword is populated with the coding bits. At least another one of the remaining portions of the RLL codeword is populated with at least part of the data from one of the N portions of the data block that corresponds with the one of the N portions of the RLL codeword.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: October 14, 2008
    Assignee: Marvell International Ltd.
    Inventors: Panu Chaichanavong, Zining Wu
  • Patent number: 7436332
    Abstract: A method and an encoder (1001) are disclosed for encoding an input bitstream derived from a block of coefficients relating to video data. Leading zeros and tailing zeros are determined and removed (4050, 4070) from the input bitstream. Parity bits are generated (60) for bits remaining in the input bitstream. An encoded bitstream (1032) is then generated, where the encoded bitstream (1032) comprises the number of leading zeros, the number of tailing zeros, and the parity bits.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: October 14, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Axel Lakus-Becker
  • Patent number: 7429937
    Abstract: The claimed embodiments provide methods, apparatuses and systems directed to run-length limited (RLL) coding of data. In one implementation, concatenatable RLL codes with run lengths of zeroes not exceeding k are constructed for any rate N/(N+1) where N?2k?2+k?1. As code rates increase, the value of k departs from the minimum possible value more slowly than that of many other codes. Further, occurrences of k-bit run lengths occur only at the juncture of two codewords. Due to this, the codes are mostly k?1. This quality makes the codes ideal for parity bit insertion applications such as LDPC channels. The method, in one implementation, places the bit addresses of violating sequences in a table at the beginning of the codeword, and the user data, occupying the locations where the table entries are placed, are moved into the locations of the violating sequences. This is done iteratively and in a way which provides for cases in which the violating sequence is inside the address table itself.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: September 30, 2008
    Assignee: Quantum Corporation
    Inventor: Marc Feller
  • Patent number: 7425906
    Abstract: A method of generating codewords that conform to a run length limited (RLL) constraint represented by (d, k, a, b), where d is a minimum run length of a codeword, k is a maximum run length of the codeword, a is a length of source data, and b is a length of the codeword. The method includes generating codewords conforming to the RLL(d, k) constraint, and removing codewords in which a relatively long T and a relatively short T are placed adjacent to each other from the generated codewords.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: September 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiu-Hae Jung, Joo-Ho Kim
  • Patent number: 7425905
    Abstract: Methods, algorithms, software, circuits, architectures, and systems for conditionally encoding information and processing conditionally encoded information. The present invention takes advantage of codes where most randomly selected data units fulfill the coding constraints. Thus, only those data units that need encoding (i.e., that do not fulfill coding constraints) are encoded, and those data units that do not need encoding (i.e., that fulfill coding constraints) are not encoded. By doing so, one may increase the density, bandwidth and/or gain of data communications, increase the error checking and/or correcting capabilities of a data communications system, and/or reduce interference in a multi-user system.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: September 16, 2008
    Assignee: Marvell International Ltd.
    Inventor: Mats Öberg
  • Patent number: 7425907
    Abstract: A run-length limited (RLL) DC-free encoder includes a determination module that receives input words and that determines whether each input word is a member of one of a first input set and a second input set, a first mapping module that maps the first ones of the input words of the first input set to corresponding output words that are run-length limited and DC-free, a second mapping module that maps the second ones of the input words of the second input set to corresponding output words that are run-length limited and have a negative digital sum, and an inverter module that selectively inverts the output words from the second mapping module based on a cumulative digital sum of the output words.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: September 16, 2008
    Assignee: Marvell International Ltd.
    Inventors: Panu Chaichanavong, Zining Wu
  • Publication number: 20080191908
    Abstract: Method of converting information words, which includes receiving m-bit information words, where m is an integer, and converting the m-bit information words into n-bit code words based on a code conversion table including a plurality of coding states, where n is an integer greater than m. The plurality of coding states are categorized into a first kind or a second kind and a number of coding states of the first kind is greater than a number of coding states of the second kind. Each coding state includes at least two code words of a same value representing information words of a different value, and a minimum number of zeros between consecutive ones in the n-bit code words is 1.
    Type: Application
    Filed: October 11, 2007
    Publication date: August 14, 2008
    Inventor: Kees A. Schouhamer Immink
  • Patent number: 7405679
    Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: July 29, 2008
    Assignee: International Business Machines Corporation
    Inventor: Albert X. Widmer
  • Patent number: 7403138
    Abstract: Presently known codes have long trains consisting of 2T runs that reduce the performance of the bit detector. By using a code with an RMTR constraint of 2 an improvement in the bit detection is achieved. A code constructed is a systematic way that provides an RMTR constraint of 2 is presented. Several variations of such a code are disclosed where one or more sub-codes are used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, a code word type t can be concatenated with a code word of the next sub-code if the subsequent code word of the next sub-code belongs to one of coding states of the coding class with index Tmax+1?t.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: July 22, 2008
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Willem Marie Julia Marcel Coene
  • Patent number: 7397397
    Abstract: A method and a system for communicating data in a communication channel are provided. The method includes the identification of a sequence of bits recurring in the data, and generating a locking pattern. The locking pattern includes locking symbols and a random bit pattern. The method also includes sending the locking pattern within the data. The locking pattern is received by a receiver and is used to lock the receiver and ignore the recurring bit sequence.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: July 8, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Manjunath Duntoor, Srirajkumar Sundararaman, Anand Sridharan, Benjamin Chen
  • Patent number: 7397396
    Abstract: A modulation system includes an encoder for transferring data words to tentative code words. A DSV control bit generator determines the value of a DSV control bit according to the data words or the tentative code words to optimize the cumulative DSVs corresponding tentative code words, wherein the DSV control bit generator determines the value of a current DSV control bit when at least a subsequent DSV control bit is detected. A final code word generator generates final code words according to the determined DSV control bit and the tentative code words.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: July 8, 2008
    Assignee: MediaTek Inc.
    Inventors: Hsin-Cheng Chen, Pi-Hai Liu, Ming-Yang Chao
  • Patent number: 7397398
    Abstract: A data word is error correction encoded to provide a worst case codeword without bit transitions between worst case codeword bits. A modulation bit is calculated as a function of the worst case codeword. The modulation bit has a bit polarity opposite a bit polarity of the worst case codeword bits. The worst case codeword bits are added with the modulation bit to form a modulated code word.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: July 8, 2008
    Assignee: Seagate Technology LLC
    Inventors: Ming Jin, Hiauchoon Kee, Zhenyu Sun, Liu Li, Myint Ngwe
  • Patent number: 7388523
    Abstract: An MTR encoder includes convolution units that perform convolution of input data using additional bits, MTR encoding units that MTR-encode data obtained by the convolution units, RDS calculating units and on-bit sequence checking units that calculate RDSs and counts the number of sequential on-bits of the data MTR-encoded by the MTR encoding units, respectively, and a selecting unit that selects optimum data based on the RDSs and the number of sequential on-bits.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: June 17, 2008
    Assignee: Fujitsu Limited
    Inventors: Akihiro Itakura, Toshikazu Kanaoka, Toshio Ito
  • Patent number: 7385533
    Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: June 10, 2008
    Assignee: Fujitsu Limited
    Inventors: Masaru Sawada, Toshio Ito, Toshihiko Morita
  • Patent number: 7382805
    Abstract: Embodiments of a method and apparatus for aggregating Ethernet streams are generally described. According to but one example embodiment, implementations of a physical coding sublayer (PCS) modify one or more Ethernet streams to uniquely distinguish at least one of the Ethernet streams from the other Ethernet streams. Any two or more of the modified Ethernet streams may be interleaved to form an aggregate Ethernet stream. The aggregate Ethernet stream may by transmitted over a serial link.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: June 3, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: S. Babar Raza, Edward Grivna
  • Patent number: 7379502
    Abstract: Disclosed is a method of digital data conversion. The method includes binding input digital data into unit blocks constituted by a plurality of bytes, modulation-coding each byte of the input data blocks by using a code conversion table, and allocating a merging bit in block unit for the modulation-coded input data in block unit.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: May 27, 2008
    Assignee: LG Electronics Inc.
    Inventors: Heui Gi Son, Bo Hyung Lee, Jae Jin Lee, Joo Hyun Lee
  • Patent number: 7375661
    Abstract: A variable-length coding apparatus having a smaller circuit scale, which flexibly handles identifier insertion processing in correspondence with various coding schemes, and which performs fine code amount control and adaptive erroneous operation control, and an image coding apparatus having the variable-length coding apparatus. The variable-length coding apparatus converts quantized data obtained by quantizing image data into variable-length code data, generates a code data string having a predetermined data structure, and inserts padding bits and identifier into the variable-length code data based on an externally-input instruction. Further, the image coding apparatus having the variable-length coding apparatus changes quantization values based on the total code amount of code data string generated by the variable-length coding apparatus.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: May 20, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yukio Chiba, Katsumi Otsuka
  • Patent number: 7365657
    Abstract: A data identification method including: a first step; a second step; a third step; and a fourth step, and the third and fourth steps being repeated until an identification result included in the table of recording modulation codes is obtained at the third step.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: April 29, 2008
    Assignee: Sony Corporation
    Inventor: Masaaki Hara
  • Patent number: 7365656
    Abstract: Disclosed herein is a data identification method for identifying, from within a readout signal from a recording medium on or in which user data of k bits are recorded using a recording modulation code wherein m bits from among n bits which compose one codeword have a value of “1” while the remaining n-m bits have another value of “0”, the data, n and m being integers including, a first step of delimiting the readout signal in a unit of a codeword and adding, with regard to one of the n-bit codewords obtained by the delimiting, an amplitude of the readout signal of the bits of “1” to 2^k different codewords which may possibly be recorded and setting results of the addition as evaluation values, and a second step of finding a maximum value among the 2^k evaluation values and outputting the maximum value as an evaluation result.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: April 29, 2008
    Assignee: Sony Corporation
    Inventors: Masaaki Hara, Kenji Tanaka
  • Patent number: 7358869
    Abstract: A low-power, area and pin efficient signaling alternative to serial differential links used for chip-to-chip, backplane, optical and other signaling applications. The multi-bit differential signaling (MBDS) generally comprises a driver and link termination network design coupled with a coding system based on n choose M (nCm) coding. MBDS has comparable electrical characteristics to conventional low-voltage differential signaling (LVDS) and is fully compatible with existing LVDS receivers in point-to-point and multi-point bus topologies. However, MBDS uses up to 40% less power, with up to 33% fewer I/O pads than equivalent LVDS links.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: April 15, 2008
    Assignee: University of Pittsburgh
    Inventors: Donald M. Chiarulli, Steven P. Levitan
  • Patent number: 7355532
    Abstract: We describe a voltage level coding system and method. The voltage level coding system includes a level encoder having an input to receive data segments coded using a first code and an output to supply second data codes indicating one of 2N plus at least one additional voltage level to which each data segment is assigned. A converter converts the second data codes into such voltage levels. A controller output supplies the voltage levels. A method for coding digital data includes determining a first data transition, generating a code that includes at least one additional level that minimizes data skew in the first data transition, and coding the first data transition with the additional level in the code.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: April 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin-Hyun Kim
  • Patent number: 7352302
    Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b2 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: April 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-seong Shim, Ki-hyun Kim, Hyun-soo Park, Kiu-hae Jung, Iqbal Mahboob
  • Patent number: 7348900
    Abstract: A modulation method for a first data string having a plurality of symbols is disclosed. The method includes: appending a data string to the first data string to form a second data string; and converting the second data string to a code word sequence by converting each of the symbols in the first data string to a code word according to predetermined modulation rules and a symbol set selected from the second data string. Each code word has a first fixed number of bits, each symbol has a second fixed number of bits, and each symbol set has a fixed number of symbols.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: March 25, 2008
    Assignee: MediaTek Inc.
    Inventors: Pi-Hai Liu, Ming-Yang Chao, Jin-Bin Yang
  • Patent number: 7339500
    Abstract: The present invention allows two different block codes to be encoded by one-type of encoding section. A first-point-fixed encoding section divides m-bit data into a first-half code and a second-half code, and encodes them into an n-bit provisional code with fixed start-point state. A code A/B counter receives a reset-signal and outputs a code selection signal to a code-order reversing section and a top-code correction section. The code-order reversing section receives a codeword excluding the top code from the start-point-fixed encoding section; and outputs the codeword as is, when the code selection signal indicates a code B, and reverses the order of the codeword to generate a new codeword, and outputs the new codeword to a latch, when the code selection signal indicates a code A. The top-code correction section determines whether the top code needs to be modified, and modifies the top code, if necessary.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: March 4, 2008
    Assignee: Sony Corporation
    Inventor: Makoto Noda
  • Patent number: 7330137
    Abstract: An encoder and decoder for encoding data bits of a binary source signal into a stream of data bits of a binary channel signal and vice versa includes a conversion table used to map m-bit source words to codeword having a variable code length with a basic code length of n bits and a total code length of n*i bits, i being an integer of at least 1. The conversion table preserves the parity of the m-bit source words over the codeword and limits a characteristic of the codeword specified for each starting bit position in the code word.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: February 12, 2008
    Assignee: MediaTek Inc.
    Inventor: Pi-Hai Liu
  • Patent number: 7324023
    Abstract: A decoding method for optical storage device, which decodes channel bits upon a disc by partial response maximum likelihood (PRML) detection, is proposed. Unlike the conventional skills, the present method does not decode the detected RF signals directly, but adjusts values of parts of detected RF signals to their original ideal values before channel decoding instead, thereby reducing the decoding error rate of channel bits. The decoding method includes the step of: retrieving a first sequence of RF signals; identifying if the first sequence of RF signals contains a signal combination which satisfies a particular condition; adjusting a plurality of RF signals in the first sequence of RF signals to some pre-determined RF signals' value and then forming a second sequence of RF signals; and decoding the second sequence of RF signals. In a preferred embodiment of the invention, the method is applied to an optical storage system of PR (1,2,2,2,1) channel.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: January 29, 2008
    Assignee: Macronix International Co., Ltd.
    Inventor: Chia-Yen Chang
  • Patent number: 7321320
    Abstract: A digital sum value (DSV) control apparatus inserts a DC control bit for each DC control block. The apparatus includes a first DSV accumulated value comparator for setting a target flag to a DC control bit for a first DC control block, a second DSV accumulated value comparator for comparing a first DSV accumulated value accumulated and calculated from DSV values of the first DC control block with a second DSV accumulated value accumulated and calculated from DSV values of a plurality of DC control blocks subsequent to the first DC control block, and a DC control bit determination output section for determining a value of a DC control bit for the first control block according to an output of the first and the second DSV accumulated value comparators.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: January 22, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Hiroyuki Shine
  • Patent number: 7317408
    Abstract: A digital modulation apparatus capable of generating a modulated code so that binary slice is correctly performed when reproducing is provided. To achieve this, in a digital modulation apparatus (10A), a DSV change amount calculator (15) calculates change amounts (?DSVa, ?DSVb) in DSVs of candidate modulated codes (CODEa, CODEb) generated by a modulated code generator (11). A modulated code determinator (13) compares the change amounts (?DSVa, ?DSVb), and determines that the candidate modulated code having a smaller absolute value should be selected as a modulated code (CODE). A modulated code selector (14) selects one of the candidate modulated codes (CODEa, CODEb) which is determined by the modulated code determinator (13), and outputs the selected code as a modulated code (CODE) for source data (DATA).
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: January 8, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Yabuno, Hironori Deguchi
  • Patent number: 7315262
    Abstract: A coding method for a sequence of elements that can be equal to at least two distinct values, the elements forming at least one input symbol. The coding method comprises a stretching step of stretching at least one of the input symbols, to form a stretched symbol, such that the stretched symbol does not have any successive transitions. The coding method further comprises a cancelling step of canceling the disparity of the stretched symbol to form a coded symbol, such that the coded symbol comprises approximately the same number of elements of each value.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: January 1, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Christopher Paul Hulme Walker, Arnaud Closset, Laurent Frouin, Sylvain Buriau, Barry Michael Cook
  • Patent number: 7312727
    Abstract: A communications channel comprises a seed selector that selectively removes X M-bit symbols of user data from a seed set comprising Y M-bit symbols and that selects a scrambling seed from Y-X symbols remaining in the seed set, where X, Y and M are integers greater than one. A Hamming weight coding device that determines a Hamming weight of symbols of scrambled user data that are generated based on the user data and the selected scrambling seed and that selectively codes the symbols depending upon the determined Hamming weight.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: December 25, 2007
    Assignee: Marvell International Ltd.
    Inventors: Weishi Feng, Zhan Yu
  • Patent number: 7313751
    Abstract: A dual mode decoder which includes an MB810 decoder; an 8B/10B decoder; a mode detection unit, a first low pass filter; a second low pass filter; an IDLE code detection unit which detects IDLE code and transfers to the mode detection unit; a first switch unit which selectively outputs the 10-bit code input from the first low pass filter and the second low pass filter; a parallel conversion unit which outputs a 10-bit parallel code; a first selection unit which provides the 10-bit parallel code to the decoder determined as the operation decoder between the MB810 decoder and the 8B/10B decoder; and a second selection unit which selectively outputs an 8-bit code corresponding to the 10-bit parallel code input form the decoder determined as the operation decoder.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: December 25, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sungsoo Kang, Tae Whan Yoo, Hyeong Ho Lee
  • Patent number: 7307555
    Abstract: An information recording processing apparatus includes a modulating portion operable to modulate write data on an information recording medium and to create code data thereby; and a DC level calculating portion operable to calculate a DC level corresponding to a given run length based on a coefficient defined in accordance with the run length of a component bit of the code data, wherein DC-controlled code data is created or selected based on a DC level addition result based on the DC level corresponding to the given run length, and the created or selected data is defined as write data onto the information recording medium.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: December 11, 2007
    Assignee: Sony Corporation
    Inventor: Kosuke Nakamura
  • Patent number: 7307554
    Abstract: In a data transmission system, a transmitter encodes n-bit transmit data into m-bit code (2n>m>n), and simultaneously transmits the encoded m-bit code via m signal lines. A receiver receives the m-bit code transmitted from the transmitter via the m signal lines, and decodes the received m-bit code into an n-bit data thereby obtaining received data. In the transmitter, the n-bit transmit data is encoded into an m-bit code in accordance with predefined one-to-one correspondence between 2n codes with a width of n bits and 2n codes with a width of m bits each including equal or similar number of “1”s and “0”s selected from 2m codes with the width of m bits, and amplitude levels of transmitted signals are adjusted such that the average voltage of the m signal lines is maintained constant.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: December 11, 2007
    Assignee: Kawasaki Microelectronics, Inc.
    Inventor: Osamu Kojima
  • Patent number: 7304932
    Abstract: A recording method for converting m-bit data into n-bit (where n>m) bit data whose run length is restricted and recoding the converted data on a recording medium, the recording method comprising the steps of when at least preceded data is data containing a special data pattern, lightening the restriction of the run length; and recording data so that the cumulative value of DC components per unit time increase when the data is reproduced in the state that the run length is restricted.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: December 4, 2007
    Assignees: Sony Corporation, Sony Disc & Digital Solutions Inc.
    Inventors: Yoichiro Sako, Tatsuya Inokuchi, Takashi Kihara, Shunsuke Furukawa, Yoriaki Kanada, Akiya Saito, Toru Aida, Tatsushi Sano, Yoshiro Miyoshi, Yoshinobu Usui, Toshihiko Senno
  • Patent number: 7301483
    Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: November 27, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-seong Shim, Ki-hyun Kim, Hyun-soo Park, Kiu-hae Jung, Igbal Mahboob
  • Patent number: 7301482
    Abstract: Methods, algorithms, software, circuits, architectures, and systems for conditionally encoding information and processing conditionally encoded information. The present invention takes advantage of codes where most randomly selected data units fulfill the coding constraints. Thus, only those data units that need encoding (i.e., that do not fulfill coding constraints) are encoded, and those data units that do not need encoding (i.e., that fulfill coding constraints) are not encoded. By doing so, one may increase the density, bandwidth and/or gain of data communications, increase the error checking and/or correcting capabilities of a data communications system, and/or reduce interference in a multi-user system.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: November 27, 2007
    Assignee: Marvell International Ltd.
    Inventor: Mats Oberg
  • Patent number: 7298294
    Abstract: An encoder for encoding a communication signal includes a signal buffer to buffer data associated with the communication signal. A DC-Check circuit to compute a metric as a function of the data. A DC tracking block to generate a flip signal as a function of the metric, the flip signal having a flip state and a nonflip state. A flip unit, responsive to the flip signal, to control a flip bit of an output of the signal buffer such that an average DC value of the data approaches zero.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: November 20, 2007
    Assignee: Marvell International Ltd.
    Inventors: Mats Oberg, Pantas Sutardja, Gregory Burd
  • Patent number: 7295138
    Abstract: In the coding device and method, m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than ?. The n-bit code words are divided into a first type and a second type, and into coding states of a first kind and a second kind such that an m-bit information word is converted into an n-bit code word of the first or second kind if the previous m-bit information word was converted into an n-bit code word of the first type and is converted into an n-bit code word of the first kind if the previous m-bit information word was converted into an n-bit code word of the second type. In one embodiment, n-bit code words of the first type end in zero, n-bit code words of the second type end in one, n-bit code words of the first kind start with zero, and n-bit code words of the second kind start with zero or one.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: November 13, 2007
    Assignee: LG Electronics Inc.
    Inventor: Kees A. Schouhamer Immink
  • Patent number: 7292161
    Abstract: Techniques for encoding N-binary symbol (NB) source data vectors into M-binary symbol (MB) encoded vectors, M>N>0, are provided. Techniques for decoding are also provided. Exemplary coding and decoding apparatuses are presented, as is an exemplary 8B/10B encoding scheme. Encoded vectors may be disparity dependent or disparity independent. In assigning encoded vectors that have one or more individual binary symbol changes compared with their source data vectors, preference can be given to encoded vectors that are balanced and disparity independent. Whole-vector complementation and individual changes of one or more binary symbols can advantageously be performed substantially in parallel.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: November 6, 2007
    Assignee: International Business Machines Corporation
    Inventor: Albert X. Widmer