Abstract: A methodology for designing an implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 20/21, rate 50/51, rate 90/91 and other modulation code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for the removal or reduction of divergence artifacts between a transmitting codec and a receiving codec. One of a number of implementations includes using a deblocking filter in an inverse transformer loop and selectively disabling the filter upon certain conditions.

Abstract: A programmable logic device can be programmed to configure its logic elements to approximate the normalization of probability values used in the operation of logMAP decoders, thereby significantly reducing the amount of logic resources required in the normalization procedure without significantly degrading performance. In the first preferred embodiment, normalization is achieved by approximating the normalization value by calculating an approximate normalization value which is then deducted from all &agr; values in the trellis at any time. This is done by logically ANDing all &agr; input probability values with the NOT of their own MSBs. The resulting outputs are then all bitwise ORed together, the output of which is the approximate normalization value. In another embodiment, the approximate normalization value is calculated using a fixed constant determinable at the outset of the logMAP decoder operation.

Abstract: A decoding apparatus and data reproduction apparatus which can perform correction of 1T and 2T which inherently cannot exist as EFM signals, reduce processing of an error correction circuit, and improve the playability. Provision is made of an EPM block containing a correction portion for detecting an edge of an RF signal converted to a binary format by the PLL asymmetry correction circuit for NRZ conversion, using a clock generated in the digital PLL circuit for synchronization, detecting 1T and 2T (T is a channel clock period), which inherently cannot exist as EFM signals in format, generated at the time of synchronization, correcting the detected 1T and 2T signals to 0 or 3T in accordance with predetermined conditions to remove the 1T and 2T from the RF signal, and modulating the RF signal from which the 1T and 2T have been removed by EFM and a demodulation circuit for demodulating by EFM a signal after modulation by EFM.

Abstract: A digital video coding method for encoding video frames and outputting a bit stream including picture headers is provided. The digital video coding method includes the steps of identifying what is changed in a coding type between a previous frame and a current frame, and performing a predetermined bitwise logical operation with respect to a value of an indicator field of the previous frame and a bit value, wherein the bit value is determined according to the kind of change in a coding type which is identified in the above step and the indicator field is a predetermined field for indicating whether the coding type has been changed, and determining a result value of the logical operation as a value of an indicator field of the current frame.

Abstract: A data compression apparatus for data compressing an information signal, which is in n-level form, n being larger than 2. The data compression apparatus includes an input terminal for receiving the n-level information signal, an entropy coder, such as an arithmetic coder having an input for receiving an input signal, which is adapted to carry out a lossless encoding step on the input signal, so as to obtain a data compressed output signal at an output. The apparatus further includes a prediction filter for carrying out a prediction step on the n-level information signal so as to obtain a prediction signal and a probability signal determining unit for generating the probability signal in response to the prediction signal. An output terminal is available for supplying the data compressed output signal. Further, a data expansion apparatus is disclosed.

Abstract: This invention relates to a data decoding apparatus and data decoding method which perform maximum likelihood decoding by means of a simple construction, and which can be applied for example to a videotape recorder or optical disk device. In the data decoding apparatus or data decoding method according to this invention, a logic level inversion timing during one clock interval is detected from an input signal, a provisional identification result of identifying the input signal is corrected by effectively one clock identification error, the number of state transitions which can be obtained from the input signal is limited based on this corrected provisional identification result, and the most probable state transition of these limited state transitions is detected to output an input signal identification result.

Abstract: A method and apparatus for radically abbreviated decoding for providing decoded data by dividing a stream of data symbols, which form the decoder input, into symbol bit streams. The symbol bit streams are combined with delayed data streams in a first formatting means forming formatted bit streams. The formatted bit streams are applied to a selecting means for selecting bits from the formatted bit streams, forming a selected formatted bit stream. The selected formatted bit stream is applied to a sequential storage means forming delayed bits. The delayed bits are tapped from different points on the sequential storage means forming weighted bits. The weighted bits are then combined with a second formatting means further forming the delayed data streams, where the selected formatted bit stream is the decoded data.

Abstract: A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.

Abstract: There is provided a decoding device comprising a unit for checking whether an error occurs in pack header information which is extracted from each pack by a pack header information extracting unit, for retrieving pack header information that mostly conforms to a specific standard from a pack header information database if the extracted pack header information has an error, and for replacing the extracted pack header information having an error with the pack header information that mostly conforms to the specific standard to enable a packet header detecting unit to detect the packet header.

Abstract: Error correction coding and decoding according to a serial concatenated modulation system are carried out under high code rate. A coding apparatus 1 comprises three convolutional coders 10, 30 and 50 for carrying out convolutional operation; two interleavers 20 and 40 for rearranging order of data input; and a multi-value mapping circuit 60 for carrying out mapping of a single point on the basis of a predetermined modulation system. The coding apparatus 1 carries out convolutional operation whose code rate is “⅔” as coding of extrinsic codes by a convolutional coder 10, and carries out convolutional operation whose code rate is “1” as coding of inner codes by a convolutional coder 50, and a multi-value modulation mapping circuit 60 applies mapping to a transmission symbol of a 8 PSK modulation system to output it as a single code transmission symbol.

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

Abstract: There is provided a decoding device comprising a unit for checking whether an error occurs in pack header information which is extracted from each pack by a pack header information extracting unit, for retrieving pack header information that mostly conforms to a specific standard from a pack header information database if the extracted pack header information has an error, and for replacing the extracted pack header information having an error with the pack header information that mostly conforms to the specific standard to enable a packet header detecting unit to detect the packet header.

Abstract: An analog to digital converter converts an analog input signal to at least two digital output signals as follows. An analog feedback signal is subtracted from the analog input signal to produce a difference signal. The difference signal, then, is integrated to produce an integrated signal which is quantized to produce the digital output signals in response to respective control signals each having a predetermined frequency and being offset in phase from each other. Finally, the digital output signals are converted into the analog feedback signal. Such analog to digital converter uses components operating at a lower frequency than the sampling frequency fs without loss of dynamic range.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for the removal or reduction of divergence artifacts between a transmitting codec and a receiving codec. One of a number of implementations includes using a deblocking filter in an inverse transformer loop and selectively disabling the filter upon certain conditions.

Abstract: A method to create runlength-limited codes from shorter codes having suppression of error propagation by insertion of uncoded bits adjacent error suppression end bits of the shorter code.

Abstract: A D/A converter of a multibit type has improved performance by reducing dispersion of the electric currents of plural electric current sources as much as possible in which the D/A converter has a constant electric current source (10) constructed by 2N (N=2, 3, - - - and here, N=16) constant electric current sources having constant electric current values equal to each other; selectors (7, 8) for selecting Di constant electric current sources according to input data Di {here, Di=0, 1, 2, 3, - - - , (2N−1)} having N-bits in input word length so as to use these 2N constant electric current sources one by one until a sum of values of one input data or continuous plural input data among these 2N constant electric current sources exceeds 2N; and an electric current adder (9) for adding each of the constant electric currents from the Di constant electric current sources selected by the selectors to each other.

Abstract: A methodology for designing and implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 30/31, rate 40/41, rate 50/51 and much higher modulation code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.

Abstract: A trellis shaping method is described that may be used for suppressing DC components and/or Nyquist frequency components from the outputs of a PCM (56K) modem. The technique is based on convolutional codes. The code is generated through the use of a Viterbi decoder. Data bits are mapped for transmission into a set of n magnitudes and (n−k) sign bits s. The sign bits s are passed through (HT)−1 to get preliminary sing bits t=s (HT)−1 of size n. (HT)−1 is a matrix of size (n−k) by n which represents the left inverse of the syndrome-former matrix HT of convolutional code c=b G, defined so that G HT=0. The convolutional code is then added to sign bits t through an XOR operation to give final sign bits s (HT)−1+b G. After transmission, the final sign bits are passed through HT to give an output of (s (HT)−1+b G) (HT))=s, for recovery of the data bits.

Abstract: A method and apparatus for minimizing a disparity of set and clear bits transmitted across a serial line is disclosed. The method operates by determining a line disparity by examining n-bit datawords that are transmitted. The method also determines a dataword disparity is determined for a dataword yet to be transmitted. The dataword yet to be transmitted is then inverted before transmission if the line disparity and the dataword disparity have the same sign.

Abstract: The encoder arrangement and bit-exact IDCT protocol provides methods and arrangements that prevent an accumulation of errors between a transmitting codec and a receiving codec. One example embodiment is directed to an arrangement for use in a first terminal for communicating representations of images with a second terminal using a communications channel on which communication has been established between the first terminal and the second terminal. The arrangement includes a processor-based decoder/encoder circuit and a bit-exact circuit. The processor-based decoder/encoder circuit is arranged to process video data using an inverse transformer loop. The bit-exact circuit prevents unacceptable accumulation of an error within the inverse transformer loop by using the inverse transformer in the loop according to a bit-exact specification between the encoder and decoder in the respective first and second terminals.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for the removal or reduction of divergence artifacts between a transmitting codec and a receiving codec.

Abstract: An error detection circuit for detecting errors occurring in a data obtained by decoding a compressed image data block by block in a line length decoding system, includes a first storage device for temporarily storing the run representing the number of zeros (‘0’s) in the compressed image data and an EOB signal externally inputted, a selection signal generator for generating a first and a second selection signal in response to the EOB signal supplied from the first storage device, a first selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the first selection signal, a second selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the second selection signal, a reference value generator for generating a reference value based on the output signal of the first selection circuit according to an operation control signal externally inputted, accumulator for accumulatin

Abstract: A methodology for designing and implementing high rate RLL codes is optimized for application to 8-bit ECC symbols, and provides modulation code rates including rate 32/33; rate 48/49; rate 56/57; rate 72/73; rate 80/81 and other code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.

Abstract: An apparatus and a method detect and automatically correct an illegal address in a peripheral connect interface bus addressing scheme. The value of a current bit is read. The value of a bit immediately left adjacent of the current bit is read. A value of 0 is outputted as the current bit in the event the value of the current bit is 1 and the value of the left adjacent bit is 0. In one specific embodiment, the apparatus employs a multiplexer and a single-bit register with a feedback as a one bit detection and correction circuit.

Abstract: A message is encoded into an array, which is an element of a constrained array set. The message is encoded by considering candidates for each entry (e.g., column, bit) of the array. The candidates have a predetermined ordering. For each candidate that is considered, a lower bound is determined. The lower bound indicates a number of set elements including both the candidate being considered and previously selected candidates of the array. An entry is filled with a candidate based upon the value of the lower bound relative to an intermediate message. The intermediate message is initially equal to the message being encoded, and is updated after each column of the array has been filled.

Abstract: There are provided channel encoding/decoding device and method to efficiently transmit/receive voice and data. Data with a low data rate or a short data frame is convolutionally encoded and data with a high data rate or a long data frame is turbo-encoded, thereby increasing encoding performance.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for the removal or reduction of divergence artifacts between a transmitting codec and a receiving codec. One of a number of implementations includes using a deblocking filter in an inverse transformer loop and selectively disabling the filter upon certain conditions.

Abstract: A method and an apparatus for designing a codebook error resilient data transmission is disclosed. The present invention allows for creation of a robust yet compressive codebook for transmission of data. One embodiment of the present invention utilizes a combination of Huffman and Gray coding techniques to achieve both robustness and high compression ratios for data sets of single or multiple dimension. In particular, the present invention utilizes a series of Gray codes to improve the robustness of a Huffman code utilized by the MPEG-4 standard for motion video compression. The present invention may also be used to create codebooks for other forms of data, these codebooks can be designed to be robust or robust and compressive, and can encode data of single or multi-dimensional format.

Abstract: A digital-versatile disk (DVD) playback-controller integrated circuit (IC) writes data to a block in an embedded DRAM memory. The memory block has rows and columns. Data read from a DVD optical disk is read in row order. Rather than write the DVD data across the rows in the memory block, the DVD data is accumulated into 16-byte words, and successive 16-byte words are written down a column in the memory block. Each row from the DVD disk is written to a 16-byte-wide column in the memory block. The embedded DRAM has a wide 16-byte interface, so all 16 bytes in a word are written during a single memory-access cycle. All the bytes in the memory block must be read in column-order for column-syndrome generation. Since the row-column ordering is reversed, the column-syndrome generator reads bytes across the memory-block rows. Most of these fetches are DRAM page hits, so access speed is improved for column-syndrome generation.

Abstract: A combined Chien search and error position circuit (116), for use in Reed-Solomon decoding, is disclosed. The circuit (116) operates in response to a zero signal (ZRO) issued by a root detection block (200) that iteratively evaluates an error locator polynomial .LAMBDA.(x) over the Galois field used in the coding. A zeroes register (218) and a position register (22) are provided, each of which have a plurality of stages (218.sub.0 through 218.sub.t ; 220.sub.0 through 220.sub.t). An index counter (208) maintains a count over the Galois field, corresponding to the Galois field element under evaluation in the root detection block (200). An exponentiation circuit (212) performs a Galois field exponentiation of the count, and applies the result to the inputs of each of the zeroes register stages (218.sub.0 through 218.sub.t); the count is subtracted from the maximum Galois field index (e.g.

Abstract: A Viterbi PRML system and method providing a new code with distance properties such that some tribits are allowed but no longer sequences are allowed. A code rate 8/ 9 is constructed for EPR4 and E.sup.2 PR4 channels and the system independently maps 8-bit blocks of user data to 9-bit channel sequences. The precoder has transfer function, f(D)=1/(1.sym.D), and produces a binary channel input x(D), which is fed to a coder, to provide an output signal y(D), which is transmitted and corrupted by noise. The corrupted signal is received and fed to a Viterbi detector. The signal is decoded to produce an estimate of the 8-bit data bytes, as reconstructed to be freed from noise corruption. The encoding protocol of the invention is implemented in the encoder.

Abstract: A method of modulating digital data to be used for transmitting or recording N-bit (e.g., 8-bit) data comprises a step of converting the input N-bit data into an M+K-bit data selected out of a group of 2.sup.M M+K-bit data according to a predetermined rule, the group of 2.sup.M M+K-bit data being obtained by adding a K-bit error correction checking symbol to M-bit (e.g., 9-bit) data (N<M). For demodulation, the M+K-bit data is subjected to an error correcting operation or an error detecting operation before it is demodulated into an N-bit data.

Abstract: In decoding an received codeword encoded for error correction purposes, a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step is presented whereby the polynomials are generated through a number of intermediate steps that can be implemented with minimal amount of hardware circuitry. The number of intermediate steps requires a corresponding number of cycles to complete the calculation of the polynomials. Depending on the selected (N, K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of up-stream data. More specifically, an efficient scheduling of a small number of finite-field multipliers (FFM's) without the need of finite-field inverters (FFI's) is disclosed. Using these new methods, an area-efficient architecture that uses only three FFM's and no FFI's is presented to implement a method derived from the inversionless Berlekamp-Massey algorithm.

Abstract: A device including a mechanism (4) for generating a counting clock signal (CKM) whose frequency is less than or equal to n times twice the transmission frequency. The device also includes a detection mechanism (10) for detecting the transitions (TD) of the signal (DS) at the counting frequency and for delivering corresponding detection signals (ST), a selection mechanism (2) for receiving each detection signal (ST) and for delivering or otherwise a selection signal (RS) depending on the satisfying or otherwise of a predetermined selection criterion, and a frequency divider-by-n (30) which receives the counting clock signal, in order to sample the carrier signal after a predetermined time delay (Tr) after each detected transition. Provided are a sampling control device and method which are completely digital and therefore use no analog component of the phase-locked loop type and are very simple to produce at an industrially economical cost.

Abstract: A punctured maximum transition run (PMTR) code includes transition-allowed bit slots and transition-disallowed bit slots. Each of the transition-allowed bit slots is a bit slot in which a bit representing a third consecutive transition of a logic signal can occur whereas each of the transition-disallowed bit slots is a bit slot in which a bit representing a third consecutive transition of a logic signal cannot occur. There are at least two transition-allowed bit slots which are adjacent to each other. The transition occurs from a high logic level to a low logic level, or from a low logic level to a high logic level.

Abstract: A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-( . . . 010-10 . . . ) error events and error events +/-( . . . 01000-10 . . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal.

Abstract: A method and receiver for correcting a received message includes a character converter for converting received data into a character string, and for converting the character string into characters, when a predetermined character in the character string is recognized by the character converter. A message corrector corrects a message formed by the characters when an error is included in the message.

Abstract: A distributive encoder for receiving and processing digital error signals representing variations in peak values of an equalized incoming digital data signal and in accordance therewith encoding error signals which represent signal peak errors in data signals for purposes of identifying erroneous signal baseline, peak and equalization conditions. The digital error signals represent variations in peak values of an equalized incoming digital data signal which includes a data signal baseline intermediate to its positive and negative peaks. Two sets of the digital error signals identify when present positive and negative levels transcend prior positive and negative levels, respectively, of the equalized incoming digital data signal. Using various subsets of these digital error signals, the distributive encoder generates encoded error signals which identify erroneous signal baseline, peak and equalization conditions.

Abstract: There is disclosed, a converter for converting an input signal from one form to another includes a generator circuit for generating as a thermometer code a plurality of binary signals from the input signal. The converter includes one or more enhanced majority gate circuits for correcting a broken thermometer code to be a corrected thermometer code. The corrected thermometer code is decoded to provide a digital code corresponding to the input signal.

Abstract: A digital map system for displaying three dimensional terrain data uses terrain data in the form of polygons. The polygon database is produced from a database of elevation points which are divided into, for example, n.times.n (where n is a positive integer) squares which have an elevation point in the center of the square. The center point forms four polygons with the corners of the square. The elevation of the center point may be chosen to be the highest elevation point in the n.times.n square, the average elevation of the elevation points in the n.times.n square, the elevation of the actual center point, or other methods. The method chosen depends on how the data base is to be used. The size of the n.times.n square chosen also depends on how the data base is to be used since there is a tradeoff between the resolution of the displayed scene and the amount of data reduction from the original database of elevation points.

Abstract: A reproducing apparatus comprises an error correcting means which includes first and second input circuits for inputting first and second coded data read out via different series separately, first and second frequency converters for converting the respective timing frequencies of the first and second coded data to higher frequencies, a multiplexer for generating third coded data by time-division multiplexing the first and second coded data of the higher timing frequencies, and an error corrector for executing an error correction of the third coded data. The apparatus further comprises a decode means for decoding the third coded data processed through error detection and correction, and a data output means for outputting the decoded data.

Abstract: An encoder/decoder device for improving the bit error rate, speedily and at low cost without using an A/D converter circuit. A comparator compares the playback signal loaded from the disk with a specified reference level, places the signal in binary notation and sends the binary information to a memory. When the continuous length showing the quantity of zeroes placed between ones in succession is an error length which is shorter than a specified length 3T designated beforehand, an error length detection circuit detects this as a continuous length. A pattern detector circuit detects patterns in which the continuous length in front of error length 2T is 3T and the continuous length behind 2T is 4T or more, and further detects patterns in which the next continuous length after error length 2T is 3T and the continuous length in front of 2T is 4T or more.

Abstract: An efficient method and apparatus corrects synchronization problems in the recovery data stored on magnetic media. Resolving blocks are inserted into the unconstrained data string at specified intervals. A resolving block is constructed to do two things: reset the encoding automaton and produce in the constrained data string blocks which allow correction of synchronization. Before decoding, synchronization is corrected. The constrained data string is decoded, and then the resolving block removed. The blocks are inserted before run-length limited encoding occurs and deleted after run-length limited decoding takes place. The run-length limited encoder and decoder are unchanged.

Abstract: An encoding scheme controls long carry-over propagation while at the same time prevents start code emulation. An arithmetic encoder converts an input signal into an encoded bit stream that provides data compression of the original input signal. The encoding scheme identifies carry-overs from the encoded input signal that could propagate into portions of the previously encoded bit stream and inadvertently emulate a start code. Bit stuffing is used to avoid emulation of the start code while at the same time limit propagation of carry-overs. A first bit stuffing procedure is used for detecting carry-over in the encoded input signal. A second bit stuffing procedure is used during normalization of the arithmetic encoded data.

Abstract: An nB2P coding/decoding device having a line code function facilitating data transmission and data recovery in the transmission line or link, and a function of a channel code for detecting errors in the recovered data, is provided, including: an nB2P coding device for dividing n bit width parallel data into two data units each having a predetermined bit width, and serial-transmitting the resulting n+2 bit coded data to which two odd parity bits are added, with predetermined n+2 bit with block synchronization data which is orthogonal to the coded data; and an nB2P decoding device for detecting the block synchronization data from the serially transmitted data, converts serial data to parallel form of n+2 bits, checking for errors in the coded data using the odd parity, and removing the odd parity to decode them into the original n bit width parallel data.

Abstract: A run length limited (RLL) code generation method for a data storage device is provided. In the RLL code generation method for generating a predetermined number of bit codewords, sequences of 16-bit data are received, and then sequences of 17-bit codewords are produced, wherein the sequences of 17-bit codewords has a first predetermined number of successive zeros as a maximum run length of zeros, and the sequences of 17-bit codewords include two subsequences each having a second predetermined number of successive zeros as a maximum run length of zeros. Thus, the RLL code generation method is helpful for an equalizer and provides a high recording density as well as a higher signal transmission rate compared to a rate 8/9(0,4/4) coding method.

Abstract: A process for transmitting coded data over a data channel subject to interference. The information fields are provided with error protection in the amount required by the extent of interference. A configuration field, with information on the extent of data protection, is transmitted with the data.

Abstract: A rob bit compensation system improves the accuracy of digital signals transmitted to a digital network, such as a telephone network, that employs rob bit signaling (RBS) wherein the network periodically robs a bit for its own use. The rob bit compensation system can be employed within the transmit subsystem of a digital modem connected with the digital network that periodically robs a bit every nth frame, where n is, for example, 6, 12, or 24. The system may also be employed in association with the communications path within a coder/decoder (codec) that transmits data to the digital network. A feedback system advises the rob bit compensation system as to which frames of outgoing digital data are to have a bit robbed therefrom by the digital network. The feedback system causes a quantity to be mathematically combined with the digital data corresponding with each RBS frame in order to enhance accuracy of the RBS frames.

Abstract: The encoder/decoder system uses encoder hardware to encode data symbols and form a data code word. To decode, the system uses the same encoder hardware to determine a residue r(x), i.e. ##EQU1## where C.sub.r (x) is the retrieved code word and g(x) is the generator polynomial. If the residue is all zeros, the ECC code word is error-free and the system need not calculate the error syndrome. If the residue is non-zero, the encoder hardware is used, with various switches in different settings, to include certain multipliers in and exclude other multipliers from the further decoding operations of encoding the residue symbols to produce partial error syndromes that are the coefficients of the error syndrome polynomial.