Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: A switching element control circuit includes: a third electrode voltage control part which controls a third electrode voltage; a first electrode current detection part which detects a first electrode current which flows through the switching element; a memory part which stores information including an initial threshold voltage and an initial first electrode current, and a drain current characteristic of a threshold voltage; and a threshold voltage calculation part which calculates a threshold voltage at a time of operating the switching element based on information including the first electrode current, the initial threshold voltage, and an initial first electrode current, and information relating to the first electrode current characteristic of the threshold voltage, wherein the third electrode voltage control part controls the third electrode voltage based on a threshold voltage at the time of operating the switching element calculated by the threshold voltage calculation part.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. Switching transistor devices are added to an inverter of the GOA unit, and a low-potential signal is output to relevant nodes in the inverter in time to release residual charge of the relevant nodes.

Abstract: It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small. A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line.

Abstract: A display device includes: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and a second scan line; a first scan driver connected to a first scan start line and the first scan line; and a second scan driver connected to a second scan start line and the second scan line. In a first frame period, the second scan start line is to be suppled with a second scan start signal having a turn-on level, after a first period elapses after a first scan start signal having a turn-on level is supplied to the first scan start line. In a second frame period, a difference between a time at which the first scan start signal having the turn-on level is supplied and a time at which the second scan start signal having the turn-on level is supplied corresponds to a second period. The second period is shorter than the first period.

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

Abstract: An electro-optical device includes a first switch provided between an input node supplied with a data signal and a first data line, the first switch being configured to be turned ON or OFF by a first control signal, a second switch provided between the input node and a second data line, the second switch being configured to be turned ON or OFF by the second control signal, a sequential output circuit configured to output a first pulse, and a second pulse exclusive of the first pulse, logical operational first logical operation circuit configured to acquire a first logical product signal of the first control signal and the first pulse, and a second logical product signal of the second control signal and the second pulse, and a second logical operation circuit configured to generate a logical sum signal of the first logical product signal and the second logical product signal.

Abstract: A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Abstract: A display driver according to the present invention includes a control part and a fault detection circuit. The control part sequentially incorporates first fault detection data and second fault detection data into a video signal during non-display periods of the video signal. The fault detection circuit binarizes each of a first pixel driving voltage and a second pixel driving voltage with a predetermined threshold voltage to obtain a first signal and a second signal. The first pixel driving voltage is generated based on the first fault detection data. The second pixel driving voltage is generated based on the second fault detection data. The fault detection circuit determines whether the first signal and the second signal match and outputs a fault detection signal that indicates a presence of a fault when the first signal and the second signal match.

Abstract: A driving apparatus, a display apparatus, and a driving method are provided. The driving apparatus includes: a first switch tube, a second switch tube, a third switch tube, and a data output assembly. A first shared voltage or a second shared voltage are controlled by on states and off states of the first switch tube, the second switch tube, and the third switch tube to be output to a pixel electrode.

Abstract: The display apparatus includes a data generation circuit, a source driver circuit, and a pixel. The source driver circuit is electrically connected to the pixel through first and second wirings. The pixel includes a display device that is a liquid crystal device, a potential of one electrode of the display device can be a potential of the first wiring, and a potential of the other electrode of the display device can be a potential of the second wiring. The image data generation circuit has a function of generating digital image data including first and second data. One of the first and second wirings is made to have a potential corresponding to first data, and the other of the first and second wirings is made to have a potential corresponding to the second data. The potential of the first wiring and the potential of the second wiring are interchanged.

Abstract: A display device that achieves both high-accuracy sensing by a touch sensor unit and smooth input using the touch sensor unit is provided. The display device includes a display unit and the touch sensor unit. The touch sensor unit performs touch sensing operation at a different timing from display image rewriting by the display unit, whereby the high-accuracy sensing can be achieved. The display unit has a function of rewriting a display image only in a region that needs to be rewritten. In the case where the entire display region is not necessarily rewritten, the time for the sensing operation by the touch sensor unit can be lengthened, whereby the smooth input can be achieved.

Abstract: A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.

Abstract: The present disclosure provides a shift register unit, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes: an input sub-circuit coupled to an input signal terminal and a pull-up node and configured to transmit an input signal from the input signal terminal to the pull-up node under control of the input signal; and n output sub-circuits, wherein each of the n output sub-circuits is coupled to the pull-up node, one of n clock signal terminals, a first level signal terminal, and one of n output signal terminals, and is configured to transmit a clock signal from the clock signal terminal coupled to the output sub-circuit to the output signal terminal coupled to the output sub-circuit under control of a voltage signal at the pull-up node, where n is an integer greater than 1.

Abstract: Disclosed are a drive circuit of a display device, and a display device. The drive circuit includes: a plurality of sets of transmission signal lines; a set of clock signal lines, in signal connection with a timing drive circuit separately to acquire a gate drive clock signal; and a compensation capacitor, connected in parallel to each transmission signal line, each transmission signal line in each set of transmission signal lines being in signal connection with a clock signal line corresponding to a set of clock signal lines, where the compensation capacitance corresponding to the transmission signal line, closer to the timing drive circuit, in each set of transmission signal lines is smaller.

Abstract: An electronic device includes: a display panel and a host. The host is electrically connected to the display panel, and includes a processing unit and a graphics processing unit. The processing unit executes a driver program of the graphics processing unit and a specific program to render a display image of the specific program, wherein the display image includes a user interface. The processing unit obtains position information about a static area of the user interface. In response to the processing unit obtaining the position information about the static area of the user interface, the graphics processing unit performs a burn-in-prevention process on the static area via the driver program to generate an output image, and transmits the output image to the display panel for displaying.

Abstract: An array substrate is provided, which includes a gate driver on array (GOA) circuit and a plurality of logic OR gate units integrated in a rear end of the GOA circuit. The GOA circuit includes a plurality of cascaded GOA units, each of the GOA units includes a scan terminal, and at least three continuously-cascaded GOA units are connected to one of the logic OR gate units through the scan terminals.

Abstract: A display device includes: a display area including pixels for displaying an image; a non-display area adjacent to the display area; scan lines connected to the pixels; a first scan driver circuit disposed in the non-display area, where the first scan driver circuit is connected to first scan lines among the scan lines, and outputs first scan signals to the first scan lines; and a second scan driver circuit disposed in the non-display area, where the second scan driver circuit is connected to second scan lines among the scan lines, and outputs second scan signals to the second scan lines. The second scan driver circuit is disposed farther away from the display area than the first scan driver circuit is.

Abstract: A source driver includes a plurality of output buffers configured to output data signals respectively corresponding to a plurality of data lines, and an output controller configured to control a timing at which each of the data signals corresponding to second image data is transferred from the output buffers to the data lines based on a difference between first image data and the second image data.

Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Abstract: The present disclosure provides a shift register unit, a driving method, a light emitting control gate driving circuit, and a display apparatus. The shift register unit includes: a light emitting control signal output terminal, a pull-up control node control circuit, N stages of inversion control circuits, a pull-up node control circuit, a pull-down node control circuit, and an output circuit, where N is an integer greater than 1. A first stage of inversion control circuit is configured to invert an input signal. An nth stage of inversion control circuit inverts the input signal under control of an (n?1)th inversion node, where n is an integer and 2?n?N.

Abstract: A display controller for a display may include a frame rate circuit to change a frame rate of the display from a first frame rate to a second frame rate, and a reference voltage circuit to adjust a reference voltage of the display from a first reference voltage corresponding to the first frame rate to a second reference voltage corresponding to the second frame rate. The display may be a thin film transistor liquid crystal display. The reference voltage may correspond to a common voltage (Vcom) for the display.

Abstract: A shift register unit, a driving method thereof, a gate driving circuit, and a display device are provided. The shift register unit includes an input branch and a reset branch; the input branch is configured to form or disconnect a first path between a first scan voltage terminal and a pull-up node under control of a potential of a first control terminal. The reset branch is configured to form or disconnect a second path between a second scan voltage terminal and the pull-up node under control of a potential of a second control terminal.

Abstract: A display device includes a substrate including a display area and a non-display area, a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels displaying a different color from a color of the first pixel column, and data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column, wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines.

Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.

Abstract: A scan shift circuit and its driving method, a touch shift circuit and its driving method, a gate driving circuit, a touch driving circuit and a display apparatus are disclosed. The scan shift circuit includes an input circuit, a reset circuit, a latch control circuit and a scan signal output circuit. The touch shift circuit includes an input circuit, a reset circuit, a latch control circuit, a cascade signal output circuit, a touch driving circuit and a touch signal output circuit.

Abstract: System and method for displaying digital content on a display device, including at least one digital content item configured to be displayed on the display device, a service cloud, including a server, first memory, and first processor, configured to store and manage digital content, and an application, configured to run on a computer with second memory, second processor, and user input device, and configured to communicate via the Internet with the display device and service cloud. In response to a signal from the user input device, the application detects a display of a digital content item on the interface, selects the item display from a virtual representation of a digital library on the interface, and moves the item display to a virtual representation of the display device on the interface. The service cloud processor sends the item to the display device.

Abstract: A signal generating circuit for providing signals to a gate driving circuit of a display device is provided. The gate driving circuit has plural shift registers each having a main circuit unit and a discharge circuit unit. The discharge circuit units of at least some of the shift registers are configured to receive a pull-down control signal. The main circuit unit of a first stage shift register of the shift registers is configured to receive a starting signal. The signal generating circuit includes a first circuit unit that is configured to output the pull-down control signal and the starting signal to the gate driving circuit. The starting signal switches from a disabling voltage level to an enabling voltage level at a first time point. The pull-down control signal switches from a disabling voltage level to an enabling voltage level at a second time point before the first time point.

Abstract: A display panel is provided. The display panel may include a glass, a driver formed on a first surface of the glass, and a circuit layer formed on a second surface of the glass. The circuit layer may include a plurality of pixel circuits configured to drive a plurality of micro light emitting diodes (LEDs) forming a plurality of pixels of the display panel; a plurality of driving circuits which are respectively connected to the driver via wiring formed over at least one side surface of the glass, and configured to supply driving signals to the plurality of pixel circuits based on signals received from the driver; and a plurality of redundancy driving circuits connected to the plurality of respective driving circuits in parallel, the plurality of redundancy driving circuits having a same circuit structure as the plurality of respective driving circuits.

Abstract: An electroluminescent display device according to the present disclosure includes a first pixel, a second pixel sharing a data line, a reference voltage line, and an initialization voltage line with the first pixel and disposed adjoining the first pixel, a first gate line provided to supply a first gate control signal to the first pixel, a second gate line provided to supply a second gate control signal to the second pixel, a third gate line provided to supply a third gate control signal to the first and second pixels, and a fourth gate line and provided to supply a fourth gate control signal to the first and second pixels, wherein a first driving element included in the first pixel and a second driving element included in the second pixel have different channel widths.

Abstract: A shift register includes a first transistor, a second transistor, a pull-up node and a switch sub-circuit. A control electrode of the first transistor is connected to a signal input terminal, a first electrode of the first transistor is connected to a first voltage terminal, and a second electrode of the first transistor is connected to a first control node. A control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second voltage terminal, and a second electrode of the second transistor is connected to the first control node. The switching sub-circuit is connected to the first control node and the pull-up node, and is configured to control a line between the first control node and the pull-up node to be closed and opened.

Abstract: A pixel scan drive circuit including a switch unit, a pull-up output unit and a pull-down output unit is provided. In a scan signal output phase of a scanning cycle, the pull-down output unit outputs a first reference voltage in a scan signal to an output end according to a clock signal. In a maintenance phase of the scanning cycle, the switch unit controls the voltage of a pull-down node according to a switch control signal, thereby controlling the pull-down output unit to stop outputting the first reference voltage. In the maintenance phase, the pull-up output unit outputs a second reference voltage in the scan signal. The second reference voltage controls the pixel units to stop receiving the image data. Transistors in the switch unit are of different types from transistors in the pull-up output unit and the pull-down output unit. An array substrate and a display terminal are provided.

Abstract: An organic light-emitting display device includes: a data driver configured to divide one frame into an odd-numbered sub-frame and an even-numbered sub-frame, to divide frame data for implementing the one frame into odd-numbered sub-frame data and even-numbered sub-frame data, to provide the odd-numbered sub-frame data to the data lines in the odd-numbered sub-frame, and to provide the even-numbered sub-frame data to the data lines in the even-numbered sub-frame; an odd-numbered scan driver electrically connected to odd-numbered scan lines to provide an odd-numbered scan signal to the odd-numbered scan lines in the odd-numbered sub-frame; an even-numbered scan driver electrically connected to even-numbered scan lines to provide an even-numbered scan signal to the even-numbered scan lines in the even-numbered sub-frame; an emission driver to provide an emission signal to emission line groups formed by grouping the emission lines by two adjacent emission lines in the odd-numbered sub-frame and the even-numbered

Abstract: A signal processing circuit and a driving method thereof, a display panel and a driving method thereof, and a display device are disclosed. The signal processing circuit includes a shunting circuit and N buffer circuits. The shunting circuit includes N output nodes, the N buffer circuits are respectively connected with the N output nodes. The shunting circuit is configured to output input signals to the N output nodes respectively at N different time points in response to control signals. Each of the N buffer circuits is configured to buffer and output the input signal received by a corresponding output node. N is an integer great than or equal to 2.

Abstract: A display device includes: a pixel unit including pixels connected to data lines and scan lines, and signal output lines, where at least one signal output line of the signal output lines is connected to each of the scan lines through a contact point; a data driver disposed at one side of the pixel unit to drive the data lines; a scan driver disposed at the one side of the pixel unit together with the data driver to drive the scan lines; and a timing controller controlling the data driver and the scan driver. The data driver includes: output buffers outputting data signals to the data lines, respectively; and a slew rate controller adjusting a slew rate of the data signals by controlling a bias value supplied to the output buffers in units of pixel rows based on positions of the pixels and a change in the data signals.

Abstract: A structured light projector and a method for structured light projection are disclosed. The structured light projector includes a projection module, a processor. The projection module is configured to project an optical pattern onto a region of space, and includes a light source, a diffractive optical element and a liquid crystal lens. The light source is configured to generate a light beam. The diffractive optical element is configured to convert the light beam into the optical pattern. The liquid crystal lens is interposed between the light source and the diffractive optical element, and is configured to collimate the light beam. The processor is configured to generate a control signal depending on an environment temperature of the projection module for controlling the liquid crystal lens.

Abstract: Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.

Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods is disclosed. An apparatus includes a pull-up SCRC transistor, a pull-down SCRC transistor, and a charge transfer circuit. The pull-up SCRC transistor includes a pull-up gate terminal. The pull-down SCRC transistor includes a pull-down gate terminal. The charge transfer circuit is electrically connected between the pull-up gate terminal and the pull-down gate terminal. The charge transfer circuit is configured to transfer charge between the pull-up gate terminal and the pull-down gate terminal.

Abstract: A display device includes: a frame data counter configured to calculate frame information of an image displayed in a display area; a speed controller configured to determine a moving speed of the image; and a scenario determiner configured to determine a moving direction and moving amount of the image.

Abstract: A display device includes: a plurality of pixel blocks each including a plurality of pixels; a scan driver supplying a scan signal to the scan lines and to supply a control signal to the control lines; a data driver supplying an image data voltage or a low grayscale data voltage to the data lines; and a power supply supplying a reference voltage to the pixels, wherein the pixels are configured to receive the image data voltage during a first scan period of a frame, and to receive the low grayscale data voltage during a second scan period of the frame, and the reference voltage supplied to a first pixel row of at least one of the pixel blocks in the first scan period is different from the reference voltage supplied to a last pixel row of at least one of the pixel blocks in the first scan period.

Abstract: A display device includes: a plurality of pixels, each of which is connected to a corresponding one of a plurality of scan lines, and a scan driver including a plurality of stages, each of which supplies a scan signal to a corresponding one of the scan lines, each of the stages includes: a node controller which supplies a second output signal of a previous stage to a first node based on an input signal of a first clock terminal or a first output signal of the previous stage, a first inverter connected between the first node and a second node, a buffer which supplies a voltage of the second node to a first output terminal based on an input signal of a second clock terminal, and a second inverter connected between the first output terminal and a second output terminal.

Abstract: A display device includes a substrate including a first pixel region, a second pixel region connected to the first pixel region and having a smaller area than the first pixel region, and a peripheral region surrounding the first and second pixel regions, a first pixel in the first pixel region, a second pixel in the second pixel region, a first line connected to the first pixel, a second line connected to the second pixel, an extending line extending to the peripheral region and connected to any one of the first and second lines, a dummy part overlapping with the extending line for compensating a difference between load values of the first and second lines, a first power line in the peripheral region, and a conductive pattern overlapping with at least one region of the dummy part, and electrically connected to the first power line.

Abstract: A data driver includes a digital to analog converter configured to receive a reference gray voltage and image data, and configured to generate gray voltages corresponding to the image data, and an output buffer including a plurality of buffer circuits connected to an output terminal of the digital to analog converter, and configured to selectively receive one of the gray voltages.

Abstract: A non-rectangular display includes: a plurality of first signal lines extending along a first direction; a plurality of DC voltage lines extending along the first direction; and a plurality of second signal lines extending along the first direction, wherein a first DC voltage line of the plurality of DC voltage lines is between a first line of the plurality of first signal lines and a second line of the plurality of second signal lines, a second DC voltage line of the plurality of DC voltage lines is between a third line of the plurality of first signal lines and a fourth line of the plurality of second signal lines, and the first and third lines are adjacent to each other, or the second and fourth lines are adjacent to each other.

Abstract: Disclosed is a display device including: a display panel; a timing controller generating image data corresponding to an input image, and generating and outputting a first start signal, an on clock, and an off clock; a level shifter generating a second start signal in synchronization with the first start signal, generating gate clocks that swing to a predetermined voltage and have multiple phases, by using the on clock and the off clock, and outputting the generated gate clocks; a shift register including multiple stages connected to gate lines of the display panel, respectively, and outputting a scan signal sequentially to the gate lines by using the second start signal and the gate clocks; and a data driving circuit supplying a data voltage corresponding to the image data to data lines of the display panel in synchronization with the scan signal.

Abstract: A display panel, a control method and a display apparatus are provided. The display panel includes a first display area having a notched boundary and a second display area. The first display area includes a first pixel unit group comprising X white sub-pixel or sub-pixels and Y first single color sub-pixels, and the second display area includes a second pixel unit group comprising Y second single color sub-pixels, where X is an integer of at least 1 and Y is an integer of at least 1.

Abstract: The present disclosure provides a touch control display panel, a driving method thereof and a touch control display device. The touch control display panel includes a plurality of gate lines on a base substrate, a plurality of touch control lines above the plurality of gate lines and opposite to the plurality of gate lines, and a driving circuit, wherein the plurality of gate lines and the plurality of touch control lines extend along a same direction, and the driving circuit includes a timing controller, a control unit and a touch control driving unit. The timing controller is configured to output a gate driving signal to the control unit. The control unit is configured to generate touch control synchronization signal(s) according to the gate driving signal and output the touch control synchronization signal(s) to the touch control driving unit.

Abstract: The present disclosure relates to a gate driving circuit and a display device using the circuit. A gate driving circuit according to an aspect of the present disclosure comprises a Q node controller, a QB node controller, and an output unit generating a pulse-type output signal by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node, and the QB node controller controls the voltage of the QB node in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.

Abstract: A sensor system includes a sensing panel, at least one multiplexer and a controller. The sensing panel includes one or more sensing areas. The multiplexer is coupled to the one or more sensing areas through one or more connecting wire groups on the sensing panel, wherein each of the connecting wire groups includes one or more connecting wires. The controller is coupled to the at least one multiplexer via one or more control wires and one or more sensing wires. Each of the at least one multiplexer includes one or more switch groups each coupled between one of the one or more sensing wires and one of the connecting wire groups, and each of the switch groups includes one or more switches respectively controlled by one or more control signals transmitted through the one or more control wires.

Abstract: A liquid crystal display device includes a first substrate, a second substrate and liquid crystal. The first substrate includes pixel electrodes, a peripheral circuit and a dummy wiring. The peripheral circuit and the dummy wiring are provided outside a pixel area in which the pixel electrodes are arranged. The second substrate is opposed to the first substrate through the liquid crystal. The second substrate includes a translucent conductive film that is provided on an opposite side of the second substrate to a side where the liquid crystal is present. The dummy wiring is located on an outer peripheral side of the substrates than the peripheral circuit and is provided independently of the peripheral circuit in terms of circuit. The dummy wiring is grounded outside the first substrate.