Abstract: A display apparatus employs a pixel array section including pixel circuits forming a matrix, signal lines as columns, scan lines as rows and power-supply lines, and driving sections. The driving sections are a signal selector, a write scanner and a drive scanner. The signal selector provides an electric potential representing a gradation or a predetermined reference electric potential. The write scanner provides a control signal. The drive scanner provides a power-supply voltage changing the electric potential from high to low. The drive scanner drives adjacent power-supply lines as a group. The number of lines as a group is determined in advance. The drive scanner switches a power-supply voltage from high to low and vice versa, and applies the voltage to groups by shifting the phase from group to group. The voltage is supplied to a group at the same phase and switched the electric potential.

Abstract: A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.

Abstract: A picture signal processing unit having a first and a second double rate conversion section, a storage section, and a quadruple rate conversion section is provided. The first double rate conversion section inserts a first interpolation frame between a couple of successive original frames to output the original frames and the first interpolation frames. The second double rate conversion section generates a second and a third interpolation frames and allocates the second and the third interpolation frames between the couple of successive original frames to output the second and the third interpolation frames. The storage section stores the original frame and the first to the third interpolation frames. The quadruple rate conversion section sequentially reads out the original frame and the first to the third interpolation frames from the storage section in a quadruple rate to output the original frame and the first to the third interpolation frames.

Abstract: A driving apparatus applied in a liquid crystal display is disclosed. The driving apparatus at least includes a first latch, a second latch, an output buffer, and a slew rate enhancing module. The first latch is used to store a second data signal. The second latch is used to store a first data signal. The first data signal is previous to the second data signal. The slew rate enhancing module is used to compare the first data signal and the second data signal to generate a compared result, and correspondingly output a control signal to the output buffer according to the compared result to control a driving current of the output buffer.

Abstract: A method for fully-automatically aligning the quality of an image is provided. The method processes the video signals provided by the Video Graphic Array (VGA) display card in the computer system through the multi-sync display itself, and further interprets whether a computer host ID stored in the VGA display card or the computer host matches with a computer host ID stored in the multi-sync display, so as to avoid repetitious aligning to the same computer system, and achieve full automatic aligning to the quality of the image displayed on the multi-sync display. Therefore, even if the multi-sync display is situated under different computer hosts or VGA display cards and placed where an user cannot touch, the inconvenience of pressing a button on the multi-sync display to align the quality of the image displayed on the multi-sync display in conventional techniques can be prevented.

Abstract: An emissive type display device includes: a pixel array section having pixels ready for an active matrix driving system; a circuit for setting a peak luminance level of each display frame; and a driving circuit for variably controlling a total application period length of a driving voltage applied to a power supply line connected to each pixel and amplitude of the driving voltage so as to obtain a set peak luminance level, when the set peak luminance level is lower than a set value, the driving circuit dividing the driving voltage into a plurality of times of pulse waveform, and variably controlling the amplitude of the driving voltage at each output time according to the peak luminance level such that the amplitude of the driving voltage at least one output time is lower than a maximum driving voltage in a non-emission period.

Abstract: A pixel and organic light emitting display device. The pixel includes an organic light emitting diode, first through fourth transistors, and a second capacitor. The fourth transistor is for controlling an amount of current flowing through the organic light emitting diode. A first transistor is coupled between a second terminal of the second capacitor and a data line and is configured to turn on in response to a scan signal supplied to an i-th scan line. A second transistor is coupled between a first terminal of the second capacitor and an initial power source and is configured to turn on in response to an other scan signal supplied to an (i?1)-th scan line. A third transistor is coupled between the second terminal of the second capacitor and a reference power source and is configured to turn off in response to an emission control signal supplied to an (i+1)-th emission control line.

Abstract: The general field of the invention is that of display devices including a liquid-crystal matrix screen composed of elementary pixels, said screen including at least a first electrode used as voltage reference and called the “backplane,” a second electrode in the form of a matrix electronic network delivering the drive voltages for controlling the pixels and control electronics for said electrodes, said screen being used in the so-called “normally black” mode, that is to say that in the absence of applied voltages, the optical transmission of the pixels is substantially zero. In the device according to the invention, the “backplane” drive voltage is a variable periodic voltage, the amplitude of variation of this voltage being sufficient so that in the absence of voltage on the second electrode, the optical transmission of the pixels is sufficient to be detected by an observer.

Abstract: A display control system includes a display unit, a timing control unit. The display unit includes at least one source driving unit and a gate driving unit. The source driving unit includes an output buffer unit, a plurality of switches and a register unit. The output buffer unit is used to output image signals or high impedance signals. The switches are used to receive the image signals or high impedance signals. The gate driving unit is used to output gate driving signals. The timing control unit is used for controlling the timing of the source driving unit and the gate driving unit.

Abstract: A mobile terminal and a method of displaying 3D images thereon are disclosed. A display module in a mobile terminal may include a touchscreen and a controller. The touchscreen may be configured to display a plurality of icons and to receive a touch input that sets a 3D display setting for at least one of the icons. The controller may be configured to set the 3D display setting according to a pattern of the touch input. The touch pattern may determine whether the displayed 3D image of the icon is perceived to project or recede into the touch screen and/or a magnitude of a projection or recession.

Abstract: Provided are a data driving circuit, a display device, and a data driving method. The data driving circuit includes a clock generator configured to generate a clock signal from clock information included in a reception signal including the clock information, mode information and a body, a sampler configured to sample the reception signal according to the clock signal to obtain the mode information and the body that includes at least one of control information and data, a signal controller configured to determine whether or not the body corresponds to the control information with reference to the mode information, and generate a control signal corresponding to the control information according to a result of the determination, and a data driver configured to generate a data signal corresponding to the data according to the control signal.

Abstract: High efficiency drive circuitry for a group of parallel-connected light emitting devices, in which each device is driven in series by a respective source of bias current. The maximum voltage drop among the group of biased light emitting devices is determined and in response, a control voltage to drive all the light emitting device at the lowest effective voltage for the LED group is produced.

Abstract: A display device includes a display panel having pixels arranged at intersections of source lines and gate lines, a plurality of source drivers configured to dispersedly output image data signals to the source lines in response to source control signals and a data packet, a plurality of gate drivers configured to drive gate lines in response to gate control signals so as to be connected with pixels corresponding to the source lines, and a timing controller configured to output the data packet, the source control signals, and the gate control signals. At least one of the plurality of source drivers is configured to output carry information associated with an output of the image data signals, and at least another of the plurality of source drivers is configured to output the image data signals in response to the carry information.

Abstract: Disclosed is an oscillation circuit. The oscillation circuit supplies predetermined oscillation signals to a generating circuit having a divider, a phase comparator, and a generator. A clock signal generating section generates clock signals in a cycle based on the comparison results from the phase comparator. A clock signal mask section masks a part of the clock signals generated by the clock signal generating section to generate the predetermined oscillation signals and supplies the predetermined oscillation signals to the divider. The clock signal mask section masks a part of the clock signals such that the cycle of sampling signals generated by the generator is the same as a predetermined cycle which is the cycle of a clock for use in generating image signals.

Abstract: The present invention directs to a method for automatically compensating a common electrode voltage, comprising: calculating an average shift amount of a common electrode voltage according to gray scale data in a line on a displayed image, processing the average shift amount of the common electrode voltage to be a digital signal then converting it into an analog signal then into an average shift amount voltage waveform, and superposing it with a common electrode voltage waveform to form a new output signal waveform for driving the common electrode; the present invention also directs to a device for automatically compensating a common electrode voltage, comprising a data input module, a looking up module, a data operation module, a data encoding and converting module, a waveform generator and an operational amplification module.

Abstract: The present invention provides an intelligent, modular multimedia computer management system for coupling a series of remote computers to one or more user workstations to allow each user workstation to selectively access and control one or more remote computers. The computer management system incorporates a centralized switching system that receives keyboard, cursor control device, audio, and auxiliary peripheral device signals from the user workstation and transmits and applies the signals to the remote computer in the same manner as if the keyboard, cursor control device, audio input source, or auxiliary peripheral device of the user workstation were directly coupled to the remote computer. Also, the user workstation receives audio signals and auxiliary peripheral device signals from the remote computer. In addition, the multimedia computer management system transmits video signals from the remote computer over an extended range for display on the video monitor of the user workstation.

Abstract: A synchronous and asymmetrical display system and a method of operating the same are disclosed herein, where the synchronous and asymmetrical display system includes a single power module, a set of synchronous transmission lines, and display modules connected in series through the set of synchronous transmission lines, in which each display module includes a receive unit. This method includes the steps as follows. The first step is to command each display module to search a signal command from its receive unit and the set of synchronous transmission lines. Then, when one of the display modules acquire the power switch signal, the power switch signal is transmitted to the other display modules through the set of synchronous transmission lines, and one of the display modules generates a power control signal to control the power module.

Abstract: According to various embodiments of the invention, gamma curves for multiple pixel groups can be calibrated using look-up tables or by using reference voltage groups provided by gamma voltage generators so that the pixels can display multiple images with correct gray levels at different view angles. Therefore, color shift can be avoided or lessened without necessarily using extra circuitry on the display panel. Also, any related light transmittance or light utilization efficiency reduction may be decreased or eliminated.

Abstract: A system and method transmits graphic data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

Abstract: Dynamically managing power consumption of a computer, the computer including two or more graphics adapters, the computer having a number of graphics adapter configurations including one or more of the graphics adapters, where managing power consumption includes: monitoring, by a graphics driver, operation of a current graphics adapter configuration, the operation characterized by a graphics processing load; determining, in dependence upon the graphics processing load, whether operation of the current graphics adapter configuration conforms to predefined graphics processing criteria; if operation conforms, processing graphics, by the graphics adapter, for display with the one or more graphics adapters of the current graphics adapter configuration; and if operation does not conform, processing graphics, by the graphics adapter, for display with the one or more graphics adapters of another graphics adapter configuration.

Abstract: A drive circuit of a displayer for driving at least a pixel, including: an output stage coupled to the pixel and controlled by a pixel signal to switch an output voltage on the pixel; a calibration device coupled between the output stage and the pixel and including an input end controlled by a bias voltage further calibrating the brightness of the pixel; a stabilizing device coupled between the input end of the calibration device and the pixel signal for stabilizing the voltage on the input end of the calibration device to be at the level of the bias voltage after a variation; and a accelerating device coupled between the stabilizing device and a voltage source for generating the bias voltage and accelerating the speed stabilizing the voltage on the input end of the calibration device to be at the level of the bias voltage.

Abstract: An apparatus for driving a light scanner and method thereof are disclosed. The present invention includes an apparatus for driving a light scanner, which scans an image on a screen, the apparatus comprising the light scanner driven by a drive signal, a sensing unit sensing a driving of the light scanner, a pixel clock signal generating unit generating a pixel clock signal by detecting a 90-degree phase difference between the drive signal and a sensing signal sensed by the sensing unit, a sync signal adjusting unit adjusting vertical and horizontal sync signals of an input video according to the pixel clock signal and a driving unit driving the light scanner according to the adjusted horizontal and vertical sync signals.

Abstract: A drive circuit includes a generator and a driver. The generator generates a signal having a period and a varying amplitude during a driving portion of the period, and the driver is coupled to the generator and drives a plate of an electrostatically drivable plant with the signal. The drive circuit may be used to drive a mirror plate of a comb-drive MEMS mirror.

Abstract: Image processing and corresponding apparatus, methods and systems. The image processing includes controlling n number of data-line driver circuits included in a display apparatus, the data-line driver circuit driving n number of subpixels. Such controlling causes to display a moving picture image such that frame information of the moving picture image with first frame rate is displayed at a second frame rate, which is 1/n of the first frame rate, and the n number of subpixels included in each pixel are sequentially driven with a time shift, the time shift being 1/n of display period of single frame with the second frame rate.

Abstract: A stereo display including a display panel unit, a shutter glasses unit, and a backlight unit is provided. The display panel unit sequentially displays a right eye image and a left eye image according to a right eye synchronizing vertical signal and a left eye synchronizing vertical signal. The shutter glasses unit has a right eye glass and a left eye glass, wherein the right eye glass is synchronously opened according to the right eye synchronizing vertical signal, and the left eye glass is synchronously opened according to the left eye synchronizing vertical signal. The backlight unit provides a light source to the display panel unit, wherein the backlight unit is synchronously turned on and off according to the right eye synchronizing vertical signal, and the backlight unit is also synchronously turned on and off according to the left eye synchronizing vertical signal.

Abstract: The present invention discloses a backlight control circuit, comprising: a voltage supply circuit, under control by a control signal, for receiving an input voltage and generating an output voltage; a plurality of nodes for respectively indicating the current status of corresponding light emission device paths; and a high-low voltage comparison and amplifier circuit for generating the control signal according to a voltage difference between at least two nodes.

Abstract: Disclosed are a method of driving a display panel and a display apparatus using the same, in which a driving voltage is applied to a transistor provided in each pixel of the display to drive the transistor. A voltage level of the driving voltage applied to the transistor is adjusted every predetermined period and the changed driving voltage is applied to the transistor to prevent the operational reliability of the transistor from being lowered by a shift in the threshold voltage of the transistor.

Abstract: Methods for producing a remote current for driving a load, include one of sourcing and sinking a local current, Iref, through a distributed impedance line, at a first node thereof; the other of sourcing and sinking a remote current, Iref, through the distributed impedance line in response to the local current Iref; determining a rate change of voltage of the first node; and sourcing or sinking additional current, into or out of the first node, in response to the rate of change of voltage of the first node in order to settle the voltage on the distributed impedance line, and apparatus for providing such are disclosed.

Abstract: An LCD device adapted to cut costs through the simplification of circuitry is disclosed. The LCD device includes a timing controller that includes: an inter-integrated circuit driver and a memory which are configured to communicate with an external system using an inter-integrated circuit protocol; and a logic element configured to operate a first logic signal from a first write protection terminal of the external system with a second logic signal from a second write protection terminal of the inter-integrated circuit driver, and to apply the operated logic signal to the memory. The memory replies to the operated logic signal from an output terminal of the logic element and performs a write operation.

Abstract: A display apparatus including a plurality of pixels arranged in association with a plurality of gate lines and a plurality of data lines crossing the gate lines, a data driver configured to drive the data lines, a gate driving unit configured to drive the gate lines in synchronization with a gate control signal, and a timing controller configured to control the data driver and the gate driving unit in response to an image signal and a control signal from an exterior. The timing controller outputs the gate control signal including a plurality of pulses respectively corresponding to the gate lines and an enable time of each pulse of the gate control signal is set according to a position of a corresponding gate line of the gate lines.

Abstract: The present invention provides an active matrix image display apparatus including an organic EL element capable of efficiently arranging a wiring pattern on an insulating substrate compared to the related art. The present invention provides a dummy region arranged at the outermost periphery of a display unit as a scanning line coupling region or a pitch conversion region. A power supply scanning line is commonly used by a pixel circuit of an odd-numbered line and a pixel circuit of a following even-numbered line.

Abstract: A liquid crystal display (LCD) apparatus includes: multiple differential amplifier stages each of which is operable to generate, according to a bias current and an input voltage, an output voltage having a magnitude and a slew rate that correspond respectively to the input voltage and a magnitude of the bias current, and serving as a data voltage of a corresponding pixel unit of an LCD panel; multiple current sources controllable to generate and provide a plurality of the bias currents to the differential amplifier stages, respectively; and a bias voltage generating unit connected electrically to the current sources in a current mirror configuration for generating an input bias current and controlling the current sources to generate the bias currents according to a latch pulse signal. The slew rate of the output voltage corresponds to a logic state of the input bias current.

Abstract: A scan driving apparatus, includes scan driving blocks, each including a first and a second input terminal where a frame start or a scan signal of an adjacent scan driving block is input during forward and backward direction driving, respectively, wherein each of the scan driving blocks transmits a first scan direction signal instructing forward scan driving to a first transistor adjusting a clock signal in accordance with a signal input to the first input terminal, transmits a second scan direction signal instructing backward scan driving to the first transistor in accordance with a signal input to the second input terminal, and outputs the clock signal as a corresponding scan signal, the even numbered ones of the scan driving blocks receive a first clock signal as the clock signal, the odd numbered ones of the scan driving blocks receive a second clock signal as the clock signal.

Abstract: The present invention involves a technique of recognizing a demand for displaying a shutdown pattern when driving a liquid crystal panel in an inversion method and converting the inversion method into another inversion method causing no horizontal crosstalk. The present invention is achieved by providing an apparatus for controlling driving of a liquid crystal display device, comprising: a timing controller for processing input RGB data by a certain inversion method to supply the data to a data driver and, upon inputting of RGB data of a shutdown pattern, converting the RGB data by an inversion driving method causing no crosstalk to supply the data; a gate driver for outputting gate signals to each gate line of a liquid crystal panel in response to a gate signal control signal; and a data driver for supplying data voltages to each data line of the liquid crystal panel in response to a data signal control signal.

Abstract: A display driving system includes a timing controller configured to receive a data signal composed of image data and generate a control signal such as a clock signal; an interface configured to transmit the data signal and the control signal to a plurality of data drivers; the data drivers configured to receive the data signal and the control signal through the interface and supply received signals to a display panel to display an image; and a monitoring unit configured to feed back LOCK signals indicative of state information of the data drivers to the timing controller such that the data drivers can be monitored.

Abstract: A pixel clock generator includes a frequency divider 4 that generates a pixel clock PCLK based on a high frequency clock VCLK, a comparator 5 that calculates an error Lerr in the time obtained by integrating a cycle of the pixel clock PCLK for a target number RefN from a time when synchronization signals SPSYNC and EPSYNC are detected, a filter 6, and a frequency calculating unit 7 that sets a frequency dividing value M of the frequency divider 4. The filter 6 and the frequency calculating unit 7 calculate an average of a frequency of the pixel clock PCLK based on the error Lerr, determine a reference error value from the error Lerr in N-cycles, calculate offset values of the frequencies of N pieces of pixel clocks PCLK based on a difference between the reference error value and the error Lerr, and calculate the frequency dividing value M based on a result obtained by adding the circularly selected offset values and the average of the frequency of the pixel clock PCLK.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.

Abstract: When an image signal suitable for performing automatic adjustment of an effective image area and a dot clock is not output, the adjustment may be unsuccessfully performed. An effective image area detector detects an effective image area and determines whether an image in the effective image area is a blank image. If a synchronization signal detector determines that there exists a synchronization signal and if the effective image area detector determines that the image is not a blank image, a controller adjusts an area captured as image data by an input signal processor.

Abstract: A driving method of a semiconductor device for compensating variation in threshold voltage and mobility of a transistor is provided. A driving method of a semiconductor device including a transistor and a capacitor electrically connected to a gate of the transistor includes a first period where voltage corresponding to threshold voltage of the transistor is held in the capacitor, a second period where a total voltage of video signal voltage and threshold voltage is held in the capacitor holding the threshold voltage, and a third period where charge held in the capacitor in accordance with the total voltage of the video signal voltage and the threshold voltage in the second period is discharged through the transistor.

Abstract: A display apparatus and driving method is provided. The display apparatus includes a power supply unit which supplies a DC voltage, a switch unit which is connected to the power supply unit in series and performs a switching operation according to different switching signals, a transformer unit which switches a voltage applied to primary winding to secondary winding according to the switching operation of the switch unit, a synchronous rectifying unit which performs synchronous rectification with respect to the voltage induced to the secondary winding, and an output unit which outputs the rectified DC voltage.

Abstract: An organic light emitting diode (OLED) display is provided. The OLED display includes a display panel including pixels formed at each of crossings of a plurality of gate lines and a plurality of data lines, a monitoring signal line formed along an outer area of the display panel, a first signal supply unit that supplies a monitoring signal to the monitoring signal line and generates a first power control signal, a power supply unit that supplies a high potential driving voltage and a low potential driving voltage to the pixels, and a second signal supply unit that monitors the monitoring signal and generates a second power control signal. If the monitoring signal is not monitored, the second signal supply unit controls the power supply unit through the second power control signal and allows the power supply unit to stop supplying one of the high and low potential driving voltages to the pixels.

Abstract: A display drive apparatus performs a display drive of a display panel on the basis of display data and comprises a selection drive section for applying a selection signal to each of display pixels arranged in each row of the display panel, a data drive section for generating a drive signal based on the display data, and a power source drive section for setting at least a row as a writing region and at least a region as a designated region separated from the writing region by the number of one or more rows and sequentially moving correspondingly to moving of the writing region, and the power source drive section supplies a power source voltage for operating each display pixel to make each display pixel corresponding to the row of the writing region and each display pixel corresponding to the row of the designated region perform non-display operation.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a liquid crystal display panel including data lines and gate lines crossing each other and liquid crystal cells, a timing control signal generating unit, a data drive circuit supplying a data voltage to the data lines, and a gate drive circuit. The timing control signal generating unit generates a first gate timing control signal for controlling a scan direction of the liquid crystal display panel in a sequential direction and a second gate timing control signal for controlling the scan direction in a reverse sequential direction. The gate drive circuit supplies a gate pulse to the gate lines while a shift direction of the gate pulse changes in response to the first and second gate timing control signals.

Abstract: A device for driving an image display device that includes an image display panel, a plurality of drivers for driving the image display panel, a Low Voltage Differential Signaling (LVDS) transmission unit for converting external image data and a plurality of control signals including frame ratio setting signals into LVDS signals and transmitting the same, an LVDS reception unit for converting the image data and the plurality of control signals including frame ratio setting signals OP1, OP1 converted into the LVDS signals and transmitted thus into TTL signals and forwarding the same, and a timing controller for aligning the image data to fit to the display frame ratio according to the frame ratio setting signal and the plurality of control signals from the LVDS reception unit and supplying the same to the plurality of drivers, for displaying the image on the image display panel.

Abstract: A method to drive a display device with electron sources displaying grey scales divided into two families. The display device includes one or more rows and one or more columns. An intermediate potential lies between a first potential and a second potential. To display a grey level of the first family, the column voltage is pulse width modulated between the intermediate potential and the second potential right at the start of the row selection period. To display a grey level of the second family, the column voltage is pulse width modulated between the intermediate potential and the first potential from a determined instant of the row selection period.

Abstract: A liquid crystal display includes a first substrate. A plurality of scan lines and a plurality of data lines are disposed on the first substrate to define a plurality of pixel regions. A plurality of common line groups is disposed on the first substrate, and each of the common line groups includes a plurality of common lines parallel to the scan lines. And, at least, a voltage regulator is electrically connected to one of the common line groups, wherein the voltage regulator can stabilize the pixel voltage to decrease the flicker of the liquid crystal display.

Abstract: A driving circuit for driving a display panel includes a dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratioless shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.

Abstract: A low voltage differential signal (LVDS) output stage including a display signal digital circuit, a data parallel-to-serial (P2S) circuit and a transmitting circuit is provided. The display signal digital circuit generates a display signal and a display clock signal synchronous to each other according to a first frequency multiplication clock signal. The data P2S circuit samples the display signal according to a second frequency multiplication clock signal, so as to generate a serial data signal and a serial clock signal. The first frequency multiplication clock signal and the second frequency multiplication clock signal have a relationship of frequency multiplication. The data P2S circuit includes an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second frequency multiplication clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second frequency multiplication clock signal.

Abstract: An integrated circuit device includes: a data driver that drives a plurality of data lines of an electro optical device; and a data distribution circuit that supplies data to the data driver, wherein the data driver includes an odd numbered data line driver circuit for driving odd numbered data lines among the plurality of data lines, an even numbered data line driver circuit for driving even numbered data lines among the plurality of data lines, an odd numbered data line latch circuit provided for the odd numbered data line driver circuit, and an even numbered data line latch circuit provided for the even numbered data line driver circuit; and the data line distribution circuit, upon receiving time serially inputted image data, supplies odd numbered data line image data for the number of multiplexes to the odd numbered data line latch circuit, and supplies even numbered data line image data for the number of multiplexes to the even numbered data line latch circuit.

Abstract: A monitor control system capable of reprogramming the function of a LCD monitor. The monitor control system utilizes VGA signal lines for video signal transmission during normal mode of operation and the same VGA signal lines for transmitting erase/record commands and data when the erasable programmable ROM inside the monitor demands reprogramming. Using an isolator circuit in the monitor control system for isolating an erase/record pathway of an erasable programmable ROM from a normal video pathway, data within the erasable programmable ROM can be modified without opening up the monitor casing. Hence, the modification of monitor function is much more convenient.