Abstract: A method of differently producing driving clock signals for a shift register of a gate lines driving circuit of a Liquid Crystal Display (LCD), the method includes the steps of determining whether an ambient temperature is greater than or not in comparison to a predetermined threshold temperature; in response to the determining indicating that the ambient temperature is greater, using a first ON voltage and a first charge canceling method; and in response to the determining indicating that the ambient temperature is not greater, using a second ON voltage and a second charge canceling method, where the second ON voltage is different from the first ON voltage and where the second charge canceling method is different from the first charge canceling method. The second charge canceling method may have a shorter duration than that of the first charge canceling method. The second ON voltage may be greater than the first ON voltage.

Abstract: A method of refreshing a memory array for a driving circuit includes generating a word-line scanning signal corresponding to a word-line of a memory array, and turning on a plurality of memory cells corresponding to the word-line of the memory array according to the word-line scanning signal to refresh the plurality of memory cells corresponding to the word-line of the memory array, wherein the memory has a first number of bit-lines and a second number of word-lines.

Abstract: Provided is a display device including a pixel array forming by arranging a plurality of pixels whose display grayscale are controlled according to a pixel signal written, a signal line drive unit that outputs a pixel signal, to a plurality of signal lines, with a polarity according to a polarity signal, a scan line drive unit that drives the plurality of signal lines and performs a writing of the pixel signal output to the signal line into the pixels, a polarity signal generation unit that generates the polarity signal instructing the polarity of the pixel signal to be reversed, and supplies the result to the signal line drive unit, and a frame cycle set unit that generates the vertical start pulse in such a manner that a period of the number of vertical clocks that is not a multiple of the N is one frame period.

Abstract: The apparatus for driving LED display includes a system control unit having a synchronization signal generator configured to generate a synchronization start signal and a plurality of phase locked loop circuits. Each of the phase locked loop circuits includes a divider coupled to the voltage controlled oscillator and configured to change the sequence of dividing ratios over a modulation period, a sigma delta modulator configured to generate a sequence of random numbers to the divider, and a spread spectrum modulation depth controller coupled to the sigma delta modulator and configured to receive the synchronization start signal from the synchronization signal generator. Upon receipt of the synchronization start signal, the spread spectrum modulation depth controller starts a spread spectrum modulation.

Abstract: A display device includes a data driver for applying a data signal to a data line; a gate driver for applying a gate signal to a gate line; a level shifter for shifting a voltage level of a signal applied to the gate driver; and a signal controller for controlling the data driver, the level shifter, and the gate driver, wherein when a signal exchange between the data driver and the signal controller has an abnormality, the signal controller maintains a control signal applied to the level shifter in an off level.

Abstract: An organic light emitting display is provided. The organic light emitting display includes a display unit coupled to scan lines and data lines and including pixels configured to receive first and second power sources, and a DC-DC converter for generating the first and second power sources. The DC-DC converter includes first and second power source generating units for generating the first and second power sources from an input power source and for outputting the first and second power sources to first and second output ends, a controller for controlling driving of the first and second power source generating units, and first and second short sensing units for outputting first and second short sensing signals to the controller when voltages of the first and/or second output ends are greater than or equal to corresponding first and second reference voltages.

Abstract: A display device includes a panel displaying an image using image data and including a common electrode to which a common voltage is applied; a timing controller providing the image data to the panel and outputting a correction voltage corresponding to the image data; and a power supply unit generating a compensation voltage using a panel common voltage and the correction voltage and providing the compensation voltage to the panel, wherein the panel common voltage is a voltage measuring the common voltage applied to the panel.

Abstract: A method of driving a display panel is disclosed. In one aspect, the display panel includes a plurality of pixels arranged in odd and even rows and a plurality of odd and even gate lines respectively connected to the pixels of the corresponding odd and even rows. The method includes outputting odd gate signals to the odd numbered gate lines during two consecutive subframes and outputting even gate signals to the even numbered gate lines during two consecutive subframes. A frame is divided into two subframes.

Abstract: When an image signal suitable for performing automatic adjustment of an effective image area and a dot clock is not output, the adjustment may be unsuccessfully performed. An effective image area detector detects an effective image area and determines whether an image in the effective image area is a blank image. If a synchronization signal detector determines that there exists a synchronization signal and if the effective image area detector determines that the image is not a blank image, a controller adjusts an area captured as image data by an input signal processor.

Abstract: An OLED device is disclosed that enhances display quality by minimizing capacitance deviation between data lines of the OLED device. The capacitance deviation may be minimized by utilizing an expansion portion of a power line of the OLED device. The capacitance deviation may also by minimized by utilizing an overlap pattern that overlaps a plurality of the data lines.

Abstract: A method of deserializing signals output from a master can include generating an indication signal based on occurrence of a first signal pattern input via a data line during a first period and occurrence of a second signal pattern input via a clock line during the first period and enabling a deserializer in response to the indication signal and deserializing serialized video data input via the data line during a second period following the first period, in response to a clock signal input via the clock line during the second period. Related circuits are also disclosed.

Abstract: A flat panel display includes a signal generator to generate data signals to respective data lines via an output terminal or to generate a control signal for controlling switches. The signal generator includes a first voltage supply unit to supply, to the output terminal, a voltage of a first voltage sources, a voltage stabilizing unit to raise or drop the voltage supplied to the output terminal, and a second voltage supply unit to supply, to the output terminal, a voltage from a second voltage source, after the voltage of the output terminal is raised or dropped.

Abstract: A semiconductor device includes a plurality of thin film transistors of a single channel formed on an insulating substrate, and a buffer circuit including an outputting stage; a first inputting stage; a second inputting stage; a seventh thin film transistor; and an eighth thin film transistor.

Abstract: An organic light emitting display includes a display unit including pixels coupled to scan lines, first control lines, second control lines, and data lines, a control line driver configured to supply a first control signal and a second control signal to the pixels through the first control lines and the second control lines, a first power source driver for applying a first power to the pixels of the display unit, and a second power source driver for applying a second power to the pixels of the display unit. At least one of the first power or the second power is applied to the pixels of the display unit as voltage values having different levels during one frame. The first and second control signals and the first and second powers are concurrently provided to all of the pixels of the display unit.

Abstract: A shift register circuit includes plural stages of shift registers. Each stage of shift register includes a pull-up circuit, a first driving circuit and a voltage-stabilizing circuit. The pull-up circuit is used for charging a first node. The first driving circuit is electrically connected with the first node. According to a voltage level of the first node, a corresponding control signal is outputted from an output terminal of the first driving circuit. The voltage-stabilizing circuit is electrically connected with the output terminal of the first driving circuit for stabilizing the control signal from the first driving circuit. Some circuits of some other shift registers are controlled according to the control signal.

Abstract: Systems, methods, and devices for calibrating an electronic display to reduce or eliminate a mura artifact are provided. The mura artifact may be due to differential behavior of common voltage layers (VCOMs) in the electronic display. One method for reducing or eliminating the mura artifact may involve setting pixels of the electronic display to a first gray level and measuring a luminance difference between light and dark areas of a mura artifact on the electronic display. A value of an operating parameter of the electronic display may be adjusted while monitoring the luminance difference measurement. A value of the operating parameter that causes the luminance difference measurement to be within a specified range of acceptable luminance difference measurement values may be stored in the electronic display.

Abstract: A display device includes a display panel including data lines, a source driver positioned at one side of the display panel, and a timing controller which sequentially stores digital video data in a plurality of line memories, starts to generate an output data enable signal in conformity with a first writing start timing of a last line memory of the line memories, adjusts a pulse width of the output data enable signal of each horizontal pixel line based on a previously determined charge time graph, reads out the digital video data from the line memories in synchronization with rising edges of the output data enable signal, and generates a source output enable signal having the same pulse width each time each line memory finishes reading out the data.

Abstract: A liquid crystal display device discharges residual charge within the liquid crystal display panel. The liquid crystal display device comprises pixels defined by gate lines and data lines intersecting with each other and switching elements for driving the plurality of pixels; a level shifter comprising a first transistor connected between a gate-on voltage terminal and an output terminal and a second transistor connected between a gate-off voltage terminal and the output terminal to selectively output either the gate-on voltage or gate-off voltage to the plurality of gate lines; and a discharge circuit forming a discharge path connecting the gate-off voltage terminal and the ground terminal. The second transistor is turned on during the power-on of the liquid crystal display panel to apply the gate-off voltage. The discharge circuit is turned on to discharge the residual charge of the liquid crystal display panel through the discharge path.

Abstract: A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.

Abstract: Embodiments may be directed to a display panel includes a base substrate including a display region having a plurality of pixels and a non-display region adjacent to the display region, a connecting line in the non-display region and including at least a first input pad, a second input pad, and an output pad, and an insulating layer on the connecting line. The insulating layer includes at least one first contact hole exposing at least a portion of the first input pad, at least one second contact hole exposing at least a portion of the second input pad, and at least one third contact hole between the first contact hole and the second contact hole. A first contact electrode, a second contact electrode, and a dummy contact electrode are disposed at the first, second and third contact holes, respectively.

Abstract: An electronic apparatus system is provided. The electronic apparatus system includes a register, a display mode computation unit, a display device and a control circuit. The register stores image information having a data input refresh frequency. The display mode computation unit generates a display mode control signal by computation based on an image characteristic categorization of the image information. The display device includes a display panel having a plurality of pixel units. The control circuit controls a display mode and a drive mode of the display panel according to the display mode control signal to further adjust a display refresh frequency of the display panel.

Abstract: A synchronizing method and a system for marks on electronic maps and a recording medium using the same are provided. In the present synchronizing method, an input signal is received by a first electronic device, so as to draw a mark on the electronic map displayed thereon. The mark is then converted into positioning information of a plurality of positioning points on the electronic map and transmitted to a second electronic device via a wireless transmission network, wherein the positioning information is used for drawing the positioning points on the electronic map displayed on the second electronic device so as to reconstruct the mark. Accordingly, the mark on the electronic map of both communication ends can be synchronized.

Abstract: The display device including a pixel circuit has a first line, a transistor, a light emitting element, and a second line. The transistor is located between the second line and an electrode of the light emitting element. Either the first line or the second line is wired in a region that overlaps a light emitting region of the light emitting element in a lamination direction of layers. The second line intersects the first line outside of the light emitting region and overlaps a non-light emitting region of the light emitting element.

Abstract: In one embodiment, the converter is configured to receive a first sync signal from a display driver and to convert the first sync signal into a second sync signal. The second sync signal is for controlling image sensing.

Abstract: The present invention relates to a source driver of a display apparatus, and relates to a source driver for display apparatus insensitive to power noise, which forcibly decides an internal operation state as normality in a specific period including a power noise generation period and operates insensitively to the power noise. Accordingly, the display apparatus can normally output an image voltage even though power noise occurs.

Abstract: To control the state of an input signal and output signal of a sequential circuit in order to prevent a malfunction of an electronic circuit. An electronic circuit includes a sequential circuit and a control circuit. A first signal, a second signal, and a third signal are input to the sequential circuit as a start signal, a clock signal, and a reset signal, respectively. The sequential circuit outputs, as an output signal, a fourth signal whose state is set in accordance with the state of the inputted first signal, second signal, and third signal. The control circuit controls the state of the third signal input to the sequential circuit.

Abstract: A novel driving method is provided in which source line inverting drive or dot inverting drive is performed for a case of driving a plurality of source lines by one D/A converter circuit in a source signal line driver circuit of an active matrix image display drive that corresponds to digital image signal input. In a first driving method of the present invention, two systems of grey-scale electric power supply lines are supplied to a source signal line driver circuit in order to obtain output having differing polarities from a D/A converter circuit, switches for connecting to the two systems of grey-scale electric power supply lines are prepared in each D/A converter circuit, the grey-scale electric power supply lines connected to each D/A converter circuit are switched in accordance with a control signal input to the switches, and source line inverting drive or dot inverting drive are performed.

Abstract: There is provided an organic light emitting display capable of minimizing noise. A method of driving the organic light emitting display includes setting pixels included in horizontal blocks into a non-emission state, the pixels charging voltages corresponding data signals, the pixels starting to emit light at different times in units of the horizontal blocks, and emitting light from the pixels according to the charging voltages.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: A method of driving a display panel is provided. The method includes displaying a first image on at least one odd-numbered horizontal line of the display panel along a first direction and a second direction during a first period of a frame period and displaying a second image on at least one even-numbered horizontal line of the display panel along the first direction and second direction during a second period of the frame period.

Abstract: In a data driving method for driving a display panel, a data driving circuit, and a display apparatus, the data driving method includes receiving a digital driving voltage and an analog driving voltage. The analog driving voltage is switched, after the digital driving voltage is received and a specific driving time elapses. A digital data signal is converted to an analog data signal using the analog driving voltage. The analog data signal is output to a data line of the display panel.

Abstract: A source driver and an operation method thereof are provided. The operation method includes following steps. A data signal is provided to the source driver. The operating current of the source driver is reduced to an abnormal operating level in period from the source driver is reset to before a pixel data of the source driver is appeared in the data signal. The operation current of the source driver is restored to a normal operating level when the pixel data of the source driver is appeared in the data signal.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: It is an object to reduce power consumption of a display device which can perform multi-gray scale display and to suppress deterioration of an element included in the display device. The usage of a display device includes a first initialization period in which the gray scale level of an entire pixel portion is converted into a first gray scale level and a second initialization period in which the gray scale level of an entire pixel portion is converted into a second gray scale level. In the first initialization period, scanning of a plurality of signals and weighting of a holding period of each signal are performed. Therefore, the small number of scanning of signals can realize voltage application for an appropriate time with respect to each of a plurality of gray scale storage display elements included in the display device.

Abstract: In one or more example embodiments, a display controller includes a stable pixel writing period in one horizontal period in a display device, the stable pixel writing period being a period during which a voltage outputted from a gate driver is at a high level. The display controller also includes a first stable pixel writing period determination circuit which determines, by using a reference signal independent from the frame rate in the display device, the stable pixel writing period during which the voltage is at the high level. Thus, the display controller can be provided in which, regardless of whether and how the frame rate is changed, the stable pixel writing period can be of a target length.

Abstract: A liquid crystal display includes a signal controller to generate a plurality of start pulse signals based on a plurality of eye blinking signals during a predetermined mode of operation. The start pulse signals are generated in a manner different from a vertical synchronization signal. The start signals may be generated to have an irregular spacing which corresponds to the blinking signals, which may be different from a constant spacing used during display of moving images. The predetermined mode may be a still image mode.

Abstract: In one embodiment of the present application, a display controller is capable of changing a refresh rate, indicative of how often a screen displayed on a display device having a plurality of pixels is switched, between a low refresh rate of 40 Hz and a normal refresh rate of 60 Hz and generates (i) a dot clock (reference clock) serving as a timing signal indicative of a timing of operation in the display device, (ii) video data indicative of an image to be displayed on the screen, (iii) Hsync for defining a horizontal period of a display on the screen, and (vi) Vsync for defining a vertical period of the display on the screen, so as to supply the dot clock, the video data, Hsync, and Vsync to the display device, wherein the display controller includes a dot clock generation circuit for generating the reference clock whose frequency is constant without depending on a change of the refresh rate.

Abstract: A display system includes a plurality of light emitting units configured to float in a fluid medium such that each light emitting unit is movable, each light emitting unit including a light emitting element configured to selectively emit light, a communication element operable to receive instruction data to control operation of the light emitting element; and a power element configured to provide power to at least the light emitting element, and an image capture element configured to receive light emitted by at least one light emitting unit and to generate image data based on the light received and a controller configured to generate the instruction data based at least on a comparison of the image data to a desired image and transmit the instruction data to the communication element to control the light emitting element such that the display system provides the desired image.

Abstract: A display device includes an image signal processing unit to output a high-speed image signal with the aid of an image interpolation unit outputting a low-speed image signal. The display device includes an image signal processing unit to receive a primitive image signal having a first frequency and to output a 4× image signal having a second frequency. The second frequency is four times the first frequency. The display device includes a display panel displaying an image corresponding to the 4× image signal. The primitive image signal includes an (n?1)-th frame (where n is a natural number) and an n-th frame. The image signal processing unit includes a first image interpolation unit and second image interpolation unit, which receive the (n?1)-th frame and the n-th frame and output a 2× image signal including at least one interpolated frame.

Abstract: A display device including a scanning circuit formed using single conductivity type thin-film transistors suppresses threshold changes in the thin-film transistors forming the scanning circuit by controlling a circuit for maintaining an internal node of the unit circuits forming the scanning circuit at a constant potential is controlled by a clock signal or a pulse signal having a smaller amplitude than the amplitude of an output signal.

Abstract: Disclosed is a light source unit which emits fluorescence light to a display element which displays an image by using the fluorescence light including an excitation light source which emits excitation light, a fluorescent plate including a fluorescence emission region on a surface of a circular substrate which emits the fluorescence light by the fluorescence emission region being irradiated with the excitation light from the excitation light source, a drive unit which rotates the fluorescent plate in a circumferential direction and a control unit which controls the excitation light source and the drive unit.

Abstract: An image projection device includes: a drive controller that causes generation of light of a specified color tone by a combination of light to be transmitted by a liquid crystal panel to project image data onto a projection plane; an image capturing controller that receives a synchronization signal that specifies a period in which the liquid crystal panel does not transmit light from the drive controller and causes capturing of an image of the projection plane according to the period that is specified by the synchronization signal; an illuminated image detector that detects, from the captured image of the image data, an illuminated image that is illuminated by an illuminating device on the projection plane; and an illuminated image generator that generates projection image data obtained by combining given image data in a position in which the illuminated image is detected.

Abstract: According to one embodiment of the present invention, a timing controller for a display, includes a first unit, a second unit and a third unit. The first unit is configured to generate an image signal from a first input signal. The second unit is configured to generate a multitude of timing signals and a control signal from a multitude of second input signals, the control signal being generated after the multitude of timing signals are generated. The third unit is configured to generate a multitude of first signals from the multitude of timing signals after receipt of the control signal from the second unit. The image signal and the multitude of first signals are configured to drive the display when the timing controller is connected to the display.

Abstract: A semiconductor IC including a supply voltage generator, one or more first circuit blocks, and one or more second circuit blocks. The supply voltage generator is configured to generate a first supply voltage and a second supply voltage based on an external supply voltage, and to provide the first supply voltage to a first power bus and the second supply voltage to a second power bus. The first circuit blocks are connected between the first power bus and the second power bus, and the second circuit blocks are connected between the second power bus and ground.

Abstract: The present invention relates to a digital display plotter for plotting images on a digital display device 18. A cursive imagery generator 12 generates imagery inputs at a plurality of respective update phases during a refresh period of the display device. A control 20 for the display device activates selected pixels of the digital display device in response to respective said imagery inputs, activation being controlled subsequent to each update phase during a refresh period. An input store 14, 16 associates each cursively generated imagery input with an update phase that the imagery input was generated during a refresh period. The control 20 is responsive to the input store and configured to deactivate the selected pixels activated in response to each imagery input dependent on the associated update phase of each imagery input.

Abstract: A display includes a display panel, a pixel driving unit and a power supply for supplying power to the pixel driving unit. The display panel includes a plurality of pixels arranged in a matrix manner. The pixel driving unit is used for driving the pixels. The power supply includes an input power source, an output capacitor for providing an output voltage, and a control unit for controlling the input power source, such that in a frame period, the input power source charges the output capacitor during the non-refreshing duration of the pixels by the input power source and stops charging the output capacitor during the refreshing duration of the pixels.

Abstract: Described herein are apparatus, system, and method for controlling temperature drift and/or voltage supply drift in a digital phase locked loop (DPLL). The apparatus comprises a DPLL including a digital filter to generate a fine code for controlling a frequency of an output signal of a digital controlled oscillator (DCO) of the DPLL; a logic unit to monitor the fine code and to generate a compensation signal based on the fine code; and a voltage adjustment unit to update a power supply level to the DCO based on the compensation signal, wherein the updated power supply level to cause the digital filter to generate the fine code near the middle of an entire range of the fine code across various temperatures, and wherein the digital filter to generate the fine code near the middle of the entire range across power supply drift.

Abstract: A shift register for reducing size of a display apparatus through a reduction in falling edge time of a scan pulse. The shift register includes stages for sequentially outputting carry pulses and scan pulses. Each stage includes a carry output unit for generating a carry pulse, based on a first discharge voltage and a clock pulse having a low-level voltage with a level substantially equal to the first discharge voltage, and supplying the carry pulse to at least one of an upstream stage and a downstream stage, a scan output unit for generating a scan pulse, based on a second discharge voltage having a higher voltage value than the first discharge voltage and the clock pulse, and supplying the scan pulse to a corresponding gate line, and a node controller for controlling voltages at nodes connected to the carry output unit and the scan output unit.

Abstract: A display device includes display panel includes a first source driver including a first input terminal and a first output terminal connected to the display panel; a first gate driver including a first input-output terminal, a second input-output terminal connected to the first input-output terminal, and a second output terminal connected to the display panel; a timing controller including a first terminal for outputting or inputting a first signal to or from the first input-output terminal and a second terminal; a first signal line connected to the first terminal; a second signal line connected to the second terminal; and a third signal line connected to the first source driver and the timing controller for transmitting a second signal indicating a display direction of the image data. The first source driver operates according to the first signal from the first terminal or the second terminal selected.

Abstract: A monitor control system capable of reprogramming the function of a LCD monitor. The monitor control system utilizes VGA signal lines for video signal transmission during normal mode of operation and the same VGA signal lines for transmitting erase/record commands and data when the erasable programmable ROM inside the monitor demands reprogramming. Using an isolator circuit in the monitor control system for isolating an erase/record pathway of an erasable programmable ROM from a normal video pathway, data within the erasable programmable ROM can be modified without opening up the monitor casing. Hence, the modification of monitor function is much more convenient.