Abstract: A multithreaded rendering software pipeline architecture dynamically reallocates regions of an image space to raster threads based upon performance data collected by the raster threads. The reallocation of the regions typically includes resizing the regions assigned to particular raster threads and/or reassigning regions to different raster threads to better balance the relative workloads of the raster threads.

Abstract: In general, this disclosure relates to techniques for using graphics instructions and state information received from a graphics device to visually create a graphics image. Performance analysis may also be conducted to identify potential bottlenecks during instruction execution on the graphics device. One example device includes a display device and one or more processors. The one or more processors are configured to receive a plurality of graphics instructions from an external graphics device, wherein the graphics instructions are executed by the external graphics device to display a graphics image, and to receive state information from the external graphics device, wherein the state information is associated with execution of the graphics instructions on the external graphics device. The one or more processors are further configured to display, on the display device, a representation of the graphics image according to the graphics instructions and the state information.

Abstract: Backlit LCD displays are becoming commonplace within many vehicle applications. The unique advantage of this invention is that it optimizes system power savings for display of low dynamic range (LDR) images by dynamically controlling spatially adjustable backlighting. This is accomplishes through use of a control technique that takes into account the sequential nature of the video display process.

Abstract: A software layer is disposed between an application and a driver. In use, the software layer is adapted to receive an object from the application intended to be rendered by a first graphics processor. Such software layer, in turn, routes the object to a second graphics processor, based on a policy.

Abstract: A circuit arrangement, program product and method stream level of detail components between hardware threads in a multithreaded circuit arrangement to perform physics collision detection. Typically, a master hardware thread, e.g., a component loader hardware thread, is used to retrieve level of detail data for an object from a memory and stream the data to one or more slave hardware threads, e.g., collision detection hardware threads, to perform the actual collision detection. Because the slave hardware threads receive the level of detail data from the master thread, typically the slave hardware threads are not required to load the data from the memory, thereby reducing memory bandwidth requirements and accelerating performance.

Abstract: A system and method force a display device to receive the output produced by a graphics processing unit that is configured as the video graphics array (VGA) boot device for display of critical system screens. A hybrid computer system that includes multiple graphics processors configures a display multiplexor to select image data from one of the multiple graphics processing units for output to the display device. When a critical system event occurs and the graphics processing unit that is selected is not configured as the VGA boot device, system basic input/output system (BIOS) interfaces are used to configure the multiplexor to select the one graphics processing unit that is configured as the VGA boot device to output the critical system screen to the display device.

Abstract: In processing a game scene for display, in one embodiment input controller position information from a host memory is provided directly to a graphics processor rather than first being processed by a 3D application in a host processor. This results in more direct and timely processing of position information and reduces the number of 3D processing pipeline steps the controller position information must pass through thus reducing the user's perceived latency between moving the input controller and seeing the displayed results. In another embodiment, the input controller position information is provided directly from an input controller to a graphics card or subsystem rather than first going through a host processor or memory. This results in even more direct and timely processing of position information by further reducing the number of 3D processing pipeline steps the controller position information must pass through thus further reducing the user's perceived latency.

Abstract: A method of server site rendering 3D images on a server computer coupled to a client computer wherein the client computer instructs a server computer to load data for 3D rendering and sends a stream of rendering parameter sets to the server computer, each set of rendering parameters corresponding with an image to be rendered; next the render computer renders a stream of images corresponding to the stream of parameter sets and the stream of images is compressed with a video compression scheme and sent from the server computer to the client computer where the client computer decompresses the received compressed video stream and displays the result in a viewing port. The rendering and communication chain is subdivided in successive pipeline stages that work in parallel on successive rendered image information.

Abstract: A method includes performing a task in response to a request of a secondary user interface of a secondary device. The method also includes calculating a utilization of a graphics processing unit of a machine based on the task performed by the graphics processing unit. The method further includes determining the utilization, through a processor, based on a comparison of a consumption of a computing resource of the graphics processing unit and a sum of the computing resource available. The method furthermore includes performing another task in response to the request of another secondary user interface of another secondary device. The method furthermore includes calculating another utilization of another graphics processing unit based on the another task performed by the another graphics processing unit. The method furthermore includes determining the another utilization based on the comparison of a consumption of the computing resource of the another graphics processing unit.

Abstract: A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems.

Abstract: An image processing system in the medical field is provided. The system for processing image data includes at lest two graphics processors, at least one renderer module for rendering image data and at least one reconstruction module for volume reconstruction. In a first operating mode of the system in which at least one reconstruction module is inactive, the instructions of at least one renderer module is able to be executed by at least two of the graphics processors. In a second operating mode of the system in which at least one reconstruction module is active, the instructions of at least one renderer module and the instructions of at least one reconstruction module is able to be executed separately on different graphics processors of the said graphics processors. During operation in one of the two operating modes, a switch can be made to the other operating mode in each case.

Abstract: There is provided an information processing apparatus, including a first processing unit capable of processing an image, a second processing unit capable of processing the image in parallel for each unit dividing the image, and a controller section configured to perform a control to select one of the first processing unit, the second processing unit, and both of them as a subject or subjects processing the image, to divide, in a case where both the first processing unit and the second processing unit are selected, the image into a first region and a second region, and to assign processing of an image of the first region and processing of an image of the second region, which are obtained by the division, to the first processing unit and the second processing unit, respectively, to cause the first processing unit and the second processing unit to perform the processing.

Abstract: A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203—0 to 203—3 access data at an external memory system or local memories 204—0 to 204—3 according to a thread under control from a host processor. Processor units (PU) arrays 202—0 to 202—3 perform image processing by a different thread from the thread of the SCUs 203—0 to 203—3.

Abstract: Direct current circuits always require a voltage source consisting of a positive voltage and a ground. To power a plurality of a direct current circuit nodes one must traditionally supply a power supply line and a ground line to each circuit node. To simplify wiring, a single conductor system of powering a plurality of circuit nodes is disclosed wherein each circuit node has only two external connections and the circuit nodes are coupled in series. Specifically, each individual circuit node has an integrated circuit and a capacitor. A power circuit within the integrated circuit then directs current from an input into the capacitor to create a local power supply and shunts current from the input to an output when not directing current into the capacitor.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: This disclosure provides systems, methods, and apparatus for calibrating and controlling the actuation of an analog interferometric modulator. In one aspect, an electrode of a movable layer of the analog interferometric modulator may include a part for receiving a drive voltage, and an electrically isolated part. A voltage may be sensed from the electrically isolated part, and used to determine the position of the movable layer and/or provide feedback to the drive voltage.

Abstract: Systems and techniques for processing sequences of video images involve receiving, on a computer, data corresponding to a sequence of video images detected by an image sensor. The received data is processed using a graphics processor to adjust one or more visual characteristics of the video images corresponding to the received data. The received data can include video data defining pixel values and ancillary data relating to settings on the image sensor. The video data can be processed in accordance with ancillary data to adjust the visual characteristics, which can include filtering the images, blending images, and/or other processing operations.

Abstract: A DGS (discrete graphics system) unit is disclosed. The DGS unit includes a system chassis configured to house a GPU, the GPU for executing 3-D graphics instructions, and a GPU mounting unit coupled to the system chassis and configured to receive the GPU. A serial bus connector is coupled to the chassis and is coupled to the GPU mounting unit, wherein the serial bus connector is configured removably connect the GPU to a computer system to enable the GPU to access the computer system via the serial bus connector and execute the 3-D graphics instructions for the computer system. A power supply coupled to the system chassis for supplying power to the GPU independent of the computer system.

Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresse of the slave's resources and forwards the accesse to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary method comprises: converting a plurality of descriptive elements into a plurality of operational codes which at least partially control at least one processor circuit; and using at least one processor circuit, performing one or more operations corresponding to an operational code to generate pixel data for the graphical image. Another exemplary method for processing a data file which has not been fully compiled to a machine code and comprising interpretable descriptions of the graphical image in a non-pixel-bitmap form, comprises: separating the data file from other data; parsing and converting the data file to a plurality of hardware-level operational codes and corresponding data; and performing a plurality of operations in response to at least some hardware-level operational codes to generate pixel data for the graphical image.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: A variable rendering system is described that automatically transitions between hardware-accelerated rendering and software rendering of application data based on system performance and without user interaction or noticeable impact on the user experience. When hardware-accelerated rendering is available, the system renders application data using hardware-accelerated rendering. If an event occurs that causes hardware-accelerated rendering to fail, then the system dynamically transitions from hardware-accelerated rendering to software-accelerated rendering. Periodically, the system attempts to transition back to hardware-accelerated rendering.

Abstract: A display controller which prevents the duplication of functional parts and processes and which displays dynamic content on a plurality of displays is provided. A terminal used as the controller has a shared dynamic image decoder which decodes the dynamic content. A first frame buffer used by the terminal stores the decoded dynamic content. A buffer transfer unit sends the dynamic content stored in the first frame buffer to a second frame buffer used by an external monitor. A terminal display displays the dynamic content stored in the first frame buffer on a display of the terminal. An external monitor interface displays the dynamic content stored in the second frame buffer on an external monitor.

Abstract: Synchronized access to a shared surface from multiple rendering contexts is provided. Only one rendering context is allowed to access a shared surface at a given time to read from and write to the surface. Other non-owning rendering contexts are prevented from accessing and rendering to the shared surface while the surface is currently owned by another rendering context. A non-owning rendering context makes an acquire call and waits for the surface to be released. When the currently owning rendering context finishes rendering to the shared surface, it release the surface. The rendering context that made the acquire call then acquires access and renders to the shared surface.

Abstract: An image display system synchronizes the display of images on a plurality of display devices. The method entails generating at a first computer system a first signal representing first image data to be displayed on a first display device, generating at a second computer system a second signal representing second image data to be displayed on a second display device, and a method for synchronizing the first and second image data. The synchronizing method includes using a phase-locked loop circuit having a digital rate controller. The digital rate controller allows programmable control of the speed of the phase-locked loop.

Abstract: A projection system includes: a screen having screen specific authentication information; and a projector having a function of acquiring the screen specific authentication information and, based on the acquired authentication information, carrying out an authentication process for setting the projector to a usable condition.

Abstract: Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems.

Abstract: Light Emitting Diodes (LEDs) are increasingly used in illumination applications. To control multiple Light Emitting Diodes (LEDs), or any other controllable light source, this document introduces a single-wire multiple-LED power and control system. Specifically, individually controlled LED units are arranged in a series configuration that is driven by a control unit located at the head of the series. Each of the individually controlled LED units may comprise more than one LED that is also individually controllable. The head-end control unit provides both electrical power and control signals down a single wire to drive all of the LED units in the series in a manner that allows each LED unit to be controlled individually or in assigned groups.

Abstract: An controlled LED lighting system that operates using a single conductor to power and control LED nodes is disclosed. The controlled LED lighting system modulates control data onto a nominally constant DC signal transmitted down a single conductor serial line. Nodes coupled the serial line draw power into a local capacitor and demodulate the data signal. Each node shunts the serial line when additional power is not required such that the data signal is received by every node on the serial line.

Abstract: Light Emitting Diodes (LEDs) are increasingly used in illumination applications. To control multiple Light Emitting Diodes (LEDs), or any other controllable light source, this document introduces a single-wire multiple-LED power and control system. Specifically, individually controlled LED units are arranged in a series configuration that is driven by a control unit located at the head of the series. Each of the individually controlled LED units may comprise more than one LED that is also individually controllable. The head-end control unit provides both electrical power and control signals down a single wire to drive all of the LED units in the series in a manner that allows each LED unit to be controlled individually or in assigned groups.

Abstract: One embodiment of the present invention sets forth a method for managing a power state of an audio device resident in a graphics processing unit. The method includes the steps of directing audio data originated from a client application via an audio path in an audio driver stack to the audio device, determining whether an active stream of audio data along the audio path is present in response to a notification of an attempt to shut down the graphics processing unit, and requesting a plug and play manager to disable the audio device, if no active stream of audio data is present along the audio path.

Abstract: Disclosed are an apparatus and a method for processing data, capable of controlling the use of a graphic controller based on data usage in a memory, a variation speed of a memory data value, and/or operating states/conditions of a system.

Abstract: Mechanisms allow for execution of unsigned managed code graphic resource call in a closed system when such unsigned content is executing on the system. For example, a managed code graphic resource device is used between an application running unsigned content and a supervisor mode graphic resource device. A managed mode graphics device validates graphic resource calls made by the application. A managed mode graphics device manages resource calls by differentiating between calls that may be made directly to the supervisor mode graphics device, calls that may be pipelined for later action, and calls that may be made to an intermediate device.

Abstract: Multiple Video Graphic Adapters (VGAs) are used to render video data to a common port. In one embodiment, each VGA will render an entire frame of video and provide it to the output port through a switch. The next adjacent frame will be calculated by a separate VGA and provided to an output port through the switch. A voltage adjustment is made to a digital-to-analog converter (DAC) of at least one of the VGAs in order to correlate the video-out voltages being provided by the VGAs. This correlation assures that the color being viewed on the screen is uniform regardless of which VGA is providing the signal. A dummy switch receives the video-output from each of the VGAs. When a VGA is not providing information to the output port, the dummy switch can be selected to provide the video-output of the selected VGA a resistance path which matches the resistance at the video port. This allows the video graphics controller to maintain a constant thermal state.

Abstract: A method of managing resources is provided. The method includes identifying a resource associated with a processor responsive to an impending transition, and copying the identified resource from a memory associated with the GPU or to the memory associated with the GPU.

Abstract: An interface apparatus and method are provided. The interface apparatus includes a level detecting unit detecting a level of an inputted control signal, a counter unit increasing or decreasing a count value according to the level detected in the level detecting unit, and a driving control unit outputting a driving control information mapped into a count value of the counter unit.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: In a data processing system for determining intersections between geometric objects, the work is split between a CPU and a stream processor. The intersection determination is controlled by the CPU. Data processing intensive parts of intersection algorithms, such as checking possible overlap of objects, checking overlap of normal fields of objects, approximating the extent of an object, approximating the normal fields of an object, or making conjectures for intersection topology and/or geometry between objects, are run on the stream processor. The results of the algorithmic parts run on the stream processor are used by the part of the algorithms run on the CPU. In cases where conjectures for the computational result are processed on the stream processor, the conjectures are checked for correctness by algorithms run on the CPU. If the correctness check shows that the result found is incomplete or wrong, additional parts of the algorithm are run on the CPU and possibly on the stream processor.

Abstract: One embodiment of the present invention sets forth a technique for dynamically switching between a power-saving integrated graphics processing unit (IGPU) and a higher-performance discrete graphics processing unit (DGPU). This technique uses a single graphics driver and a single digital-to-analog converter (DAC) and leverages the GPU switching capability of the operating system to ensure a seamless transition. When additional graphics performance is desired, the system enters a hybrid graphics mode. In this mode, the DGPU is powered-up, and the graphics driver maintains the current display, while the operating system switches applications running on the IGPU to the DGPU. While in the hybrid graphics mode, the DGPU performs the graphics processing, and the graphics driver transmits the rendered images from the DGPU to the IGPU local memory and, then, to the IGPU DAC.

Abstract: What is provided are a system and method for print/copy job environments utilizing a page description language (PDL). In one embodiment, an input PDL stream describing embedded objects in a job is received and parsed. Reusable document components (RDCs) are identified. A determination is made as to how many placements are in the PDL for each identified RDC. If no RDCs are placed more than once, caching is disabled. If it is not efficient to split the PDL stream into smaller tasks, page parallel rip (PPR) is disabled. The embedded objects are analyzed to determine a number of PPRs for the job based on system resources. A raster image processing (RIP) time is projected for each path in the job based on the determined number of placements and the determined number of PPRs. A job processing path is prescribed for the job based on the most efficient projected RIP time.

Abstract: A processing unit, method, and graphics processing system are provided for processing a plurality of frames of graphics data. For instance, the processing unit can include a first plurality of graphics processing units (GPUs), a second plurality of GPUs, and a plurality of compositors. The first plurality of GPUs can be configured to process a first frame of graphics data. Likewise, the second plurality of GPUs can be configured to process a second frame of graphics data. Further, each compositor in the plurality of compositors can be coupled to a respective GPU from the first and second pluralities of GPUs, where the plurality of compositors is configured to sequentially pass the first and second frames of graphics data to a display module.

Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.

Abstract: Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

Abstract: An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.

Abstract: A system and method for synchronizing digital media playback at multiple digital media playback devices interconnected on a network is provided. A digital media playback device comprising a processor, a synchronization component, a timekeeper component and a digital media source performs synchronization processes to arrange for other players to begin playback at a predetermined position and time in the digital media signal. Synchronization is accomplished by processes which approximate the arrival time of a packet containing audio and/or video digital content across the network and instruct the playback devices as to when playback is to begin, and at what point in the streaming media content signal to begin playback. One method uses a time-stamp packet on the network to synchronize all players. Other methods utilize reiterative processes to narrow approximations of packet arrival time at each playback device.

Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: Exemplary embodiments include an interception mechanism for rendering commands generated by interactive applications, and a feed-forward control mechanism based on the processing of the commands on a rendering engine, on a pre-filtering module, and on a visual encoder. Also a feed-back control mechanism from the encoder is described. The mechanism is compression-quality optimized subject to some constraints on streaming bandwidth and system delay. The mechanisms allow controllable levels of detail for different rendered objects, controllable post filtering of rendered images, and controllable compression quality of each object in compressed images. A mechanism for processing and streaming of multiple interactive applications in a centralized streaming application server is also described.

Abstract: A method for assisting in data calculation by using a display card: In the present method, input data stored in a system memory is transformed into texture data, which is then stored in a display memory of the display card. Then, a Graphic processing unit (GPU) of the display card is used for executing a texture calculation to the texture data, and a result of the texture calculation is stored in a display target of the display memory. Finally, the display target is outputted to the system memory as the output data. Accordingly, a part of calculation tasks of a central processing unit (CPU) can be given to the GPU of the display card when the CPU is in a high usage rate, so as to reduce a calculation burden of the CPU.