Abstract: The present invention relates to a method for processing data entities by a data processing system, wherein: a first and a second set of data entities are stored in a main memory and associated with a respective first and second set of points of a domain; the first set of data entities is loaded into a local storage; one or more first calculations are performed using the first set of data entities to generate first calculated data; the second set of data entities is determined according to at least some of the first calculated data; the determined second set of data entities is loaded into the local storage; and one or more second calculations are performed using the second set of data entities resulting in second calculated data.

Abstract: An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

Abstract: A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.

Abstract: A semiconductor device includes a graphics processor unit (GPU) configured to receive three-dimensional (3D) input data and a central processing unit (CPU) configured to receive the 3D input data and adjust a frequency and operating voltage of the GPU based on the 3D input data. The GPU performs image processing on the 3D input data based on the adjusted frequency and the operating voltage.

Abstract: An electrical device supporting switchable graphics function, electrically connected with a display unit, includes a first graphic chip, a second graphic chip, a peripheral, an Embedded Controller (EC) and a processing unit. Information of a present graphic chip is stored in an EC RAM of the EC, wherein the present graphic chip is one of the first graphic chip and the second graphic chip. A control unit of the EC obtains the information of the present graphic chip from the EC RAM and controls operation status of the peripheral according to the obtained information of the present graphic chip. The processing unit obtains the information of the present graphic chip from the EC RAM. The processing unit drives the present graphic chip to process an image signal and transmit the processed image signal to the display unit for display according to the obtained information of the present graphic chip.

Abstract: Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

Abstract: A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system as well as external peripheral devices. The system bridge controller is capable of performing format conversion between big-endian data and little-endian data. The system bridge controller includes a PCI bridge to interface with PCI devices, an I/O bus bridge to interface with I/O devices such as RAM, ROM, flash memory and 68000-compatible peripheral devices, and a CPU interface block to interface the CPU to video processing devices on the integrated circuit chip such as an MPEG video decoder.

Abstract: A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster pattern.

Abstract: The subject application is directed to a system and method for controlling a document processing device via a remote device interface. Display data is generated corresponding to the control of the document processing device, following which instructions are received from a user corresponding to one or more document processing operations. An image is then generated on a display integrated in the document processing device based on the display data and the received instructions. The display data is then communicated, via an established data connection, to an associated data processing device having both a user data input and a user display. Control instructions for the document processing device are then received from the associated data processing device so as to allow for user control of a document processing operation and a document processing operation is commenced based on instructions received from the data processing device.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: In one embodiment, an integrated circuit design tool is provided that includes a main window graphical user interface (GUI) and several tool GUIs. Cross probing of features from a source tool GUI to a target tool GUI occurs by the source tool GUI transmitting a probe request to the main window GUI; wherein the probe request identifies one or more cross-probed features for the target tool GUI. In response, the main window GUI commands a plug-in installation of the target tool GUI if the target tool GUI has not yet been instantiated. The main window GUI transmits a notification of the probe request to the target tool GUI. In response, the target tool GUI displays the cross-probed features.

Abstract: This disclosure describes techniques for reducing memory access bandwidth in a graphics processing system based on destination alpha values. The techniques may include retrieving a destination alpha value from a bin buffer, the destination alpha value being generated in response to processing a first pixel associated with a first primitive. The techniques may further include determining, based on the destination alpha value, whether to perform an action that causes one or more texture values for a second pixel to not be retrieved from a texture buffer. In some examples, the action may include discarding the second pixel from a pixel processing pipeline prior to the second pixel arriving at a texture mapping stage of the pixel processing pipeline. The second pixel may be associated with a second primitive different than the first primitive.

Abstract: According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer.

Abstract: A method of server site rendering 3D images on a server computer coupled to a client computer wherein the client computer instructs a server computer to load data for 3D rendering and sends a stream of rendering parameter sets to the server computer, each set of rendering parameters corresponding with an image to be rendered; next the render computer renders a stream of images corresponding to the stream of parameter sets and the stream of images is compressed with a video compression scheme and sent from the server computer to the client computer where the client computer decompresses the received compressed video stream and displays the result in a viewing port. The rendering and communication chain is subdivided in successive pipeline stages that work in parallel on successive rendered image information.

Abstract: A system on chip (SoC) includes a display controller configured to receive data of a current frame and to determine whether the data of the current frame has been updated from data of a previous frame, and a transmitter configured to output a panel self-refresh (PSR) inactive command and the data of the current frame when the display controller determines that the data of the current frame has been updated and to transmit a panel self-refresh (PSR) active command when the display controller determines that the data of the current frame has not been updated.

Abstract: A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.

Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Abstract: An image display system comprises a processor 10, a main memory 20 and a display panel 30, where the main memory 20 includes an uncompressed image area 24 for storing image data relating to an image and a compressed image area 26 for storing compressed image data. The processor is microcode-programmed, and executes, after changes have been made in the uncompressed image area, a special sequence of microcode words in a micro program memory 12 of the processor for compressing at least those parts of the uncompressed image area that are subject to changes. The microcode-compressed parts of the image data are then stored in the compressed image area 26 of the main memory. Compressed image data may then be fetched from the compressed image area 26 and decompressed for enabling generation of an appropriate image signal. The generated image signal can finally be applied to the display 30 for refreshing the image.

Abstract: A circuit including a first pin connection, a second pin connection, a first diode-switch arrangement and a second diode-switch arrangement. The first diode-switch arrangement is connected in series and configured to allow a current to pass from the second pin connection to the first pin connection. The second diode-switch arrangement is connected in series and configured to allow a current to pass from the first pin connection to the second pin connection. An energized state of the first and second diode-switch arrangements is determined according to a voltage detected on the first or second pin connection.

Abstract: A method and apparatus for an interface architecture for flexible and extensible media processing. In one embodiment, the apparatus may include on-chip interconnection logic, such as, for example, a crossbar. The apparatus, which in one embodiment is a chipset, may include at least one on-chip, functional unit, which is coupled to the interconnection logic. The at least one functional unit to operate as media processing stage of a media processing pipeline. In one embodiment, the apparatus may further include an on-chip controller to enable at least one selected off-chip functional unit to operate as a media processing stage of the media processing pipeline. Accordingly, in one embodiment, the chipset may provide an internal media processing pipeline, which may be expanded, reduced or modified by the inclusion of at least one off-chip media processing stage. Other embodiments are described and claimed.

Abstract: Direct current circuits always require a voltage source consisting of a positive voltage and a ground. To power a plurality of a direct current circuit nodes one must traditionally supply a power supply line and a ground line to each circuit node. To simplify wiring, a single conductor system of powering a plurality of circuit nodes is disclosed wherein each circuit node has only two external connections and the circuit nodes are coupled in series. Specifically, each individual circuit node has an integrated circuit and a capacitor. A power circuit within the integrated circuit then directs current from an input into the capacitor to create a local power supply and shunts current from the input to an output when not directing current into the capacitor.

Abstract: A microcontroller with an integrated special instruction processing unit and a programmable cycle state machine. The special instruction processing unit allows offloading of intensive processing of output data and the programmable cycle state machine minimizes the amount of customized, off chip circuitry necessary to connect the microcontroller to an external display.

Abstract: A display apparatus, an integrated circuit and method thereof are disclosed. The display apparatus includes a frame buffer, a controller circuit, and a display driver circuit. The frame buffer is configured to retain a plurality of image frames to be displayed. The controller circuit, coupled to the frame buffer, is configured to determine whether a change in the image frames has occurred and whether a refresh time is expired. The display driver circuit, operatively coupled to the frame buffer and adapted to couple to an active display device, is configured to receive the image frames to be displayed from the frame buffer and dynamically refreshing the active display device when the change is determined or when a refresh time is expired.

Abstract: A system for providing stitched video from a first camera and a second camera to an electronic display system includes a processing circuit configured to associate a view a first camera with an approximate location. The processing circuit is further configured to build relationship data between the first camera and a second camera using the approximate location. The processing circuit is further configured to transform video from the first camera relative to video from the second camera, the transformation based on the relationship data. The processing circuit is further configured to use the transformed video to cause the stitched video to be provided to the electronic display system.

Abstract: A data processing system for processing a video stream comprises memory array circuitry, memory access circuitry, and video processing circuitry. The memory array circuitry is characterized by a width and a height. The memory access circuitry is operative to cause, through a series of write operations, a series of two-dimensional data representations of different respective regions in a frame of the video stream to be stored in the memory array circuitry. The write operations occur such that only data missing from the memory array circuitry is written to the memory array circuitry during each write operation and such that the data is written modulo at least one of the width and the height of the memory array circuitry. Lastly, the video processing circuitry is operative to perform block matching on the video stream at least in part utilizing the series of two-dimensional data representations stored in the memory array circuitry.

Abstract: This invention relates to a system and method for customizing the appearance of a vehicle. Users can display customized designs, colors or promotional information on the vehicle for free or on a fee basis. The system also allows users to use a detection device to detect the colors or patterns of other objects and then display substantially the same color or pattern on the vehicle.

Abstract: In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for the graphics process in order to allocate performance resources to the graphics process and in some cases, between the graphics process and a central processing unit.

Abstract: A display device includes a panel including pixels defined by data lines and gate lines, a housing chassis covering a sidewall and an edge of the panel, a printed circuit board under the panel, the printed circuit board including circuit elements configured to generate at least one of a data signal, a gate signal, and a control signal, a chip on film connecting the printed circuit board to the panel, the chip on film between the housing chassis and the sidewall of the panel, a driver integrated circuit mounted on the chip on film and configured to respond to the control signal and drive at least one of the data signal and the gate signal applied to the data lines and the gate lines, and a connection unit attaching the chip on film to the housing chassis and dissipating heat generated by the driver integrated circuit to the housing chassis.

Abstract: In embodiments of the present invention improved capabilities are described for a passive radio frequency identification (RFID) tag, where the passive RFID tag contains an RF network node and communication facility. The RF network node includes an RF and analog block for receiving and transmitting an RFID reader signal, a data processing and controller block for digital information processing, a memory store, and a power management block for managing power requirements of the RF network node. The communication facility communicates at least in part with an external display facility. The distribution of power to the RF network node functional blocks is controlled using the power management block to select between an extended operational time and an increase in available functionality.

Abstract: Methods and apparatus for adjusting the operation of a display device so as to be at least within prescribed form factor or other constraints. In one embodiment of the invention, various operational parameters for a display element are adjusted based on considerations specific to high density form factor constraints. For example, in one such device, a Low Power DisplayPort (LPDP) device having a LPDP source and sink adjust the data rate of the visual data to minimize power consumption while still properly supporting display panel resolutions. In some embodiments, the LPDP source and sink may adjust the transceiver voltages to minimize power consumption. In an alternate embodiment, an LPDP device adjusts data rates to minimize the effects of platform noise. In another aspect of the invention, various display elements of a device coordinate quiescent (“quiet”) mode operation during periods of inactivity.

Abstract: A server is disclosed that includes an interface to a data communication network, a compiler library that stores a plurality of different compilers, and compiler selection logic responsive to data received at the interface and including logic. The compiler selection logic is configured to select one of the plurality of different compilers based on an evaluation of the received data. The selected compiler generates compiled output data and the compiled output data is communicated over the data communication network to a client.

Abstract: A method and a system for controlling a multimedia monitor are provided. The multimedia monitor has a central processing unit (CPU) and communicates with a computer system through a communication interface. The multimedia monitor displays images from the computer system when the multimedia monitor is in an external signal mode, and displays images generated by the CPU when the multimedia monitor is in a multimedia application mode. In the method, an input event is received by the computer system and an input command corresponding to the input event is transmitted to the multimedia monitor through the communication interface. After that, whether the input command belongs to a multimedia command set is determined by the multimedia monitor. If the input command belongs to the multimedia command set, an action corresponding to the input command under the multimedia application mode is executed by the multimedia monitor.

Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.

Abstract: Light Emitting Diodes (LEDs) are increasingly used in illumination applications. To control multiple Light Emitting Diodes (LEDs), or any other controllable light source, this document introduces a single-wire multiple-LED power and control system. Specifically, individually controlled LED units are arranged in a series configuration that is driven by a control unit located at the head of the series. Each of the individually controlled LED units may comprise more than one LED that is also individually controllable. The head-end control unit provides both electrical power and control signals down a single wire to drive all of the LED units in the series in a manner that allows each LED unit to be controlled individually or in assigned groups.

Abstract: An controlled LED lighting system that operates using a single conductor to power and control LED nodes is disclosed. The controlled LED lighting system modulates control data onto a nominally constant DC signal transmitted down a single conductor serial line. Nodes coupled the serial line draw power into a local capacitor and demodulate the data signal. Each node shunts the serial line when additional power is not required such that the data signal is received by every node on the serial line.

Abstract: The semiconductor IC device for display control disclosed herein aims to achieve a higher rate of memory access cycles without enhancing the current carrying capability of the memory device. The IC device is provided with a memory cell array capable to store display data, peripheral circuits to enable writing and reading of display data, and a control circuit which is able to control read and write operations from/to the memory cell array. The memory cell array comprises a plurality of memory blocks. The control circuit comprises a control logic which enables parallel processing of write operations in such a manner that, before completion of writing of data to one of the memory blocks, writing of data to another memory block is started. Write cycles are shortened by the parallel processing of write operations.

Abstract: One embodiment of the present invention sets forth a method for managing a power state of an audio device resident in a graphics processing unit. The method includes the steps of directing audio data originated from a client application via an audio path in an audio driver stack to the audio device, determining whether an active stream of audio data along the audio path is present in response to a notification of an attempt to shut down the graphics processing unit, and requesting a plug and play manager to disable the audio device, if no active stream of audio data is present along the audio path.

Abstract: Light Emitting Diodes (LEDs) are increasingly used in illumination applications. To control multiple Light Emitting Diodes (LEDs), or any other controllable light source, this document introduces a single-wire multiple-LED power and control system. Specifically, individually controlled LED units are arranged in a series configuration that is driven by a control unit located at the head of the series. Each of the individually controlled LED units may comprise more than one LED that is also individually controllable. The head-end control unit provides both electrical power and control signals down a single wire to drive all of the LED units in the series in a manner that allows each LED unit to be controlled individually or in assigned groups.

Abstract: One embodiment of the invention sets forth a mechanism for controlling the initialization order of an iGPU and a dGPU in a hybrid graphics processing environment to ensure that the iGPU is recognized by the operating system as the primary GPU. When the device initialization request associated with the dGPU is received, the interface module determines whether the iGPU has already been initialized. If the iGPU has already been initialized, then the interface module transmits the device initialization request to the dGPU driver for dGPU initialization. However, if the iGPU flag indicates that the iGPU has not yet been initialized, then the interface module terminates the device initialization request and transmits an initialization failure notification to the operating system. In such a manner, the dGPU is initialized only after the iGPU has previously been initialized, thereby ensuring that the iGPU is recognized by the operating system as the primary GPU.

Abstract: A gate driving circuit having improved driving capability and maintaining reliability even after a prolonged period of use includes a shift register having a plurality of stages cascaded to one another, each of the plurality of stages including a pull-up unit, a pull-down unit, a discharging unit, and a holding unit, wherein at least one of the discharging unit and the holding unit includes an amorphous silicon thin film transistor and a polysilicon thin film transistor connected in parallel to each other.

Abstract: A display device with embedded networking capability is described herein. The display device uses at least a portion of a memory of the display device, the memory of which is used for storing video/image data in the display, to store networking codes for establishing and maintaining the network connection.

Abstract: An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter (e.g an opcode of a command) and its associated operands in one or more input registers connected to the addressable register array. A single instance of a command accesses the at least one register of the array. Based on the input command parameter, the command for all of the address operands: reads a datum of the data previously stored in at least one register, updates the datum thereby producing an updated datum, and writes the updated datum into at least one register. The command has multiple address operands referencing the one or more registers and supports two or more of the address operands being identical. The device includes logic circuitry which provides a logical output signal to the processing circuitry indicating which, if any, of the address operands are identical.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract: A system for providing stitched video from a first camera and a second camera to an electronic display system includes a processing circuit configured to associate a view a first camera with an approximate location. The processing circuit is further configured to build relationship data between the first camera and a second camera using the approximate location. The processing circuit is further configured to transform video from the first camera relative to video from the second camera, the transformation based on the relationship data. The processing circuit is further configured to use the transformed video to cause the stitched video to be provided to the electronic display system.

Abstract: Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.