Abstract: One embodiment facilitates a user-space storage I/O stack. During operation, the system generates, by a file system in the user-space, a logical block address associated with an I/O request which indicates data to be read or written. The system generates, by a flash translation layer module in the user-space, a physical block address corresponding to the logical block address, wherein the flash translation layer module is located between the file system and a block device driver in the user-space. The system estimates a latency associated with executing the I/O request. In response to determining that the estimated latency is greater than or equal to a predetermined threshold, and that the I/O request is a read request, the system reads the requested data from a location other than the physical block address.

Abstract: Techniques are disclosed relating to managing dependencies in a compute control stream that specifies operations to be performed on a programmable shader (e.g., of a graphics unit). In some embodiments, the compute control stream includes commands and kernels. In some embodiments, dependency circuitry is configured to maintain dependencies such that younger kernels are allowed to execute ahead of a type of cache-related command (e.g., a command that signals a cache flush and/or invalidate). Disclosed circuitry may include separate buffers for commands and kernels, command dependency circuitry, and kernel dependency circuitry. In various embodiments, the disclosed architecture may improve performance in a highly scalable manner.

Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.

Abstract: Methods, apparatus, and articles of manufacture to provide extended graphics processing capabilities are disclosed. A disclosed example method involves sending a display panel parameter to a shared library module. The display panel parameter is sent by a programmable driver interface in communication between the shared library module and a graphics hardware device driver. The shared library module includes a first graphics processing capability. The graphics hardware device driver includes a second graphics processing capability different from the first graphics processing capability. The example method also involves performing a render operation via the programmable driver interface on a frame buffer based on the first graphics processing capability. The first graphics processing capability is received at the programmable driver interface from the shared library module based on the display panel parameter. The frame buffer is output to a display.

Abstract: An electronic device includes a processor configured to generate a slice update map indicating a location of at least one updated slice having a data change in frame data including a plurality of slices; and a display controller configured to extract frame data of the at least one updated slice from a memory based on the slice update map and transfer the frame data to a display driver.

Abstract: This disclosure pertains to the operation of graphics systems and to a variety of architectures for design and/or operation of a graphics system spanning from the output of an application program and extending to the presentation of visual content in the form of pixels or otherwise. In general, many embodiments of the invention contemplate a high level graphics framework to receive graphic requests from an application. The graphics request is analyzed by the high-level framework and sorted into groups of command statements for execution. The command statements are sorted to cause the most efficient processing by the underlying hardware and the groups are submitted separately to a GPU using a low-level standard library that facilitates close control of the hardware functionality.

Abstract: One or more copy commands are scheduled for locating one or more pages of data in a local memory of a graphics processing unit (GPU) for more efficient access to the pages of data during rendering. A first processing unit that is coupled to a first GPU receives a notification that an access request count has reached a specified threshold. The first processing unit schedules a copy command to copy the first page of data to a first memory circuit of the first GPU from a second memory circuit of the second GPU. The copy command is included within a GPU command stream.

Abstract: A cache memory may be configured to store a plurality of lines, where each line includes data and metadata. A circuit may be configured to determine a respective number of edges associated with each vertex of a plurality of vertices included in a graph data structure, and sort the graph data structure using the respective number of edges. The circuit may be further configured to determine a reuse value for a particular vertex of the plurality of vertices using a respective address associated with the particular vertex in the sorted graph, and store data and metadata associated with the particular vertex in a particular line of the plurality of lines in the cache memory.

Abstract: A GPU simulation method. An instruction sequence of a client GPU is intercepted in a kernel state simulator based on system virtualization and GPU using principle, and a mechanism is selected according to user configuration to accomplish simulation of the client GPU. In first mechanism, instruction translation is accomplished on low-level semantics based on a binary translation technology, and instructions are executed on a host GPU; in second mechanism, instruction conversion is accomplished using an existing GPU software stack, and instructions are executed on host GPU. The method provides an efficient simulated GPU for a virtual machine based on a host machine physical GPU, and solves the problem of slow GPU simulation. Based on a system virtualization technology and by virtue of a convenient condition provided by an existing GPU software stack, the GPU simulation speed is improved, and the implementation difficulty and complexity of the method are effectively controlled.

Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

Abstract: Aspects of the present disclosure describe methods and apparatuses for improving efficiency in emulation. An emulated CPU receives inputs and generates a first set of frames. The frames are stored in a buffer on the emulator. Once all of the frames in the first set of frames have been produced, the contents of the buffer may be delivered to an emulated GPU. Each frame is then rendered by the emulated GPU. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: The invention notably relates to a computer-implemented method for displaying a 3D assembly of modeled objects. The method comprises streaming from a first computer to a second computer at least one raster image of a first 3D modeled object, and rendering on the second computer the 3D assembly of modeled objects by merging a second 3D modeled object with the streamed at least one raster image.

Abstract: The present invention provides a method, an apparatus and a storage medium for processing an HTML5 Canvas application, said method comprising: in the first thread: CPU executes codes of a graphic drawing application to draw each frame of canvas, when it is detected that rendering is needed, all canvas drawing commands of said frame of canvas are cached without executing the corresponding rendering, and when the drawing of said frame of canvas is completed, all the cached canvas drawing commands of said frame of canvas are sent to a second thread; in the second thread, CPU calls GPU to execute all canvas drawing commands of each frame of canvas sent by the first thread, and GPU performs rendering on each frame of canvas according to the canvas drawing commands. The present invention realizes concurrent thread processing by means of caching drawing commands such that JavaScript codes and rendering can be executed simultaneously.

Abstract: A method of graphics processing comprising receiving, at a graphics processing unit (GPU), a command stream, the command stream including one or more commands to be performed by the GPU and at least one command stream hint, the at least one command stream hint providing a characterization of a workload of the command stream, performing, by the GPU, a power management process based on the at least one command stream hint prior to executing the command stream, and executing, by the GPU, the command stream.

Abstract: Apparatuses, methods and storage medium associated with live migration of virtual machines (VMs) from/to host computers with graphics virtualization are disclosed herein. In embodiments, an apparatus may include a virtual machine monitor (VMM) having a memory manager to manage accesses of system memory of the apparatus, including tracking of modified memory pages of the system memory. Additionally, the VMM may include a graphics command parser to analyze graphics commands issued to a graphics processor (GPU) of the apparatus to detect writes to the system memory caused by the graphics commands, and augment the tracking of modified memory pages. Further, the VMM may include a live migration function to live migrate a VM to another apparatus, including provision of current memory content of the VM, utilizing modified memory pages tracked by the memory manager, as augmented by the graphics command parser.

Abstract: Techniques are disclosed relating to scheduling graphics instructions for execution on different types of execution units based on characteristics of decoded and cached graphics instruction. In some embodiments, a graphics unit includes multiple different types of execution units that are configured to execute different types of instructions (e.g., different units for datapath, sample, load/store, etc.). In some embodiments, the graphics unit stores decoded instructions in an instruction cache in at least one cache level, along with information specifying characteristics of the instructions. The characteristics may be stored at clause granularity and may indicate the type of instructions in each clause (e.g., corresponding to which type of execution unit is configured to execute the instructions).

Abstract: An embodiment of graphics apparatus may include a coarse depth tester to perform a coarse depth test on a block of pixels, and a stencil tester to perform a stencil test on the block of pixels. The stencil tester may be further configured to perform the stencil test in parallel with the coarse depth test. Other embodiments are disclosed and claimed.

Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.

Abstract: Implementations disclose methods and systems for rendering, by a browser, a content item projected on a mesh. A method includes providing, by a browser executing on a user device, an application programming interface (API) to communicate with a web application that includes a user interface to present a content item on the user device; receiving, by the browser from the web application via the API, an instruction to project the content item on a mesh, where the instruction identifies the content item and the mesh; rendering, by the browser and without involvement of the web application, a first frame of the content item projected on the mesh in a first orientation; and causing, by the browser, the rendered first frame to be displayed on the user device.

Abstract: According to one embodiment of the present disclosure, a computing system is provided, including a graphical processing unit (GPU) and a processor. The processor may be configured to execute a run-time executable cross-compiler to receive a GPU-executed program of a plurality of GPU-executed programs. The processor may be further configured to receive summary data associated with the GPU-executed program. The summary data may include a sequence in which the plurality of GPU-executed programs are configured to be executed. Based at least in part on the GPU-executed program and the summary data, the processor may be further configured to generate a translated GPU-executed program.

Abstract: A mechanism is described for facilitating configuration of computing engines based on runtime workload measurements at computing devices. A method of embodiments, as described herein, includes detecting a work unit corresponding to a workload, and collecting metrics relating to the work unit, where the metrics to indicate one or more characteristics of the work unit. The method may further include evaluating the one or more characteristics based on one or more configuration parameters relating to computing resources, and generating, based on evaluating of the one or more characteristics, a configuration plan specific to the work unit and applicable to one or more subsequent work units that are similar to the work unit. The method may further include applying and executing the configuration plan at a computing device upon execution of the one or more subsequent work units.

Abstract: The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.

Abstract: A device for processing data includes a processing unit configured to predict an execution time of a compute kernel on a secondary processing unit and, based on the predicted execution time, make a power management decision for the secondary processing unit.

Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

Abstract: The present invention relates to a computer-implemented method for handling a set of data containers of a file structure, which method is performed by one or more processors of a computing device. The method comprises determining a first set of coordinates on a digital boundary for each data container, and storing the first set of coordinates associated with each data container in a memory. Furthermore, each data container is arranged in a parent data container, and each first set of coordinates associated with a data container is representative of a default position of that data container on the digital boundary. The present invention also relates to a computing device and to a computer-readable medium.

Abstract: A computing device for just-in-time cross-compiling compiled binaries of application programs that utilize graphics processing unit (GPU) executed programs configured to be executed on a first GPU having a first application binary interface (ABI) including a second GPU having a second ABI different from the first ABI of the first GPU, and a processor configured to execute an application program that utilizes a plurality of GPU-executed programs configured to be executed for the first ABI of the first GPU, execute a run-time executable cross-compiler configured to, while the application program is being executed, emulate the first ABI using hardware resources of the second GPU by translating between the first ABI and the second ABI, and execute the plurality of GPU-executed programs on the second GPU with the emulated first ABI, and pass output of the plurality of GPU-executed programs for the emulated first ABI through the second ABI.

Abstract: Power management techniques include a graphics processing unit (GPU) in which the GPU determines whether it is operating outside an operational limit and, when the GPU is operating outside the operational limit, the GPU alters performance of an operation to be performed texture processor within the GPU to reduce complexity of the operation. Otherwise, the GPU may perform the texture processing operation at its default complexity. These techniques provide a degree of power control not available in other techniques.

Abstract: A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU (Graphics Processing Unit). The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream. Video frames provided by the video server optionally include overlays added to the output of the GPU. These overlays can include voice data received from another game player. These overlays may be used to prevent presentation of non-allowed input controls.

Abstract: Systems and methods for reducing the power consumption of an Information Handling System (IHS). In some embodiments, an IHS may be configured to: in response to a request to operate in static display mode: (a) render static content on a display, (b) allow the processor to enter standby by notifying an OS that the display is off while keeping the display on, and (c) maintain the display refreshed with the static content; while in static mode and in response to a command that requires updating the static content, wake up the processor and generate updated static content using the processor; and after generating the updated static content: render the updated static content on the display while the processor is awake, allow the processor to re-enter standby by notifying the OS that the display is off while keeping the display on, and maintain the display refreshed with the updated static content.

Abstract: Technologies for web-based game execution include a computing device with a web rendering engine and a native game engine library. The web rendering engine establishes a scripting environment that issues calls to a game engine interface established by the web rendering engine. The scripting environment may be a JavaScript engine. In response to calls to the game engine interface, the game engine interface issues calls to the native game engine library. The native game engine library issues native graphics commands to a graphics bridge of the computing device. The native graphics commands may be OpenGL calls. The graphics bridge translates the native graphics commands to a web graphics context, which renders graphical game content to a web content element of the web rendering engine. The web graphics context may be a WebGL context, and the web content element may be a canvas element. Other embodiments are described and claimed.

Abstract: A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments. The graphics processing system also comprises a cache system for storing graphics data for primitive fragments, the cache system including multiple cache subsystems. Each of the cache subsystems is coupled to a respective set of one or more processing engines. The graphics processing system also comprises a tile allocation unit which operates in one or more allocation modes to allocate tiles to processing engines. The allocation mode(s) include a spatial allocation mode in which groups of spatially adjacent tiles are allocated to the processing engines according to a spatial allocation scheme, which ensures that each of the groups of spatially adjacent tiles is allocated to a set of processing engines which are coupled to the same cache subsystem.

Abstract: A graphics processing unit (GPU) may dispatch a first set of commands for execution on one or more processing units of the GPU. The GPU may receive notification from a host device indicating that a second set of commands are ready to execute on the GPU. In response, the GPU may issue a first preemption command at a first preemption granularity to the one or more processing units. In response to the GPU failing to preempt execution of the first set of commands within an elapsed time period after issuing the first preemption command, the GPU may issue a second preemption command at a second preemption granularity to the one or more processing units, where the second preemption granularity is finer-grained than the first preemption granularity.

Abstract: A method of displaying a network graph with a computing system includes accessing data defining a network and including a plurality of vertices and a plurality of edges. If a number of vertices included in the network graph is below a first threshold, the network graph is locally rendering with a scalable vector graphics rendering engine of the computing system. If a number of vertices included in the network graph is between the first threshold and a second, higher, threshold, the network graph is locally rendered with a raster rendering engine of the computing system. If a number of vertices included in the network graph is above the second threshold, a remotely-rendered network graph rendered by a remote rendering engine is received at the computing system. The method further includes displaying the rendered network graph via a web browser of the computing system.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing latency in transmitting and presenting map user interfaces. In one aspect, a method includes receiving, from a client device, a request for presentation of an interactive map user interface that depicts (i) a region and (ii) data related to an account for sub-regions of the region. One or more servers render a map of the region. The server(s) generate an image file representing an image of the rendered map. A different visual characteristic is assigned to each different sub-region. The server(s) configure a user interface of the client device to present (i) the image with each of the different sub-regions being presented according to the different visual characteristics and (ii) account data related to a sub-region when the client device detects a user interaction with the sub-region.

Abstract: A processor includes a scheduler that governs which of a plurality of pending graphics contexts is selected for execution at a graphics pipeline of the processor. The processor also includes a plurality of flip queues storing data ready to be rendered at a display device. The executing graphics context can issue a flip request to change data at stored at one of the flip queues. In response to determining that the flip request targets a flip queue that is being used for rendering at the display device, the scheduler executes a context switch to schedule a different graphics context for execution at the graphics pipeline.

Abstract: An apparatus and method are described for cloud-based graphics updates. For example, one embodiment of an apparatus comprises a system optimization agent to detect a graphics application installed on the apparatus, the system optimization agent to responsively transmit, over a network, information related to the graphics application including a new graphics application or a new version of an existing graphics application. The apparatus may further comprise the system optimization agent to receive, over the network, optimized program code comprising one or more optimizations to specified portions of a graphics driver, where the one or more optimizations relate to the graphics application.

Abstract: A processing apparatus is described. The apparatus includes a central processing unit (CPU), a graphics processing unit (GPU) and data sharing logic to perform static physical data sharing between the CPU and the GPU by changing code written for the GPU to operate with CPU variables.

Abstract: A cross-platform rendering engine. The cross-platform rendering engine serves as an intermediary between the application and the operating system for displaying application content on the screen allowing software developers to write platform-agnostic application code. The application sends content to the cross-platform rendering engine in the form of resource-efficient content descriptions describing the content to be displayed. In turn, cross-platform rendering engine stores the content descriptions and provides rasterized images generated from the content descriptions to the compositor as needed. In the event that a content description corresponding to the texture needed by the compositor is not available, the cross-platform rendering engine pulls the content description from the application.

Abstract: A method for the quasi-parallel execution of threads, including: within a time slice, time-limited resources, particularly a computing time, are allotted to the threads by a preemptive first scheduler on the basis of a priority of the threads, and the first scheduler is combined with further schedulers.

Abstract: A non-transitory recording medium storing a computer readable program causes a computer to execute: a) analyzing unconverted first page description language data to determine whether a repetitive pattern image portion is included in the first page description language data; b) separating the repetitive pattern image portion from the first page description language data when it is determined that the repetitive pattern image portion is included in the first page description language data; c) generating first partial data in a second page description language; d) generating second partial data in the second page description language based on a portion other than the repetitive pattern image portion of the first page description language data; and e) generating converted data that relates to the first page description language data and is second page description language data based on the first partial data and the second partial data.

Abstract: A system and method for enabling graphic-based interoperability with a run-time application is configured to, during a design-time (DT) mode: receive a DT application image; identify DT visual objects within the DT application image; generate DT bounding shape objects in which each DT bounding shape object bounds one or more DT visual objects identified within the DT application image; define bounding shape properties for the DT bounding shape objects; and store as a scene, data relating to the DT application image, the DT visual objects, the DT bounding shape objects, and the bounding shape properties, for later recall; and during a run-time (RT) mode: recall the scene stored during the DT mode; capture a RT application image; identify RT visual objects within the RT application image based on the scene; generate RT bounding shape objects, and apply the bounding shape properties to the generated RT bounding shape objects.

Abstract: A system and method for processing a plurality of channels, for example audio channels, in parallel is provided. For example, a plurality of telephony channels are processed in order to detect and respond to call progress tones. The channels may be processed according to a common transform algorithm. Advantageously, a massively parallel architecture is employed, in which operations on many channels are synchronized, to achieve a high efficiency parallel processing environment. The parallel processor may be situated on a data bus, separate from a main general purpose processor, or integrated with the processor in a common board or integrated device. All, or a portion of a speech processing algorithm may also be performed in a massively parallel manner.

Abstract: A method of generating a ray tracing acceleration structure includes transformatively mapping locations of object primitives in a three dimensional first space into Morton codes indicating respective locations of the primitives along a meandering linear path through the first space; determining a Morton distance indicating a difference between a first Morton code corresponding with a first primitive and a second Morton code corresponding with a second primitive; generating an acceleration structure to include nodes representing portions of the first space and adaptively adjusting a reference level of the acceleration structure, based on the Morton distance between primitives; and dividing the first space using a first division method when a level of a first node of the acceleration structure which corresponds to the first space is lower than the reference level, and dividing the first space using a second division method when the level of the first node exceeds the reference level.

Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.

Abstract: Concepts and technologies are described herein for presenting data driven forms. In accordance with the concepts and technologies disclosed herein, a user device obtains a resource referencing or presenting data driven forms and obtains data displayed or used by the resource. The user device stores the data in a cache accessible by the user device. The user device can render multiple views containing data from the cache. The user device can display one of the views and hide the other views from display. If the user device detects input for viewing other views, the user device can present one of the previously hidden views. The user device also can manage the cache and download additional data, if the cache empties or is not full.

Abstract: Methods, systems, and computer program products are included for providing a virtual machine guest with access to a host device. A method includes providing a hypervisor with access to an enhanced allocation capability entry of a host device. The host device performs input and output operations via a range of addresses that are provided by the enhanced allocation capability entry. The hypervisor runs a virtual machine and configures the virtual machine to include a virtual device corresponding to the host device. The virtual device includes the range of addresses in an enhanced allocation capability entry. The hypervisor modifies a context, such as a bit map, corresponding to the virtual machine to provide guests of the virtual machine with access to perform I/O operations corresponding to the host device using the range of addresses.

Abstract: A wearable computing device includes a head-mounted display (HMD) that generates a virtual reality environment. Through the generation and tracking of positional data, a the virtual environment may be interrupted or paused. Upon pausing the environment, a user may access a number of ancillary menus and controls not otherwise available during normal operation of the virtual environment.

Abstract: An interface mitigates the need for inter-application locks in a storage system with a HPP. The interface includes a virtual device driver that can be accessed by both emulation threads and guest OS Container threads and separate memory pages that are pinned for use as buffer spaces. The pinned buffer memory pages are shared by CPU cores and by individual virtual HPP client drivers. The interface enables virtualization of GPUs and HPPs.

Abstract: A method of processing commands is provided. The method includes holding commands in queues and executing the commands in an order based on their respective priority. Commands having the same priority are held in the same queue.