Abstract: A memory apparatus may include a tile generator configured to generate a plurality of tiles by dividing a plurality of pixels constituting input data based on a predetermined pixel unit, and a tile storage configured to store the plurality of tiles by sequentially enumerating luminance information and chrominance information about pixels included in the plurality of tiles.

Abstract: A display apparatus includes a display panel, a plurality of gate lines driving circuit parts, a plurality of data lines driving circuit parts and a timing control part. The display panel includes a plurality of gate lines and a plurality of data lines. The gate lines driving circuit parts output gate signals to the gate lines. The data lines driving circuit parts output data signals to the data lines. The timing control part applies a dummy gate signal to at least one dummy gate line, controls a latch sequence of image data and an output sequence of the gate lines driving circuit parts in a reverse sequence, in response to an inverted-mounting mode selection signal for displaying an inverted mount image to the display panel. Because signal lines can be shortened, heat generated by the display apparatus may be decreased and image quality of the display apparatus may be improved.

Abstract: An integrated circuit device includes: a first pad to an ith pad connected to a first memory pad to an ith memory pad of a memory stacked in the integrated circuit device; a jth pad to a kth pad connected to a jth memory pad to a kth (1<i<j<k) memory pad of the memory; and at least one pad arranged between the ith pad and the jth pad, wherein the at least one pad is not connected to a memory pad of the memory and serves as a pad for input or output a signal between an external device and the integrated circuit device.

Abstract: An information processing apparatus includes: memory configured to store local data associated with content and to store network data associated with the content, wherein the local data comprises real data associated with the content, and wherein the network data comprises metadata associated with the content; and a display control unit configured to control display of the local data and the network data on a display unit based on time information associated with the network data and the local data.

Abstract: In contrast to a conventional computing system in which the graphics processor (graphics processing unit or GPU) is treated as a slave to one or several CPUs, systems and methods are provided that allow the GPU to be treated as a central processing unit (CPU) from the perspective of the operating system. The GPU can access a memory space shared by other CPUs in the computing system. Caches utilized by the GPU may be coherent with caches utilized by other CPUs in the computing system. The GPU may share execution of general-purpose computations with other CPUs in the computing system.

Abstract: In order to reduce power consumption of a display device when a still picture is to be displayed, a display area of the device is subdivided into a plurality of Still Picture Refresh Groups (SPRGoP's), with each SPRGoP consisting of n pixels. All n of the pixels are charged in every one of sequential frames when a motion picture mode is in effect. Less than all of the n pixels of each SPRGoP are refreshed in each frame of an N-frame refresh cycle when a still picture mode is in effect. Different schemes for cycling through the n pixels of each SPRGoP are disclosed.

Abstract: Control of platform control of platform power consumption using selective updating of a display image. An embodiment of an apparatus includes a display controller to transfer pixel data from a frame buffer to a video display and a detection element to track updates to the frame buffer, the detection element to identify a portion of the pixel data that has been changed from a previous image, where the display controller is to provide the video display with the identified portion of the pixel data.

Abstract: In an embodiment, a method in a device of controlling a display is provided. The method includes transmitting a heartbeat signal in a self-refresh state. The heartbeat signal is configured to be used by a display to remain in sync with the device while the device is in the self-refresh state.

Abstract: Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.

Abstract: Aspects of the invention relate to a controllable display apparatus and applications thereof. The controllable display storage includes a storage having a storage space therein and an opening exposing the storage space to an outer environment, a transparent display panel disposed at the opening, configured to display information thereon, a control device disposed between a part of the storage space and the transparent display panel, where at least a part of the control device is switchable between a transparent mode and an opaque mode, such that the information displayed on the transparent display panel is viewable when the control device is in the opaque mode, and an item displayed in the storage space is viewable through the transparent display panel when the control device is in the transparent mode, and at least one light source disposed in the storage space to provide light to the storage space.

Abstract: Modification messages may be filtered to reduce the load on a message channel between a render cache and a frame buffer compression. A group of cache lines may be checked to see whether both a subspan request hits an unlit bit and a modify message was already sent. If so, the modification message may be filtered.

Abstract: There is provided a method and apparatus for managing memory in a system for generating 3-dimensional computer images. The image is subdivided into a plurality of rectangular areas. A memory is provided and a page of the memory is allocated for storing object data for objects in the image. Object data for objects in the image are then written to the allocated page of memory. Finally, a bit mask for the allocated page of memory is compiled, the bit mask indicating the rectangular areas having object data stored in the allocated page of memory. A rectangular area of the image can then be rendered by deriving data for display from the object data stored in the memory, for objects in that rectangular area. Once the rectangular area has been rendered, the bit mask for each page of memory which stored, before the step of rendering, object data for that rectangular area, is updated so that the bit mask no longer indicates that rectangular area.

Abstract: A withdrawer withdrawing an image presenting the memory contents of a volatile storage to a nonvolatile storage at the time of power shutdown; a withdrawal controller controlling the withdrawer to withdraw an image containing only data regarding the programs fulfilling a given withdrawal condition among multiple running programs to the nonvolatile storage if the image contains data regarding the multiple programs; and a restorer restoring the operation state of the device to the operation state at the time of last power shutdown based on the image at the time of resupply of power if the image withdrawn by the withdrawer at the time of last power shutdown is present in the nonvolatile storage.

Abstract: An image displaying device with an image cache data storage unit, including: an image cache identifier generating unit that obtains a hash value of a fixed length from sampling data of original image data and generates an image cache identifier unique to said original image data based on the hash value of a fixed length; an image cache searching unit that checks whether image cache data to which the generated image cache identifier is added is stored in said image cache memory or not; and an image cache generating unit that, when the image cache data has been not stored in said image cache memory, generates image cache data by adding the image cache identifier generated by said image cache identifier generating unit to the original image data and stores the image cache data in said image cache memory.

Abstract: Methods and systems relating to providing constants are provided. In an embodiment, a method of providing constants in a processing device includes copying a constant of a first constant buffer to a second constant buffer, the first and second constant buffers being included in a ring of constant buffers and a size of the ring being one greater than a number of processes that the processing device can process concurrently, updating a value of the constant in the second buffer, and binding a command to be executed on the processing device to the second constant buffer.

Abstract: A portable electronic device is provided. The portable electronic device includes a processor for providing encoding data and an LCD module coupled to the processor. The processor includes an encoder for encoding a frame data to generate the encoding data. The LCD module includes a driver and an LCD coupled to the driver. The driver includes a decoder for decoding the encoding data to obtain an image data. The LCD displays the image data.

Abstract: Methods for managing a framebuffer in a single memory pool comprising frame buffer memory and display list memory on printing devices are presented. In some embodiments, a method for managing at least one pixmap corresponding to an image using equal sized blocks allocated to the pixmap from a memory pool comprises: receiving a request for at least one scanline in the image; securing a pointer to at least one block from the memory pool in response to the request for the at least one scanline, if memory blocks are available in the memory pool; and applying at least one of a plurality of memory freeing strategies, if there are no memory blocks available in the memory pool.

Abstract: A method and apparatus for sorting data into spatial bins or buckets using a graphics processing unit (GPU). The method takes unsorted point data as input and scatters the points, in sorted order, into a set of bins. This key operation enables construction of a spatial data structure that is useful for applications such as particle simulation or collision detection. The disclosed method achieves better performance scaling than previous methods by exploiting geometry shaders to progressively trim the size of a working set. The method also leverages predicated rendering functionality to allow early termination without CPU/GPU synchronization. Furthermore, unlike previous techniques, the method can guarantee sorted output without requiring sorted input. This allows the method to be used to implement a form of bucket sort using the GPU.

Abstract: A method and apparatus record a first object identifier in a memory associated with an object and record a second object identifier in the memory in place of the first object identifier.

Abstract: A screen time control device includes a source interface for receiving a video signal, a processor connected to the video source interface for overlaying the video signal with a translucent signal to produce an overlaid video signal, and a device interface connected to the processor for receiving the overlaid video signal and providing the overlaid video signal to the display device. The processor substitutes the translucent signal in the overlaid video signal with a parental signal, where the parental signal can be a substantially opaque overlay signal that masks an image on the screen of the display device to prohibit viewing of the screen, a textual message, or a combination of both.

Abstract: Circuit and methods provide for adjustable power consumption using a plurality of memory controllers. In one example, a first memory controller has a first power consumption level. A second memory controller has a second power consumption level that differs from the first power consumption level. Memory controller bypass logic is connected to the first and second memory controllers and selects for a memory client at least one of the first and second memory controllers in response to a change in a power conservation condition.

Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.

Abstract: This disclosure provides systems, methods and apparatus for a thin film transistor (TFT) device on a substrate. In one aspect, the TFT device includes a gate electrode, an oxide semiconductor layer, and a gate insulator between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes at least two metal oxides, with the two metal oxides having a varying concentration relative to one another between a lower surface and an upper surface of the oxide semiconductor layer. The TFT device also includes a source metal adjacent to a portion of the oxide semiconductor layer and a drain metal adjacent to another portion of the oxide semiconductor layer. The composition of the oxide semiconductor layer can be precisely controlled by a sequential deposition technique using atomic layer deposition (ALD).

Abstract: This disclosure provides systems, methods and apparatus for reducing image artifacts that arise when a display is exposed to sunlight over time. Various implementations disclosed herein can be implemented to prevent charge injection from inducing a negative offset voltage shift for display elements in the display. In one aspect, a buffer layer is applied to block electrons from being photoelectrically ejected from a movable reflective layer of a display element and into a stationary optical stack of the display element.

Abstract: An image processing apparatus includes an image-processing designating unit that allows a user to designate predetermined image processing to be applied to image data for generating a preview image that represents a state of an output image before image output; a preview-image generating unit that generates a preview image in accordance with the designated image processing; a preview-image display unit that displays the preview image generated by the preview-image generating unit; and a display-mode switching control unit that, when the preview image is displayed, switches to a display mode with an enhanced viewability relative to a power-saving display state in accordance with a content of the designated image processing.

Abstract: Embodiments of partial update for a wireless display device include providing an update information message identifying a location of the partial update and the changed image data. A display source identifies changes in image data stored in a frame buffer, generates an update information message to identify the location of the changed image data and to provide the changed image data. A display sink receives the update information message and merges the changed image data with image data stored in a local frame buffer.

Abstract: Data transfer techniques include transferring display surface data from a memory subsystem into a stutter buffer at a first rate until the stutter buffer is substantially full. The memory interface and/or memory of the memory subsystem may then be placed into a suspend state until the stutter buffer is substantially empty. The display surface data is transferred from the stutter buffer to display logic, at a second rate even when the memory subsystem is in a suspend state. The second rate, which is typically the rendering rate of the display, is substantially slower than the rate at which data is transferred into the stutter buffer.

Abstract: A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.

Abstract: A graphics processing unit 2 includes a texture pipeline 6 which performs filter operations upon texture values. If the texture values are integer texture values, then they may be processed by the texture pipeline in a variable order corresponding to the order in which they are retrieved from a memory 4. If the texture values are floating point texture values, then they are processed in a fixed order in order to ensure result invariants as the filter operation is non-associative for floating point values. The filter operation is not commenced until all of the floating point texture values have been retrieved from the memory 4 and other available for processing.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: Methods and apparatuses are described for application broadcasting. For one embodiment, pixel data being broadcast from a moderator to one or more participants is divided into tiles. Display data is generated for each tile. Each display data segment (segment) contains the pixel data for the tile, and also contains a tile identifier. The segments are periodically evaluated. If the pixel data has changed, the segment is replaced with the most recent segment corresponding to that tile. A time indicator is also included within each segment for each tile indicating the time at which the segment was updated. A participant DPS requests data from the server and provides the time indicator for the last segment it received. The server then transmits the current segment for each tile that has been updated subsequently. This allows presentation at the participant's DPS of the most current version of the moderator's display screen.

Abstract: Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available.

Abstract: A method according to an embodiment of a system for efficient resource management of a signal flow programmed digital signal processor code is provided and includes determining a connection sequence of a plurality of algorithm elements in a schematic of a signal flow for an electronic circuit, the connection sequence indicating connections between the algorithm elements and a sequence of processing the algorithm elements according to the connections, determining a buffer sequence indicating an order of using the plurality of memory buffers to process the plurality of algorithm elements according to the connection sequence, and reusing at least some of the plurality of memory buffers according to the buffer sequence.

Abstract: The present invention relates to a display device for a glass cockpit of an aircraft, intended to provide video streams to a plurality of viewing screens of said glass cockpit, said aircraft being partitioned into a secured area, a so-called avionic world (AW), and a non-secured area, a so-called open world (OW), said system comprising at least one first port intended to receive first data to be displayed from a system (210, 310, 410) belonging to the avionic area and at least one second port intended to receive second data to be displayed from a system (220, 320, 420) belonging to the open world, the display device comprising: predetermined hardware resources allocated to the processing of the second data; a processor (241, 341, 441), belonging to the avionic area, adapted to controlling the hardware resources used by said processing and interrupting this processing if said hardware resources used exceed said allocated resources.

Abstract: Various techniques for remoting graphics are described in the claims, drawings, and text forming a part of the present disclosure.

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values for different attribute types (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel packet rows including the pixel surface attribute values are forwarded to other graphics pipeline stages for single thread processing (e.g. to a universal arithmetic logic unit capable of performing multiple graphics functions on the pixel surface attribute values).

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and also facilitates power conservation. Pixel packet information includes pixel surface attribute values are retrieved in a single unified data fetch stage. At a data fetch pipestage a determination may be made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values is performed determine if the pixel is occluded). A pixel packet status indicator (e.g., a kill bit) is set in the sideband portion of a pixel packet and the pixel packet is forwarded for processing in accordance with the pixel packet status indicator.

Abstract: Systems and methods for providing registration at a remote site that may include, for example, a monitoring module that may communicate with a remote site. A registration protocol may be used by the monitoring module and the remote site in generating the messages communicated during the registration process. The monitoring module may gather and generate various identification information to be included in the registration protocol messages. The registration information provided by the monitoring module may be stored at the remote site in a database server having a database. A confirmation message may be communicated from the remote site to the monitoring module that may either acknowledge successful registration or report that an error occurred during the registration process.

Abstract: Systems, servers, methods, media, and programs for storing a list of options associated with object-types, such as a chart-type, selected during an on-line session. When a new object-type is selected, some of the options in the first object-type are copied from the options list associated with the first object-type to the options list associated with the second (new) object-type. The list of options to be transferred is determined by a set rules associated with a transferable array and a set of rules associated with a quarantine set. The transferrable array includes rules for options available for transfer, and quarantine list includes rules for options and type pairs that are not available for transfer.

Abstract: The subject matter of this specification can be embodied in, among other things, a method that includes computer-implemented graphics frame buffer process that establishes on a computing device a graphics frame buffer accessible to be written by an application process and to be read by a graphics server process. The method further comprises generating a plurality of control bits whose value or values control access to the frame buffer by the application process and the graphics server process and reading frames from the frame buffer using the value or values in the plurality of control bits.

Abstract: When a plurality of display panel drivers is set to a state in conformity to given specifications, setting data indicative of details of the setting is stored in a memory. One of the display panel drivers supplies a first signal indicating that the setting data is in a readout condition to the memory and other display panel drivers. In response to the first signal, the memory reads and provides the setting data on the first line. The one display panel driver fetches the setting data on the first line to perform the setting based on the setting data. The other display panel drivers fetch the setting data from the first line in response to the first signal to perform the setting based on the setting data.

Abstract: A method according to an embodiment of a system for efficient resource management of a signal flow programmed digital signal processor code is provided and includes determining a connection sequence of a plurality of algorithm elements in a schematic of a signal flow for an electronic circuit, the connection sequence indicating connections between the algorithm elements and a sequence of processing the algorithm elements according to the connections, determining a buffer sequence indicating an order of using the plurality of memory buffers to process the plurality of algorithm elements according to the connection sequence, and reusing at least some of the plurality of memory buffers according to the buffer sequence.

Abstract: A system that displays a video signal on a display for a computer system is presented. During operation, the system receives a signal to switch from displaying a video signal from an internal video source to displaying a video signal from an external video source. In this system, the internal and external video sources are coupled to a bi-directional video port for the computer system, wherein the internal video source generates an output video signal and the external video source generates an input video signal. The system then determines whether the external video source is coupled to the bi-directional video port. If so, the system couples the external video source to the display and determines whether the external video source is a valid video source. If the external video source is a valid video source, the system displays the video signal from the external video source on the display.

Abstract: A system is configured to: conduct asynchronous updates, of a display, based on a fixed rate when operating in an asynchronous state; determine whether to switch to a synchronous state from the asynchronous state based on the asynchronous updates; conduct synchronous updates, of the display, after switching to the synchronous state; receive a lock request, and conduct updating of the display based on the lock request. The synchronous updates may be performed independent of the fixed rate.

Abstract: An apparatus has a first attribute setting unit which sets first attribute information of image data, a second attribute setting unit which sets second attribute information of the image data, and an input-output controller which writes and reads out image data to and from an external storage medium. The first attribute information is stored in the image data, and the second attribute information is stored in an area in the external storage medium, which is used to manage the image data to be written in the external storage medium.

Abstract: According to one embodiment, a flat panel display includes a first mounting portion including a first input pad and a first output pad, a second mounting portion including a second input pad and a second output pad, a first common terminal and a second common terminal, which have a common potential, and a guard ring wiring which is formed in a manner to extend from the first common terminal, to pass between the first input pad and the first output pad of the first mounting portion, to pass between the second input pad and the second output pad of the second mounting portion, and to reach the second common terminal, the guard ring wiring including a first resistor element of a first resistance value and a second resistor element of a second resistance value which is higher than the first resistance value.

Abstract: The present invention relates to methods and systems for updating a buffer. In one aspect, the present invention provides a method for updating a buffer, which includes strategically writing to the buffer to enable concurrent read and write to the buffer. The method eliminates the need for double buffering, thereby resulting in implementation cost and space savings compared to conventional buffering approaches. The method also prevents image tearing when used to update a frame buffer associated with a display, but is not limited to such applications. In another aspect, the present invention provides efficient mechanisms to enable buffer update across a communication link. In one example, the present invention provides a method for relaying timing information across a communication link.

Abstract: The present invention relates to methods and systems for updating a buffer. In one aspect, the present invention provides a method for updating a buffer, which includes strategically writing to the buffer to enable concurrent read and write to the buffer. The method eliminates the need for double buffering, thereby resulting in implementation cost and space savings compared to conventional buffering approaches. The method also prevents image tearing when, used to update a frame buffer associated with a display, but is not limited to such applications. In another aspect, the present invention provides efficient mechanisms to enable buffer update across a communication link. In one example, the present invention provides a method for relaying timing information across a communication link.

Abstract: Computer systems and methods that utilize a GPU whose operation is able to switch between ECC and non-ECC memory operations on demand. The computer system includes a graphics processing unit and a memory controller and local memory that are functionally integrated with the graphics processing unit. The memory controller has at least two operating modes comprising a first memory access mode that uses error checking and correction when accessing the local memory, and a second memory access mode that does not use error checking and correction when accessing the local memory. The memory controller is further operable to switch the operation of the memory controller between the first and second memory access modes without rebooting the computer system.

Abstract: A method of displaying a plurality of picture files on a display of a portable wireless communication device is described. The method comprises receiving a plurality of picture files, wherein each picture file of the plurality of picture files has location data stored in a location field for the picture file and relationship data in a relationship field related to at least one other picture file; displaying a first image associated with a first picture file; and displaying a second image in response to a prompt for a next image.