Abstract: The present disclosure discloses a method and system for switched display of a grayscale of a multi-line scan light-emitting diode (LED), and relates to the field of LED display technology. In view of the problems in the prior art that a multi-line scan constant-current source chip has an insufficient refresh rate, a low grayscale level, and a poor low-grayscale effect, the present disclosure provides a method during the display of relatively high grayscales, a display cycle is scrambled. During the display of relatively low grayscales, the grayscales are combined. In the present disclosure, a relatively high refresh rate and a grayscale level can still be ensured in a case of a relatively large quantity of line scans. In addition, in the case of low-grayscale display, the problems such as low-grayscale speckles, slightly dark low-grayscale, and relatively poor low-grayscale linearity are resolved, thereby improving a picture display effect.

Abstract: A display system includes a light emitting array and a driving circuit. The light emitting array includes: a plurality of scan lines, a plurality of channel lines, and a plurality of light emitting elements connected to the scan lines and the channel lines. The driving circuit includes: a delay-locked loop generating an internal global clock signal; a signal processor generating a scan control output and a channel control output based on the internal global clock signal and display data; a scan driver driving the scan lines based on the scan control output; and a channel driver providing a plurality of driving current signals respectively to the channel lines based on the channel control signal.

Abstract: A display includes eight modules. A relay group includes eight relays provided for the respective modules. Each relay includes: a buffer; a memory writer for writing video data into the buffer; and a memory reader that, after the memory writer completes writing, reads the video data from the buffer at a speed lower than a speed of the writing and outputs the read video data to the corresponding module. A video data supplier sequentially sorts the video data to the eight relays in such a manner that, per line of line data, the line data from the buffer of one relay of the eight relays is read during a writing period of the line data to buffers of the other seven relays.

Abstract: An LED display system has an LED display panel coupled to a driver circuitry. The driver circuitry includes a scrambled PWM generator, a register, and a memory. The driver circuit receives an image data from an external source and, after certain compensations, the compensated data is sent to the scrambled PWM generator to be distributed according to a new set of rules. Compared with existing technologies, this LED display has a host of benefits, including having a uniform optical energy output at low brightness.

Abstract: A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU. The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream.

Abstract: A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

Abstract: System and methods for providing quality of service (QOS) in networks. The method includes determining whether a transmit segment of a port of a network device has received a grant from a scheduler to transmit a packet. The port includes a plurality of sub-ports that share the transmit segment to transmit packets and a receive segment to receive packets. When the transmit buffer has received the grant, a virtual queue associated with the grant is mapped to a QOS bin that includes a minimum bandwidth limit threshold value, a maximum bandwidth threshold value, and a counter for counting actual bandwidth consumed. The QOS bin monitors bandwidth consumed by a source traffic group for adjusting QOS priority and the source traffic group includes the virtual queue.

Abstract: A system and method are disclosed for managing memory requests that are coordinated between a system memory controller and a graphics memory controller. Memory requests are pre-scheduled according to the optimization policies of the source memory controller and then sent over the CPU/GPU boundary in a bundle of pre-scheduled requests to the target memory controller. The target memory controller then processes pre-scheduling decisions contained in the pre-schedule requests, and in turn, issues memory requests as a proxy of the source memory controller. As a result, the target memory controller does not need to perform both CPU requests and GPU requests.

Abstract: A signal controlling method for a display device for signal processing between an external system and a display panel that displays an image by receiving a signal from the external system. The method includes receiving N clock signals and N data signals synchronized with the N clock signals from the external system through N channels, N being a natural number no less than 2; writing the received N data signals in N storage units in order of reception time of the N data signals; extracting one clock signal from the N clock signals; and outputting the N data signals written in the N storage units simultaneously in synchronization with the extracted clock signal.

Abstract: Disclosed herein is a graphics-processing unit (GPU) having an internal memory for general-purpose use and applications thereof. Such a GPU includes a first internal memory, an execution unit coupled to the first internal memory, and an interface configured to couple the first internal memory to a second internal memory of an other processing unit. The first internal memory may comprise a stacked dynamic random access memory (DRAM) or an embedded DRAM. The interface may be further configured to couple the first internal memory to a display device. The GPU may also include another interface configured to couple the first internal memory to a central processing unit. In addition, the GPU may be embodied in software and/or included in a computing system.

Abstract: Circuit and methods provide for adjustable power consumption using a plurality of memory controllers. In one example, a first memory controller has a first power consumption level. A second memory controller has a second power consumption level that differs from the first power consumption level. Memory controller bypass logic is connected to the first and second memory controllers and selects for a memory client at least one of the first and second memory controllers in response to a change in a power conservation condition.

Abstract: A scan-type display device control circuit is suitable for receiving successive frame data and driving a light-emitting diode (LED) display device accordingly. The scan-type display device control circuit includes a ping-pong buffer, a data storage controller, a line scan controller, a display buffer, and a scrambled pulse width modulation (PMW) signal generating device. The scan-type display device control circuit can utilize frame data circularly and repeatedly, so as to prevent a great mass of data from being transmitted repeatedly. Therefore, a band width for inputting data can be reduced significantly. Furthermore, the scrambled PMW signal generating device can scramble a PMW signal with a long period into a plurality of scrambled PMW signals with a short period. Therefore, the refresh rate can be efficiently enhanced without changing the band width for inputting data.

Abstract: A system and method for cryptographically securing a graphics system connectable via an external bus to a computing system, the graphics system including a graphics processor, a video memory and a memory controller for controlling the flow of data to and from the video memory. The graphics system further includes a copy engine for copying data between a system memory of the computing system and the video memory, where this copy engine acts independently of the graphics processor of the graphics system. The present invention enables the copy engine of the graphics system to decrypt encrypted data in the course of copying data from the system memory to the video memory and to encrypt unencrypted data in the course of copying data from the video memory to the system memory. Thus, cryptographic protection of secure content may be assured by the graphics system without the excessive usage of its primary resources for this non-graphical purpose.

Abstract: A driving chip set includes a master chip and at least one slave chip. In the master chip, a master receiving terminal receives a data signal through a first data transmission interface; a processing unit generates a first partial data signal and a second partial data signal according to the data signal; a master buffer registers the first partial data signal; a master output terminal outputs the second partial data signal through a second data transmission interface. In the slave chip, a slave receiving terminal receives the second partial data signal through the second data transmission interface and it is registered by a slave buffer. The processing unit controls a master driver and a slave driver to output the first partial data signal and second partial data signal to a display panel. The display panel displays an image according to the first partial data signal and second partial data signal.

Abstract: A parallel processing subsystem includes a plurality of general processing clusters (GPCs). Each GPC includes one or more clipping, culling, viewport transformation, and perspective correction engines (VPC). Since VPCs are distributed per GPC, each VPC can process graphics primitives in parallel with the other VPCs processing graphics primitives.

Abstract: A system and method for efficiently processing access requests for a shared resource. A computing system includes a shared memory accessed by multiple requestors. Control logic determines two requestors seek to access a same data block within the shared memory. In response to the determination, a first requestor of the two requestors sends a read request to the shared memory on behalf of the two requestors. The second requestor of the two requestors is prevented from sending a read request. In response to detecting data is returned as a response to the read request generated by the first requestor, both the first requestor and the second requestor retrieve the data. In response to detecting a given requestor of the two requestors generates an indication that it is unable to continue retrieving the same response data, the two requestors return to generating separate, respective read requests.

Abstract: Technologies are described herein for buffer management during real-time streaming. A video frame buffer stores video frames generated by a real-time streaming video capture device. New video frames received from the video capture device are stored in the video frame buffer prior to processing by a video processing pipeline that processes frames stored in the video frame buffer. A buffer manager determines whether a new video frame has been received from the video capture device and stored in the video frame buffer. When the buffer manager determines that a new video frame has arrived at the video frame buffer, it then determines whether the video processing pipeline has an unprocessed video frame. If the video processing pipeline has an unprocessed video frame, the buffer manager discards the new video frame stored in the video frame buffer or performs other processing on the new video frame.

Abstract: At least some embodiments of the present disclosure include a method for compositing media and non-media content of user interface for display on a device. The method includes constructing a data structure having a hierarchy of layers associated with the user interface of the device. The method further includes determining whether each layer of the data structure is associated with media or non-media content. The data structure or layer tree is traversed in order to determine whether each of the layers of the data structure is associated with media or non-media content. The method further includes detaching a layer associated with media content from the data structure. The method further includes storing media content in a first memory location. The method further includes storing non-media content in a second memory location. The method further includes compositing the media and non-media content for display on the device.

Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.

Abstract: A method of managing multiple contexts for a single mode display includes receiving a plurality of tasks from one or more applications and determining respective contexts for each task, each context having a range of memory addresses. The method also includes selecting one context for output to the single mode display and loading the selected context into a graphics processor for the display.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A method, system and product are disclosed for volume rendering of medical images on a shared memory system implemented on a multi-socket mainboard with multiple multi-core processors and multiple last level caches, cores that share a cache being united in a socket. The method includes decomposing the image space to be used for rendering in regions, each region including a plurality of tiles; assigning two sockets to each of the decomposed regions; determining a tile enumeration scheme for a region; rendering all tiles within a region according to a determined tile enumeration scheme on the assigned two sockets until the respective region is finished; if a region is finished, assigning the two sockets to another region; and if no region is left, splitting an existing region of un-rendered tiles into sub-regions according to a splitting scheme and applying the steps recursively for the sub-regions.

Abstract: A method and an apparatus for maintaining separate information for graphics commands that have been sent to a graphics processing unit (GPU) and for graphics commands that have been processed by the GPU are described. The graphics commands may be associated with graphics resources. A manner to respond to a request for updating the graphics resources may be determined based on examining the separate information maintained for the graphics commands. The request may be received from a graphics API (application programming interface). Responding to the request may include at least one of notifying the graphics API regarding a status of the graphics resources and updating the graphics resources identified by the request.

Abstract: A dual mode touchscreen display disposed in an information handling system chassis proximate a keyboard selectively presents images from information generated by a central processing unit or from information generated by a secondary processor associated with the touchscreen display. An operating system executing on the central processor unit presents information at the touchscreen through a serial link by treating the touchscreen as a secondary display to a primary display integrated in the chassis. Alternatively, an application executing on the secondary processor presents information at the touchscreen independent of the central processing unit or the operating system. As an example, the touchscreen display presents a number pad under the direction of the operating system to accept number pad inputs or, alternatively, presents a number pad under the direction of an application running on the secondary processor to accept number pad inputs that are forwarded to a keyboard controller.

Abstract: A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.

Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.

Abstract: An apparatus for use in image processing is set forth that comprises a pixel processor, context memory, and a context memory controller. The pixel processor is adapted to execute a pixel processing operation on a target pixel using a context of the target pixel. The context memory is adapted to store context values associated with the target pixel. The context memory controller may be adapted to control communication of context values between the pixel processor and the context memory. Further, the context memory controller may be responsive to a context initialization signal or the like provided by the pixel processor to initialize the content of the context memory to a known state, even before the pixel processor has completed its image processing operations and/or immediately after completion of its image processing operations. In one embodiment, the pixel processor executes a JBIG coding operation on the target pixel.

Abstract: A dual mode touchscreen display disposed in an information handling system chassis proximate a keyboard selectively presents images from information generated by a central processing unit or from information generated by a secondary processor associated with the touchscreen display. An operating system executing on the central processor unit presents information at the touchscreen through a serial link by treating the touchscreen as a secondary display to a primary display integrated in the chassis. Alternatively, an application executing on the secondary processor presents information at the touchscreen independent of the central processing unit or the operating system. As an example, the touchscreen display presents a number pad under the direction of the operating system to accept number pad inputs or, alternatively, presents a number pad under the direction of an application running on the secondary processor to accept number pad inputs that are forwarded to a keyboard controller.

Abstract: In an system for representing a signal on a display device, the signal is fed to a first sampling device and, time-displaced via a time-delay device, is fed at least to a second sampling device for sampling. The sampling values of the first sampled signal and the sampling values of the second sampled signal are appropriately ordered in a first memory control device of a first component connected to the first sampling device in order to compensate a time-delay of the sampling values of the second sampled signal caused by the time-delay device, and are passed to a post-treatment device provided in the first component and connected to the display device.

Abstract: Provided are a system for compensating response speed and a method of controlling frame data of an image. The system includes: a circuit for compensating response speed; an internal frame memory that comprises N sub frame memories formed in a single chip with the circuit for compensating response speed, wherein N is a natural number; a frame memory controller that comprises N sub frame memory controllers corresponding to each sub frame memory; and a data flow controller that comprises N write first-in-first-out (FIFO) circuits and N read FIFO circuits corresponding to each sub frame memory.

Abstract: A method of transmitting video content between a computing device and display device. The method includes establishing a data connection between a receiver unit and the display device, where the receiver unit includes a first wireless transceiver and an output port, establishing a data connection between a transmitter unit and the computing device, where the transmitter unit includes a second wireless transceiver and a memory and is configured to perform two-way wireless communications with only the receiver unit and is configured to not perform two-way wireless communications with any other devices, and transmitting the video content from the transmitter unit to the receiver unit.

Abstract: A method and an apparatus for maintaining separate information for graphics commands that have been sent to a graphics processing unit (GPU) and for graphics commands that have been processed by the GPU are described. The graphics commands may be associated with graphics resources. A manner to respond to a request for updating the graphics resources may be determined based on examining the separate information maintained for the graphics commands. The request may be received from a graphics API (application programming interface). Responding to the request may include at least one of notifying the graphics API regarding a status of the graphics resources and updating the graphics resources identified by the request.

Abstract: A self-addressing control unit system and method for controlling a sequence of or an array of display signs comprising of a remote or master controller and a plurality of control units interconnected by a physical or logical parallel electrical bus having multiple connections to transfer data or power between the plurality of control units; wherein the electrical bus further comprises of a main broadcast line, an addressing line and a feedback line to every control unit. The remote or master controller transmits an initial address to a first of the plurality of control units on the addressing line of the bus where a calculator or computer within each of the plurality of control units computes its own address by performing a mathematical operation that changes the initial address by adding a constant of one to the address received to produce its own new address.

Abstract: A system and method are disclosed for managing memory requests that are coordinated between a system memory controller and a graphics memory controller. Memory requests are pre-scheduled according to the optimization policies of the source memory controller and then sent over the CPU/GPU boundary in a bundle of pre-scheduled requests to the target memory controller. The target memory controller then processes pre-scheduling decisions contained in the pre-schedule requests, and in turn, issues memory requests as a proxy of the source memory controller. As a result, the target memory controller does not need to perform both CPU requests and GPU requests.

Abstract: A computer of an information processing apparatus repeatedly accepts an operation to designate at least one of a plurality of command elements making up of a command, executes at least any one of a first memory writing processing to write a first command element having a specific attribute out of the command elements corresponding to the accepted operation in a first memory and a second memory writing processing to write a second command element having an attribute different from the attribute in a second memory, determines whether or not a command element array stored over the first memory and the second memory satisfies an execution allowable condition every execution of the writing processing, and processes information according to the command element array when the satisfaction is determined.

Abstract: For providing a display device and a method for transferring an image data, shortening process time required to transfer image data without greater processing capacity, the CPU 4 outputs the bypass write signal to the GDC 6, the CPU 4 then outputs the read signal to both the ROM 5 and the GDC 6, and the ROM 5 outputs the image data to the data bus 8 according to input of the read signal, wherein the GDC 6 directly reads the image data outputted on the data bus 8 according to input of the read not through the CPU 4 and writes the read image data to the VRAM 7.

Abstract: An image processing apparatus including a frame doubling processing part for generating a doubled image signal, a false impulse drive processing part for outputting a current image signal after dividing the doubled image signal, a first frame memory for outputting the current image signal as a previous image signal delayed by one sub-frame, a correction processing part for correcting a gradation level of the current image signal after the previous image signal and the current image signal being input thereto, a second frame memory for outputting a delayed doubled image signal from the doubled image signal, and a movement detector for outputting a movement detection signal after the delayed doubled image signal and the doubled image signal being input thereto is provided, wherein the correction processing part corrects the gradation level of the current image signal when the movement detection signal is a signal indicating a dynamic image.

Abstract: The present invention enables to update a program in a storage control device while processing access requests, without imposing any burden on a host. When execution of updating of a program is commanded from a management terminal, an update control unit starts within the controller which is the object of updating. After a host I/F unit has been connected to an access request processing unit within another controller by a connection control unit, the update control unit updates a program which is stored in a program memory or a boot disk. When this updating is completed, the update control unit reconnects the host I/F unit to its access processing unit by the connection control unit. Since the stored contents of data memories are synchronized, the other access request processing unit can continue processing access requests from the host in place one access request processing unit.

Abstract: A system, apparatus, method and article to perform buffering techniques are described. The apparatus may include a buffer having a fixed number of storage slots that store reconstructed picture representations received from an image processing module. Also, the apparatus may include a buffer status unit to store a multiple information items to indicate one or more buffer characteristics of the buffer. Further, the apparatus may include a buffer control module to manage storage within the buffer.

Abstract: A method of driving a display device includes outputting an upper data signal array of a (n+1)th frame to an upper display area of a display panel during a first frame period; and, outputting a lower data signal array of a nth frame to a lower display area of the display panel during the first frame period is provided. The display panel has at least an upper display area and a lower display area which may be independently operable, the display areas communicating with a memory device storing and outputting a signal data array of a (n+1)th frame to an upper display area of a display panel during a first frame period; and, outputting a lower data signal array of a nth frame to a lower display area of the display panel during the first frame period.

Abstract: There is provided an image processing device for controlling a display device to display a plurality of unit images making up a moving image at predetermined intervals, the image processing device including: 4×N (N: an arbitrary integer) quadrant memories; a separation section; a memory output control section; an assignment section; and an output control section.

Abstract: According to an aspect of the invention, there is provided a mobile phone including: a calculating unit configured to calculate an update range of the update data; an input-side switch unit configured to switch a first frame buffer of the plurality of frame buffers to which the update data is to be inputted; and an output-side switch unit configured to switch a second frame buffer of the plurality of frame buffers from which the update data is to be outputted. If the calculated update range is equal to or greater than a predetermined value, the input-side switch unit is connected to the first frame buffer different from the second frame so as to input the update data. If the input-side switch unit completes the input of the update data, the output-side switch unit is connected to the first frame buffer so as to output the update data.

Abstract: A system for processing image data from a plurality of images is disclosed. The invention involves alpha blending of two images of different resolution and color space utilizing shared logic for multiple image streams and without display storage frame buffer. The invention utilizes Direct Memory Access (DMA) fetching module for fetching image data from source images or from source image memory areas and transferring the data to another memory area without having to go through a central processing unit or display storage frame buffer. The DMAs are configured with direct registers or memory mapped descriptors as to the location of the source data. The DMA channels of the DMA module will fetch a portion of the source images (tiling) utilizing a link list or series of descriptors in a certain fetching order. The DMA modules can perform the alpha blending on the fetched image data.

Abstract: A scan-type display device control circuit is suitable for receiving successive frame data and driving a light-emitting diode (LED) display device accordingly. The scan-type display device control circuit includes a ping-pong buffer, a data storage controller, a line scan controller, a display buffer, and a scrambled pulse width modulation (PMW) signal generating device. The scan-type display device control circuit can utilize frame data circularly and repeatedly, so as to prevent a great mass of data from being transmitted repeatedly. Therefore, a band width for inputting data can be reduced significantly. Furthermore, the scrambled PMW signal generating device can scramble a PMW signal with a long period into a plurality of scrambled PMW signals with a short period. Therefore, the refresh rate can be efficiently enhanced without changing the band width for inputting data.

Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: One embodiment provides a system including a communications channel, a first channel master, and a second channel master. The first channel master is configured to obtain latency values and maintain a first schedule of data traffic on the communications channel based on the latency values. The second channel master is configured to obtain the latency values and maintain a second schedule of data traffic on the communications channel based on the latency values. The first channel master manages data on the communications channel via the first schedule and the second channel master manages data on the communications channel via the second schedule.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: A transmitter/receiver obtains scanning data by transmitting ultrasonic waves to a subject to be examined and receiving reflected waves from the subject to be examined. An image processor converts the scanning data into image data represented by a predetermined coordinate system and applies a predetermined smoothing process to the image data. The image processor calculates the vector of each point, based on the image data after the smoothing process. The image processor generates three-dimensional image data by applying a ray-tracing process to the image data to which the smoothing process has not been applied, according to the vector.

Abstract: A computer implemented method, apparatus, and computer usable program code are provided for managing dual active controllers in a high availability storage configuration. Redundant dual active controllers in high availability storage configurations are made to appear as individual storage target devices to a host system. Each controller owns certain volumes of data storage. When a host system sends a request to identify available data volumes, the controller that owns certain volumes provides preferred paths to those owned volumes. The host system may also send an inquiry to a controller that asks the controller about data volumes not owned by the controller. For such inquiries, no paths to the non-owned data volumes are returned to the host system.