Plural Memory Controllers Patents (Class 345/532)
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Patent number: 7800605Abstract: Multi-view video switching control methods and systems are disclosed. It is determined whether a VBI (vertical blanking interval) of signals respectively transmitted by a first GA (graphic array) and a second GA is detected. The video source of first and second GAs belongs to the same first video source. If the VBI corresponding to first GA is detected first, the video source of first GA is switched to a second video source, and the video source of second GA is switched to the second video source if the VBI corresponding to second GA is then present. If the VBI corresponding to second GA is detected first, the video source of second GA is switched to the second video source, and the video source of first GA is switched to the second video source if the VBI corresponding to first GA is then present.Type: GrantFiled: August 5, 2005Date of Patent: September 21, 2010Assignee: Via Technologies Inc.Inventor: Ping-Huei Hsieh
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Method of implementing an accelerated graphics port for a multiple memory controller computer system
Patent number: 7777752Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.Type: GrantFiled: July 27, 2005Date of Patent: August 17, 2010Assignee: Round Rock Research, LLCInventor: Joseph Jeddeloh -
Patent number: 7672573Abstract: A system includes an integrated encoder comprising an optical storage controller for coupling to an optical storage medium, and a data encoder for coding input data coupled to the optical storage controller, a first external memory coupled to a first memory controller in the integrated encoder, and a second external memory coupled to a second memory controller in the integrated encoder. In one aspect, the integrated encoder further comprises a first memory arbiter for selectively directing access to the first external memory by the optical storage controller and the data encoder, and a second memory arbiter for selectively directing access to the second external memory by the optical storage controller and the data encoder.Type: GrantFiled: May 13, 2004Date of Patent: March 2, 2010Assignee: Sunplus Technology Co., Ltd.Inventor: Tzu-Hsin Wang
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Patent number: 7656410Abstract: A system, apparatus, method and article to perform buffering techniques are described. The apparatus may include a buffer having a fixed number of storage slots that store reconstructed picture representations received from an image processing module. Also, the apparatus may include a buffer status unit to store a multiple information items to indicate one or more buffer characteristics of the buffer. Further, the apparatus may include a buffer control module to manage storage within the buffer.Type: GrantFiled: March 31, 2006Date of Patent: February 2, 2010Assignee: Intel CorporationInventors: Yi-Jen Chiu, Mei-Chen Yeh
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Publication number: 20090244074Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.Type: ApplicationFiled: June 5, 2009Publication date: October 1, 2009Inventors: John S. Montrym, David B. Glasco, Steven E. Molnar
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Patent number: 7595804Abstract: A display of CPU utilization in a multiprocessor system is provided. This feature illustrates processor utilization and application group assignments to CPUs and clusters of CPUs. Various graphic indicator are described that can be used to display processor utilization and indicate processors that have no application group assignments. For example, bar graphs as well as gauge displays can be used to visually convey processor utilization. As a result, a user can visually determine the processor utilization and application group assignments across a multiprocessor system. Additionally, various colors and shadings can be used to visually convey application group assignments.Type: GrantFiled: November 14, 2003Date of Patent: September 29, 2009Assignee: Unisys CorporationInventor: Clifford Shiroku Shimizu
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Patent number: 7584321Abstract: Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.Type: GrantFiled: November 12, 2003Date of Patent: September 1, 2009Assignee: NVIDIA CorporationInventors: Chris Alan Malachowsky, David G. Reed, Sean Jeffrey Treichler, Brad W. Simeral
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Patent number: 7532218Abstract: Embodiments of methods and apparatus for memory training concurrent with data transfers are disclosed. For an example embodiment, data may be transferred from a first memory device to a first partition of a memory controller, and a training operation may be performed for a second partition of the memory controller coupled to a second memory device while the first partition of the memory controller is transferring data from the first memory device.Type: GrantFiled: February 1, 2005Date of Patent: May 12, 2009Assignee: nVidia CorporationInventor: Barry Wagner
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Patent number: 7477205Abstract: A computer system including a processor, a display, and a graphics unit coupled between the processor and the display, in which the processor is configured to perform multi-display operations which generate multiple frames of display data for simultaneous display, and a graphics unit for use in such a system. Typically, the graphics unit includes graphics memory that includes at least two frame buffers, and the processor operates as if it were independently asserting multiple streams of display data to multiple frame buffers for driving multiple displays independently. Another aspect of the invention is a system that displays data from a frame buffer on a screen.Type: GrantFiled: November 5, 2002Date of Patent: January 13, 2009Assignee: NVIDIA CorporationInventors: Abraham B. de Waal, Walter E. Donovan
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Patent number: 7450116Abstract: An apparatus for storing, displaying and recalling data, includes a display field for displaying data, a memory for storing said data, a keypad for entering the data into the memory, and a field button associated with the display field for initiating entry of the data into the apparatus. The field button is adjacent to the display field. A recall button for recalling stored data and for causing the recalled stored data to appear on the display field is also provided adjacent to the display field.Type: GrantFiled: September 27, 2004Date of Patent: November 11, 2008Assignee: Flight Vitals, Inc.Inventor: Marc Howard Greenstein
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Patent number: 7450125Abstract: A method and system for compressing and displaying a digital ink trace. Raw ink data is smoothed, and sharp points of the smoothed line are found. Curve-fitting is then used to generate a mathematical expression that defines the line segments between adjacent sharp points. The ink trace then is represented by a backbone spline that includes the sharp points and the mathematical expressions for the line segments. Thickness information, such as pressure or acceleration information, is combined with the backbone spline to provide a compressed ink file that represents a contour curve of the original ink trace. A display module uses an algorithm to separate the contour curve into a sequence of straight lines. A set of pixels is then generated for the display of each straight line using a novel antialiasing method. The pixels at the ends of adjacent straight lines are aligned using a weighting algorithm.Type: GrantFiled: June 1, 2006Date of Patent: November 11, 2008Assignee: Microsoft CorporationInventors: Jian Wang, Yu Zou, Liyong Chen, Siwei Lyu
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Patent number: 7446776Abstract: A system, a circuit and a method are given, to realize a display control and driver interface with graphic display memory, whereby the use of dynamic RAM rather than static RAM for this graphic display memory is new. This has the advantage, that for a given size of display memory (number of bits) the DRAM silicon area is significantly less than that of the SRAM. Said system and circuit are designed in order to be implemented with a very economic number of components, capable to be realized with modern monolithic integrated circuit technologies and implementing the given method. This display controller and driver chip can then be used for all LCD display devices including STN (Super Twisted Nematic), CSTN (Colour STN), TFT (Thin Film Transistor) LCD's and for OLED (Organic Light Emitting Diode) displays.Type: GrantFiled: August 30, 2004Date of Patent: November 4, 2008Assignee: Dialog Semiconductor GmbHInventors: David Clewett, Toshiki Kitaguchi
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Patent number: 7439983Abstract: A pixel shader is operated to perform a first texture lookup in an index buffer to obtain a vertex index value for a geometric primitive to be displayed. The pixel shader is also operated to perform a second texture lookup in a vertex buffer to obtain vertex data, wherein the vertex data corresponds to the previously obtained vertex index value for the geometric primitive to be displayed. The first and second texture lookups are repeated by the pixel shader such that vertex data is obtained for each vertex required to define the geometric primitive to be displayed. The pixel shader is then operated to rasterize the geometric primitive to be displayed, wherein the rasterizing is performed using the vertex data previously obtained by the pixel shader.Type: GrantFiled: February 10, 2005Date of Patent: October 21, 2008Assignee: Sony Computer Entertainment Inc.Inventors: Remi Arnaud, Roy Hashimoto
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Patent number: 7423644Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.Type: GrantFiled: July 5, 2006Date of Patent: September 9, 2008Assignee: ATI Technologies Inc.Inventors: Vineet Goel, Stephen L. Morein, Robert Scott Hartog
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Publication number: 20080198170Abstract: A system for processing image data from a plurality of images is disclosed. The invention involves alpha blending of two images of different resolution and color space utilizing shared logic for multiple image streams and without display storage frame buffer. The invention utilizes Direct Memory Access (DMA) fetching module for fetching image data from source images or from source image memory areas and transferring the data to another memory area without having to go through a central processing unit or display storage frame buffer. The DMAs are configured with direct registers or memory mapped descriptors as to the location of the source data. The DMA channels of the DMA module will fetch a portion of the source images (tiling) utilizing a link list or series of descriptors in a certain fetching order. The DMA modules can perform the alpha blending on the fetched image data.Type: ApplicationFiled: February 20, 2007Publication date: August 21, 2008Applicant: MTEKVISION CO., LTD.Inventor: Rabindra Guha
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Patent number: 7369132Abstract: A graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a buffer including a buffering space shared by the memory clients. The buffering module also includes a buffer controller connected to the buffer. The buffer controller is configured to: (1) dynamically assign portions of the buffering space to respective ones of the memory clients; (2) coordinate storage of the data in the assigned portions; and (3) coordinate delivery of the data from the assigned portions to respective ones of the memory clients.Type: GrantFiled: March 20, 2007Date of Patent: May 6, 2008Assignee: Nvidia CorporationInventors: Brijesh Tripathi, Wayne Douglas Young, Adam E. Levinthal, Stephen M. Ryan
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Patent number: 7347570Abstract: A multimedia presentation apparatus and method by which a presenter is freed from the requirement of having or providing or transporting a supporting computer system such as the notebook or laptop system by the incorporation of computing capability and an accessible data port into the housing of the apparatus through which an executable data file may be delivered to cause generation of the desired presentation.Type: GrantFiled: November 22, 2002Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Charles Edward Kuhlmann, Francis Edward Noel, Jr., Charles Joseph Sannipoli
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Patent number: 7333106Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a Z-buffer memory. The apparatus also includes a set of bits, each of which corresponds to a block of the Z-buffer memory. The apparatus also includes an initialization (init) register. The apparatus also includes control logic coupled to the Z-buffer memory, the set of bits, and the init register. The control logic sets the set of bits upon receipt of an initialization request. The control logic retrieves a Z value from either the init register or from the Z-buffer memory according to the states of the set of bits.Type: GrantFiled: March 27, 2003Date of Patent: February 19, 2008Assignee: Silicon Motion, Inc.Inventors: Tsailai Terry Wu, Ming Chen
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Patent number: 7292235Abstract: A control driver includes a display memory control section which generates a first process control signal when image data includes only first image data which has a pixel size equal to or smaller than that of a display section, and generates a second process control signal when the image data includes first image data and second image data and the first image data has a pixel size equal to that of the display section, and a display memory section which stores upper and lower portions of the first image data as first and second portions of display data in response to the first process control signal, and stores the upper portion of the first image data and an upper portion of the second image data as the first and second portions of the display data in response to the second process control signal. The display data is displayed on the display section.Type: GrantFiled: June 2, 2004Date of Patent: November 6, 2007Assignee: NEC Electronics CorporationInventor: Takashi Nose
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Publication number: 20070188507Abstract: The present invention enables to update a program in a storage control device while processing access requests, without imposing any burden on a host. When execution of updating of a program is commanded from a management terminal, an update control unit starts within the controller which is the object of updating. After a host I/F unit has been connected to an access request processing unit within another controller by a connection control unit, the update control unit updates a program which is stored in a program memory or a boot disk. When this updating is completed, the update control unit reconnects the host I/F unit to its access processing unit by the connection control unit. Since the stored contents of data memories are synchronized, the other access request processing unit can continue processing access requests from the host in place one access request processing unit.Type: ApplicationFiled: June 7, 2006Publication date: August 16, 2007Inventors: Akihiro Mannen, Akira Nishimoto, Junji Ogawa
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Patent number: 7256789Abstract: It comprises a main CPU, a main memory for storing the programs, display data and other data, a data processing circuit for performing a processing to convert the display data in the main memory to the data format for the display, a display memory section for storing the converted display data, an output processing circuit for performing a processing to output the display data on the screen, a DMA for performing a data access to the main memory, a program memory, a data memory, a display processor for interpreting the commands/data described in the program memory and the data memory and transferring the display data according thereto, and a sync signal generating circuit.Type: GrantFiled: January 22, 1998Date of Patent: August 14, 2007Assignee: Sharp Kabushiki KaishaInventors: Satoshi Nakamura, Hiroyuki Yamamura, Shinzi Yamamoto, Masaaki Moriya
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Patent number: 7253818Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.Type: GrantFiled: August 7, 2001Date of Patent: August 7, 2007Assignee: ATI Technologies, Inc.Inventors: Chun Wang, Youjing Zhang, Richard K. Sita, Glen T. McDonnell, Babs L. Carter
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Patent number: 7243041Abstract: A device to control memory bandwidth including a processing unit and a memory connected to the processing unit, the memory having a memory controller driver to issue at least one command based on a memory bandwidth requirement of another driver process. A memory controller to direct data to and from the memory. An active cooling device is connected to the processing unit and a thermal sensor.Type: GrantFiled: September 30, 2004Date of Patent: July 10, 2007Assignee: Intel CorporationInventors: Rajeev K. Nalawadi, Murali Ramadoss
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Patent number: 7221369Abstract: Apparatus, system, and method for delivering data to multiple memory clients are described. In one embodiment, a graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the set of memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a unitary buffer and a buffer controller connected to the unitary buffer. The buffer controller is configured to coordinate storage of the data in the unitary buffer, and the buffer controller is configured to coordinate delivery of the data from the unitary buffer to respective ones of the set of memory clients.Type: GrantFiled: July 29, 2004Date of Patent: May 22, 2007Assignee: Nvidia CorporationInventors: Brijesh Tripathi, Wayne Douglas Young, Adam E. Levinthal, Stephen M. Ryan
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Patent number: 7200287Abstract: The image processing apparatus is provided with a plural memory controllers, each of which controls a RAM. The memory controllers are connected to an SIMD type arithmetic processing section. A control register is connected to the memory controllers. The control register controls transfer of image data between the RAMs and the SIMD type arithmetic processing section.Type: GrantFiled: December 28, 2000Date of Patent: April 3, 2007Assignee: Ricoh Company, LtdInventors: Hiroaki Fukuda, Yoshiyuki Namizuka, Hideto Miyazaki, Shinya Miyazaki, Yasuyuki Nomizu, Sugitaka Oteki, Takako Satoh, Takeharu Tone, Fumio Yoshizawa, Yuji Takahashi, Hiroyuki Kawamoto, Rie Ishii
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Patent number: 7180522Abstract: A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.Type: GrantFiled: August 31, 2004Date of Patent: February 20, 2007Assignee: Micron Technology, Inc.Inventors: William Radke, James R. Peterson
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Patent number: 7173629Abstract: A memory control unit adjusts and sets the address of an image data area in the memory space of a memory and the address of a window area adjacent to the memory area, using a memory controller. The memory control unit stores data, other than image data that is supplied, at a specified address location and, when a control signal is sent to the memory, reads out the image data, including data stored in the window area, from the memory. The data that is read out from the window area is inserted into a predetermined position during a blanking period.Type: GrantFiled: March 21, 2001Date of Patent: February 6, 2007Assignee: Fuji Photo Film Co., Ltd.Inventor: Masanari Asano
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Patent number: 7123267Abstract: An additional data transmission channel is provided between the north bridge chip and the system memory when the graphic accelerator is integrated into the north bridge chip. The additional data transmission channel can be similar to the existent data transmission channel between the north bridge chip and the system memory for providing extensive data transmission bandwidth. Alternatively, the additional data transmission channel can be specific to the communication between the graphic accelerator in the north bridge chip and the frame buffer in the system memory.Type: GrantFiled: July 29, 2003Date of Patent: October 17, 2006Assignee: Via Technologies, Inc.Inventors: Chih-Yuan Liu, Chi-Hsin Lin, Mei-Ling Lin, Chia-Hsing Yu
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Patent number: 7109987Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.Type: GrantFiled: March 2, 2004Date of Patent: September 19, 2006Assignee: ATI Technologies Inc.Inventors: Vineet Goel, Stephen L. Morein, Robert Scott Hartog
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Patent number: 7100118Abstract: In an embedded system, for instance in a household appliance, in addition to the usual embedded microprocessor/microcontroller there is provided another processor which actually executes a user interface HTML document for accepting user input, for instance from a keypad and controlling the display device, for instance an LCD. The embedded microprocessor hosts the user interface document, responds to requests from the other processor, keeps track of changes in variables shared with the other processor, and executes the control device functionality. The other processor renders the graphical user interface to the display and interacts with the user by executing local functions to operate on the memory and i/o resources of the embedded processor as described by the user interface document served to it.Type: GrantFiled: October 20, 2000Date of Patent: August 29, 2006Assignee: Amulet Technologies, LLCInventor: Kenneth J. Klask
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Patent number: 7071946Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.Type: GrantFiled: February 10, 2004Date of Patent: July 4, 2006Assignee: Micron Technology, Inc.Inventor: Joseph Jeddeloh
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Patent number: 7030873Abstract: A system for generating three-dimensional shape data about a high precision printed board without considerable amount of time and efforts. The system comprises a first storage means for storing therein three-dimensional simple shape data about a printed board; a second storage means for storing therein detailed shape data an electronic component; a third storage means for storing therein wiring data; and a generation.Type: GrantFiled: December 14, 2000Date of Patent: April 18, 2006Assignee: Zuken Inc.Inventor: Tatsuhiro Matsuda
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Patent number: 7027057Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.Type: GrantFiled: August 12, 2003Date of Patent: April 11, 2006Assignee: Intel CorporationInventors: Satchit Jain, Debra T. Cohen, Leslie E. Cline, Barnes Cooper, Anil V. Nanduri
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Patent number: 7015921Abstract: An apparatus, in a data processing system having at least one host processor with host processor cache and host memory, includes a chip interconnect, a cache coherent interface coupled to the chip interconnect wherein the cache coherent interface provides cache coherent access, a cache non-coherent interface coupled to the chip interconnect wherein the cache non-coherent interface provides cache non-coherent access to the host memory, and a compute engine coupled to the chip interconnect and coupled to the cache coherent interface and coupled to cache non-coherent interface wherein the compute engine issues a memory access request. Other methods and apparatuses are also described.Type: GrantFiled: December 31, 2001Date of Patent: March 21, 2006Assignee: Apple Computer, Inc.Inventors: Sushma Shrikant Trivedi, Joseph P. Bratt
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Apparatus and method for dynamically disabling faulty embedded memory in a graphic processing system
Patent number: 6963343Abstract: A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.Type: GrantFiled: June 23, 2000Date of Patent: November 8, 2005Assignee: Micron Technology, Inc.Inventors: James R. Peterson, William Radke -
Method of implementing an accelerated graphics/port for a multiple memory controller computer system
Patent number: 6947050Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.Type: GrantFiled: May 4, 2004Date of Patent: September 20, 2005Assignee: Micron Technology Inc.Inventor: Joseph Jeddeloh -
Patent number: 6913362Abstract: A projection display apparatus which display a projected image and may be free from connection with a computer. The projection display apparatus carries out processing with information stored in a portable memory and includes a memory controller that reads out the information stored in the portable memory; an image processing section that prepares display image data. The display image data represents an image to be displayed from the image data stored in the portable memory according to an instruction of a processing program that is read from the portable memory and represents a series of processing steps to be executed by the projection display apparatus. An electro-optic device then forms image light in response to the display image data, and an optical system projects the image light to display the image.Type: GrantFiled: December 24, 2003Date of Patent: July 5, 2005Assignee: Seiko Epson CorporationInventors: Takafumi Ito, Shoichi Akaiwa
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Patent number: 6912000Abstract: A picture processing apparatus is composed of a plurality of picture processing systems. Each picture processing system includes an identical picture processing IC (integrated circuit) and a plurality of memories each capable of memorizing a picture frame and including at least two memories operating at different timings. The picture processing IC includes a picture processing unit, an operation timing signal generator, a plurality of control timing signal generators for controlling different memories, and a memory control signal selection circuit for selectively outputting one of at least two memory control timing signals. As a result, the number of output pins of each picture processing IC for outputting memory control signal can be reduced, whereby the picture processing apparatus can be produced at a lower cost while retaining an identically large size of the picture processing ICs.Type: GrantFiled: February 23, 2000Date of Patent: June 28, 2005Assignee: Canon Kabushiki KaishaInventor: Kazuyuki Shigeta
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Patent number: 6897873Abstract: A display control apparatus contains a video memory, a video memory controller, a color palette memory and a color palette replacer signal generator. The video memory stores display data that are read from a CD-ROM and contain header data (HA-HD), palette data (P0-P2) and bitmap data (BA-BD) in connection with four planes which are combined together to form one frame of picture. The header data contain a color palette pointer (CPP) and a color palette replacer instruction (CPP31) with respect to each of the planes. The video memory controller reads the palette data and bitmap data from the video memory in accordance with addresses designated by the header data. The color palette replacer signal generator generates a color palette replacer signal (COL) based on the header data so as to make determination whether to replace contents of color palettes with respect to the planes respectively.Type: GrantFiled: March 29, 2001Date of Patent: May 24, 2005Assignee: Yamaha CorporationInventor: Toru Sasaki
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Patent number: 6885377Abstract: An image data output control apparatus for enhancing a screen update speed to naturally update a screen is provided. The image data output control apparatus comprises first and second memories each for buffering image data of one screen, a host processor for selecting the first and second memories alternately as a display buffer for output of image data of a current screen and a screen buffer for storage of image data of a subsequent new screen, writing the image data of the subsequent screen into the screen buffer to construct the subsequent screen, and outputting the image data of the current screen stored in the display buffer. An output terminal outputs image data from any one of the first and second memories as image data for a screen to be displayed through a display unit.Type: GrantFiled: October 23, 2002Date of Patent: April 26, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Chae-Whan Lim, Soon-Jin Kim
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Patent number: 6833832Abstract: A controller (15) for a display system (10) that uses a spatial light modulator (15) to display data formatted in bit-planes. The controller (15) receives at least some of the bit-plane data from a frame memory. It has local memory that buffers data transfer and stores data for bit-planes having multiple accesses, thereby increasing the bandwidth of data transfers from the frame memory (14) to the SLM (16).Type: GrantFiled: December 31, 2001Date of Patent: December 21, 2004Assignee: Texas Instruments IncorporatedInventor: Gary S. Wolverton
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Patent number: 6806882Abstract: The image formation apparatus comprises a plurality of hard disk drives which store image data and a hard disk drive array control integrated circuit which controls reading/writing of image data from/into the hard disk drives. The hard disk drive array control integrated circuit executes setting of parameters, issuance of commands, and reading of statuses for all the hard disk drives substantially at the same time, divides the image data into pieces, and executes direct memory access transfer of the pieces of the image data to the hard disk drives substantially at the same time.Type: GrantFiled: March 20, 2002Date of Patent: October 19, 2004Assignee: Ricoh Company, Ltd.Inventor: Yoshimichi Kanda
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Patent number: 6791555Abstract: A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.Type: GrantFiled: June 23, 2000Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventors: William Radke, James R. Peterson
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Publication number: 20040160449Abstract: A video memory manager manages and virtualizes memory so that an application or multiple applications can utilize both system memory and local video memory in processing graphics. The video memory manager allocates memory in either the system memory or the local video memory as appropriate. The video memory manager may also manage the system memory accessible to the graphics processing unit via an aperture of the graphics processing unit. The video memory manager may evict memory from the local video memory as appropriate, thereby freeing a portion of local video memory use by other applications. In this manner, a graphics processing unit and its local video memory may be more readily shared by multiple applications.Type: ApplicationFiled: December 30, 2003Publication date: August 19, 2004Applicant: Microsoft CorporationInventors: Anuj B. Gossalia, Steve Pronovost, Bryan Langley
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Publication number: 20040160448Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.Type: ApplicationFiled: February 10, 2004Publication date: August 19, 2004Inventor: Joseph Jeddeloh
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Patent number: 6771270Abstract: The present invention provides a variable-width object builder for use in a graphics memory system of a computer graphics display system. The ratio of tile size to object size is variable. The tile size to object size ratio for the object builder can be 1:1 or greater. The frame buffer controller of the graphics memory system preferably comprises three memory controllers. The object builder preferably outputs either two 32-bit words or two 24-bit words. The object builder preferably utilizes a general purpose object building algorithm that eliminates stalls in the incoming stage of the object builder, thereby eliminating the potential for wasted states at the output of the object builder. A side effect of reducing the complexity of the object building algorithm is that a variety of tile and object sizes can be accommodated. The ratio of tile size to object size can range from 1 to 2 without any significant change in architecture, and higher ratios can be accommodated by adding additional backup registers.Type: GrantFiled: October 26, 2000Date of Patent: August 3, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventor: Jason Kassoff
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Patent number: 6750876Abstract: A programmable display controller for use in a digital imaging system has a video control register, a data access controller and a programmable modulator. The programmable display control is designed to be used with a digital imaging systems, such as digital cameras, having a variety of display different devices that require respective different control signals, different image signal modulations, and so on. The video control register stores video mode bits indicating the type of video signal to output. The data access controller has a buffer for requesting image data and storing the requested image data in the buffer. The programmable modulator, in response to the video mode bits, generates a video signal from the image data stored in the buffer. In some embodiments, a decoder detects and decodes a link code in received image data. An address generator is responsive to the decoder and outputs a link address corresponding to the decoded link code for fetching image data that is stored at the link address.Type: GrantFiled: November 9, 1998Date of Patent: June 15, 2004Assignee: ESS Technology, Inc.Inventors: Sean R. Atsatt, William S. Jacobs
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Method of implementing an accelerated graphics port for a multiple memory controller computer system
Patent number: 6741254Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.Type: GrantFiled: November 27, 2000Date of Patent: May 25, 2004Assignee: Micron Technology, Inc.Inventor: Joseph Jeddeloh -
Patent number: 6717582Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.Type: GrantFiled: June 26, 2001Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventor: Joseph Jeddeloh
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Patent number: 6712476Abstract: A projection display apparatus which display a projected image and may be free from connection with a computer. The projection display apparatus carries out processing with information stored in a portable memory and includes a memory controller that reads out the information stored in the portable memory; an image processing section that prepares display image data. The display image data represents an image to be displayed from the image data stored in the portable memory according to an instruction of a processing program that is read from the portable memory and represents a series of processing steps to be executed by the projection display apparatus. An electro-optic device then forms image light in response to the display image data, and an optical system projects the image light to display the image.Type: GrantFiled: November 17, 2000Date of Patent: March 30, 2004Assignee: Seiko Epson CorporationInventors: Takafumi Ito, Shoichi Akaiwa