Memory Allocation Patents (Class 345/543)
  • Patent number: 9448930
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: September 20, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 9420022
    Abstract: A client media application sends a first request for a first chunk of a particular media stream. In response to the request, the client media application begins receiving data packets associated with the requested first chunk of the particular media stream. The data packets are received through a socket having a buffer. Rather than waiting until all of the data packets associated with the first chunk of the particular media stream have been read from the buffer by the client media application before sending a request for a second chunk of the particular media stream, the client media application monitors the amount of data that has been received compared to an expected amount of data, and sends the second request when it determines that the amount of data remaining to be received is less than the size of the buffer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: August 16, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pradip K Fatehpuria, Zhefeng (Jeff) Du
  • Patent number: 9396243
    Abstract: In one aspect, a method includes sending a first short hash handle and a first identity bit associated with the first short hash handle to a replication site, determining if a second hash handle is identical to the first short hash handle, determining if a second identity bit associated with the second short hash handle at the replication is set if the second short hash handle is identical to the first short hash handle and using the second hash handle to identify the data if the second identity bit being is set. The first short hash handle is an identifier of data stored on a disk.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: July 19, 2016
    Assignee: EMC Corporation
    Inventors: Ido Halevi, David Meiri
  • Patent number: 9342322
    Abstract: A method for tile-based rendering of content. Content may be rendered in a memory region organized as multiple tiles. In scenarios in which content is generated in layers, for operations that involve compositing image layers, an order in which portions of the image are processed may be selected to reduce the aggregate number of memory accesses times, which in turn may improve the performance of a computer that uses tile-based rendering. An image may be processed such that operations relating to rendering portions of different layers corresponding to the same tile are performed sequentially. Such processing may be used in a computer with a graphics processing unit that supports tile-based rendering, and may be particularly well suited for computers with a slate form factor. An interface to a graphics processing utility within the computer may provide a flag to allow an application to specify whether operations may be reordered.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: May 17, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Blake D. Pelton, Amar Patel, Steve Pronovost
  • Patent number: 9336056
    Abstract: Embodiments include methods, systems and computer program products for providing an extendable job structure for executing instructions on an accelerator. The method includes creating a number of data descriptor blocks, each having a fixed number of memory location addresses and a pointer to a next of the number of the data descriptor block. The method further includes creating a last data descriptor block having the fixed number of memory location addresses and a last block indicator. Based on determining that additional memory is required for executing instructions on the accelerator, the method includes modifying the last data descriptor block to become a data extender block having a pointer to one of one or more new data descriptor blocks and creating a new last data descriptor block.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh W. Asaad, Parijat Dube, Hong Min, Donald W. Schmidt, Bharat Sukhwani, Mathew S. Thoennes
  • Patent number: 9323684
    Abstract: Technologies are presented that allow a portion of a cache to be used as a front memory when there is dynamic need based on system demand. A computing system may include at least one processor, a memory controlled by a controller and communicatively coupled with the at least one processor, a cache communicatively coupled with the at least one processor and the memory, and mapping logic communicatively coupled with the at least one processor, the memory, and the cache. The mapping logic may map a portion of the cache to a portion of the memory, wherein the portion of the cache is to be used by the at least one processor as a local memory, and wherein the mapping is dynamic based on system demand and managed by the controller in a physical address domain.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Altug Koker, Aditya Navale
  • Patent number: 9219926
    Abstract: An image processing apparatus according to the present invention includes, a division unit configured to divide an image to generate a first block group including one or more blocks and a second block group adjacent to the first block group, a first encoding unit to encode the first block group in units of block, a second encoding unit to encode the second block group in units of block, and a storage unit to store encoded information after the first encoding unit processes a block at a predetermined position, in which the storage unit, when the first block group does not include a block at the predetermined position, sets the predetermined position to a block in the first block group and stores the encoded information based on the set position, and wherein the second encoding unit starts encoding based on the encoded information.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 22, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Koji Okawa
  • Patent number: 9208602
    Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 8, 2015
    Assignee: INTEL CORPORATION
    Inventors: Rahul P. Sathe, Tim Foley
  • Patent number: 9202007
    Abstract: A method for providing documentation and/or annotation capabilities for volumetric data may include receiving an indication of user insertion of an annotation with respect to a particular presentation state of a planar view of volumetric data and generating a medical image such as a DICOM image corresponding to the particular presentation state and including the annotation in response to receipt of the indication. A corresponding computer program product and apparatus are also provided.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 1, 2015
    Assignee: McKesson Financial Holdings
    Inventors: Allan Noordvyk, Leonard Yan, Cristian Stegaru, Radu Catalin Bocirnea, Monica Paul, Gillian Lo
  • Patent number: 9197933
    Abstract: A display apparatus is provided. The display apparatus includes a signal processor which processes a broadcast signal; an application executor which executes at least one application; a storage which stores a code command to change a use of a memory area, the storage including a first memory area allocated for processing the broadcast signal and a second memory area allocated for execution of the application; and a controller which, if the application is executed, changes, based on the code command, the first memory area to an area for execution of the application.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 24, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chung-ki Woo
  • Patent number: 9111325
    Abstract: The graphics processing technique includes detecting a transition from rendering graphics on a first graphics processing unit to a second graphics processing, by a hybrid driver. The hybrid driver, in response to detecting the transition, configures the first graphics processing unit to create a frame buffer. Thereafter, an image rendered on the second graphics processing unit may be copied to the frame buffer of the first graphics processing unit. The rendered image in the frame buffer may then be scanned out on the display.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 18, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Franck Diard
  • Patent number: 9087394
    Abstract: A new hardware architecture defines an indexing and encoding method for accelerating incoherent ray traversal. Accelerating multiple ray traversal may be accomplished by organizing the rays for minimal movement of data, hiding latency due to external memory access, and performing adaptive binning. Rays may be binned into coarse grain and fine grain spatial bins, independent of direction.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: July 21, 2015
    Assignee: Raycast Systems, Inc.
    Inventor: Alvin D. Zimmerman
  • Patent number: 9053752
    Abstract: Systems and methods for layering a graphics plane on top of a compressed video signal are disclosed herein. A processed video stream is received from a video processing path, wherein the processed video stream comprises a stream of video macroblocks. A graphics plane is received from a graphics processing path, wherein the graphics plane comprises a set of graphics macroblocks. The graphics plane is layered on top of the processed video stream to generate an output video stream. Layering comprises blending a video macroblock from the stream of video macroblocks with a graphics macroblock from the set of graphics macroblocks. By layering one macroblock at time, graphics overlay can occur in real time or faster than real time as the compressed input stream is received.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: June 9, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Anthony D. Masterson
  • Publication number: 20150130825
    Abstract: A method for computing eigenvectors and eigenvalues of a square matrix in a high performance computer involves dynamically reallocating the computer's computing cores for various phases of the computation process.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 14, 2015
    Inventor: Cheng Liao
  • Publication number: 20150109314
    Abstract: There is provided a method and apparatus for managing memory in a system for generating 3-dimensional computer images. The image is subdivided into a plurality of rectangular areas. A memory is provided and a page of the memory is allocated for storing object data for objects in the image. Object data for objects in the image are then written to the allocated page of memory. Finally, a bit mask for the allocated page of memory is compiled, the bit mask indicating the rectangular areas having object data stored in the allocated page of memory. A rectangular area of the image can then be rendered by deriving data for display from the object data stored in the memory, for objects in that rectangular area. Once the rectangular area has been rendered, the bit mask for each page of memory which stored, before the step of rendering, object data for that rectangular area, is updated so that the bit mask no longer indicates that rectangular area.
    Type: Application
    Filed: September 11, 2014
    Publication date: April 23, 2015
    Inventor: Jonathan Redshaw
  • Patent number: 9013473
    Abstract: A graphic processing unit (GPU) and method for decompressing compressed 3-dimensional (3D) compressed data. The GPU may extract segment information by analyzing a compressed data header and decompress segments included in a bit stream based on the segment information.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Su Ahn, Do Kyoon Kim, Tae Hyun Rhee
  • Patent number: 9007387
    Abstract: A drawing processing apparatus is disclosed. A graphic index of a graphic included in a display screen or graphic description information which includes a setting parameter to be applied to the graphic is determined for each of regions dividing the display screen. A data size of the graphic description information is aggregated for the regions. A start address in a memory is determined to store the graphic description information into a successive storage area in the memory, based on the aggregated data size. The data size of an area of an overflow occurrence target is stored when the overflow occurs. The graphic description information of the regions is successively written from the start address when the overflow does not occur. A write process is stopped, and resumed from the area of the overflow occurrence target by using the data size when the overflow occurs.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Fujitsu Limited
    Inventor: Yasushi Sugama
  • Publication number: 20150091924
    Abstract: A method for sharing memory between a central processing unit (CPU) and an input/output (I/O) device of a computing device is described. The method may include creating an allocation of memory for the I/O device to operate on. The method includes detecting whether the allocation is not page-aligned, wherein an allocation is page-aligned when its base address and size be evenly divisible by the applicable page-size. The allocation may be successfully shared, even if not page-aligned, even if an operating system of the computing device doesn't support sharing of non-page-aligned allocations.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Jayanth Rao, Pavan Lanka, Ronald Silvas
  • Patent number: 8994740
    Abstract: A cache line allocation method, wherein the cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a plurality of instructions the method comprising the steps of: putting the plurality of instructions in whole cache lines; locking the whole cache lines if an instruction size is less than a cache size; locking a first number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is less than or equal to a threshold; and locking a second number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is large than the threshold; wherein the first number is greater than the second number.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: March 31, 2015
    Assignee: VIA Technologies, Inc.
    Inventors: Bingxu Gao, Xian Chen
  • Publication number: 20150084974
    Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Eric B. LUM, Cass W. EVERITT, Henry Packard MORETON, Yury Y. URALSKY, Cyril CRASSIN, Jerome F. DULUK, Jr.
  • Publication number: 20150070370
    Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 12, 2015
    Inventors: Steve Pronovost, Maxwell Abernethy, Rudolph Balaz, Ameet Chitre
  • Patent number: 8941675
    Abstract: A device, system and method are provided for managing memory for rendering webpages and other structured documents that contain multiple regions. A backing store is created in memory for storing rendered document content. A main region of the structured document is rendered for display, divided into a set of tiles, and stored in the backing store. A subregion of the document is rendered and stored as tiles in the same backing store as well. At least a portion of the tiles for the main region and subregion intersecting with corresponding viewports are outputted to a display. When an active one of the viewports is changed and additional content of the document is to be rendered for display, tiles in the backing store used to store rendered but undisplayed data for the inactive viewport are released to store new rendered content for the active viewport.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: January 27, 2015
    Assignee: BlackBerry Limited
    Inventors: Adam Chester Treat, Eli Joshua Fidler, Antonio Gomes Araujo Netto
  • Patent number: 8938599
    Abstract: In a method of implementing a graph storage system, the graph storage system is stored on a plurality of computing systems. A global address space is provided for distributed graph storage. The global address space is managed with graph allocators, in which a graph allocator allocates space from a block of the distributed global memory in order to store a plurality of graphs.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: January 20, 2015
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Michael Mihn-Jong Lee, Indrajit Roy, Vanish Talwar, Alvin AuYoung, Parthasarathy Ranganathan
  • Patent number: 8928680
    Abstract: A program module executing in a first process space of a mobile computing device receives a buffer request from a graphics driver running in a second process space of the mobile computing device, wherein the second process space is isolated from the first process space. The program module assigns a buffer to the graphics driver to store image data processed by a graphical processing unit (GPU) controlled by the graphics driver. The program module receives a release of the buffer from the graphics driver. The program module assigns the buffer to a media encoder driver for a hardware media encoder to encode the image data in the buffer into a file.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: January 6, 2015
    Assignee: Google Inc.
    Inventors: Pannag Raghunath Sanketi, Jamie Gennis
  • Patent number: 8922712
    Abstract: In an embodiment, there is provided a video processing component comprising a compensation engine configured to generate pixels of a first video frame from a second video frame based at least in part on specified pixel motion; and an access buffer configured to store pixel data corresponding to pixels of the second video frame for reference by the compensation engine, wherein the pixel data is stored by the access buffer at different vertical resolutions depending on vertical distances of the pixels corresponding to the pixel data from a target pixel that is indicated by the compensation engine.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: December 30, 2014
    Assignee: Marvell International Ltd.
    Inventor: Vipin Namboodiri
  • Patent number: 8924677
    Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: December 30, 2014
    Assignee: Microsoft Corporation
    Inventors: Steve Pronovost, Maxwell Abernethy, Rudolph Balaz, Ameet Chitre
  • Patent number: 8923405
    Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: December 30, 2014
    Assignee: Ambarella, Inc.
    Inventors: Ellen M. Lee, Yat Kuen Wong
  • Patent number: 8917279
    Abstract: A system for dynamically binding and unbinding of graphics processing unit GPU applications, the system includes a memory management for tracking memory of a GPU used by an application, and a source-to-source compiler for identifying nested structures allocated on the GPU so that the virtual memory management can track these nested structures, and identifying all instances where nested structures on the GPU are modified inside kernels.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: December 23, 2014
    Assignee: NEC Laboratories America, Inc.
    Inventors: Michela Becchi, Kittisak Sajjapongse, Srimat T. Chakradhar
  • Patent number: 8907964
    Abstract: A system to process a plurality of vertices to model an object. An embodiment of the system includes a processor, a front end unit coupled to the processor, and cache configuration logic coupled to the front end unit and the processor. The processor is configured to process the plurality of vertices. The front end unit is configured to communicate vertex data to the processor. The cache configuration logic is configured to establish a cache line size of a vertex cache based on a vertex size of a drawing command.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: December 9, 2014
    Assignee: Vivante Corporation
    Inventors: Keith Lee, Mike M. Cai
  • Publication number: 20140313213
    Abstract: A memory apparatus may include a tile generator configured to generate a plurality of tiles by dividing a plurality of pixels constituting input data based on a predetermined pixel unit, and a tile storage configured to store the plurality of tiles by sequentially enumerating luminance information and chrominance information about pixels included in the plurality of tiles.
    Type: Application
    Filed: November 19, 2013
    Publication date: October 23, 2014
    Applicants: Industry-Academia Cooperation Group Of Sejong University, Samsung Electronics Co., Ltd.
    Inventors: Won Chang LEE, Gi Ho Park, Do Hyung Kim, Shi Hwa Lee, Seong Uk Jeong
  • Publication number: 20140313214
    Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 23, 2014
    Applicant: Apple Inc.
    Inventors: Aaftab A. Munshi, Ian R. Ollmann
  • Patent number: 8860739
    Abstract: Disclosed is a method of processing a digital representation comprising a plurality of cells having respective cell values and being arranged in a regular grid. The method comprises performing at least one cell data reordering operation and performing at least one arithmetic operation for computing at least a first cell value of a first cell from one or more cell values of respective cells of the digital representation, each arithmetic operation including at least one multiplication. The method comprises performing the at least one reordering operation and the at least one arithmetic operation as at least two concurrent processes, each of the concurrent processes reading respective parts of the digital representation from respective memory buffers of a shared memory.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: October 14, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Jordan Vitella-Espinoza
  • Patent number: 8860740
    Abstract: A computing machine includes a virtual machine monitor and a display adapter. The virtual machine monitor receives a graphics device interface (GDI) instruction including display content information and virtual machine identification information from a virtual machine, obtains video memory identification information by querying a correspondence between the virtual machine identification information and the video memory identification information, and sends a display driver message including the display content information and the video memory identification information to the display adapter. The display adapter receives the display driver message, stores the display content information in a video memory in the display adapter according to the video memory identification information, and sends the display driver message to a client terminal via a network interface card in the display adapter.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Hao Zhang
  • Patent number: 8854388
    Abstract: An image processing apparatus has a plurality of functions and is capable of executing a job relating to any of the plurality of functions. The image processing apparatus includes a memory management unit to secure a storage region in a first storage device for program execution, a save unit to save information from the storage region in the first storage device to a second storage device, a history recording unit to record a history relating to execution of the job each time the image processing apparatus executes the job, and a save restriction unit to restrict saving of information from the storage region in the first storage device to the second storage device in order to execute a job relating to a function which is specified based on a job history recorded by the history recording unit from among the plurality of functions.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: October 7, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akira Ishikawa
  • Publication number: 20140267334
    Abstract: One embodiment of the present invention includes techniques for a first processing unit to perform an atomic operation on a memory page shared with a second processing unit. The memory page is associated with a page table entry corresponding to the first processing unit. Before executing the atomic operation, an MMU included in the first processing unit evaluates an atomic permission bit that is included in the page table entry. If the MMU determines that the atomic permission bit is inactive, then the two processing units coordinate to change the permission status of the memory page. As part of the status change, the atomic permission bit in the page table entry is activated. Subsequently, the first processing unit performs the atomic operation uninterrupted by the second processing unit. Advantageously, coordinating the processing unit via the atomic permission bit ensures the proper and efficient execution of the atomic operation.
    Type: Application
    Filed: August 27, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jerome F. DULUK, JR., John MASHEY, Mark HAIRGROVE, James Leroy DEMING, Cameron BUSCHARDT, Brian FAHS
  • Patent number: 8836700
    Abstract: A method, system, and computer program product are disclosed for providing tessellated primitive data to a geometry shader. The method comprises computing a set of tessellated vertices and a computed set of connectivity data based on an original set of vertices and an original set of connectivity data, generating computed vertex data based on the original set of vertices and the set of tessellated vertices, receiving the computed set of connectivity data, requesting a subset of the computed vertex data based on the computed set of connectivity data, and processing primitives defined by the subset of the computed vertex data. The system and computer program product are further disclosed for accomplishing a similar result as the aforementioned method.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Vineet Goel
  • Patent number: 8823720
    Abstract: Methods, systems and data structures produce a rasterizer. A graphical state is detected on a machine architecture. The graphical state is used for assembling a shell rasterizer. The machine architecture is used for selecting replacement logic that replaces portions of shell logic in the shell rasterizer. The machine architecture is used for selectively inserting memory management logic into portions of the shell logic to produce.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: September 2, 2014
    Assignee: Intel Corporation
    Inventors: William A. Hux, Stephen Junkins
  • Publication number: 20140240335
    Abstract: System and method for operating a solid state memory containing a memory space. The present invention provides a computerized system that includes a solid state memory having a memory space; a controller adapted to use a first portion of the memory space as a cache; and a garbage collector adapted to use a second portion of the memory space to collect garbage in the solid state memory. The controller is adapted to change a size of at least one of the first portion and the second portion of the memory space during operation of the solid state memory.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: International Business Machines Corporation
    Inventors: Xiao-Yu Hu, Nikolas Ioannou, Ioannis Koltsidas
  • Patent number: 8817033
    Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Young Hur, Sang woo Rhim, Beom Hak Lee
  • Patent number: 8810588
    Abstract: Provided is a display switching apparatus that reduces delayed display, and the like, of frame images. An information processing terminal 1 is provided with a first rendering component 61 that, in each first time interval, generates and writes an image to a buffer, a second rendering component 62 that, in each second time interval, generates and writes an image to a buffer, a frame buffer management unit 11 that allocates a high-speed frame buffer 31 on a high-speed memory device 18 and a universal frame buffer 32 on a universal memory device 19, and a display switching apparatus 12 that includes a switching determination unit 81 that repeatedly calculates a rendering load for each rendering component and a switching performance unit 82 that switches the buffers allocated to the rendering components when the high-speed frame buffer 31 is not allocated to the rendering component with the higher rendering load.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventor: Kazutoshi Kashimoto
  • Patent number: 8806325
    Abstract: Methods and apparatuses that identify one of a plurality of modes from a web page associated with a document received at a browser are described. An identified mode may correspond to a user interface configuration. A portion of content may be extracted from the document for a presentation configured by the user interface configuration. A presentation of the extracted content may be displayed on a display screen while excluding a reset of the document without displaying the web page.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: August 12, 2014
    Assignee: Apple Inc.
    Inventors: Kevin Decker, Giovanni Donelli
  • Patent number: 8797815
    Abstract: A measuring device for the efficient storage of test values and associated addresses provides a first storage region (30) and a second storage region (33). The first storage region (30) comprises a first number of memory cells (32) of a first cell size (31). The second storage region (33) comprises a second number of memory cells (35) of a second cell size (34). The measuring device further provides a third storage region (36) made from a second number of memory cells (38). A memory cell (38) of the third storage region (36) is rigidly assigned to each memory cell (35) of the second storage region (33).
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: August 5, 2014
    Assignee: Rohde & Schwarz GmbH & Co. Kg
    Inventor: Andrew Schaefer
  • Publication number: 20140204106
    Abstract: A system, method, and computer program product are provided for determining a size of an attribute storage buffer. Input attributes read by a shader program to generate output attributes are identified. A portion of the output attributes to be consumed by a destination shader program is identified. The size of the attribute storage buffer that is allocated for execution of the shader program is computed based on the input attributes and the portion of the output attributes.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ziyad Sami Hakura, Emmett M. Kilgariff
  • Patent number: 8786620
    Abstract: Memory storage and processing for idle computer-generated graphical display components are discarded for conserving memory capacity, processing resources and power consumption. If a computer-generated display frame goes idle for a prescribed duration, for example, 30 seconds, wherein no user action or processor action is performed on the idle display frame, stored data representing the idle display frame is discarded from memory and processing for the idle display component is ceased, thus conserving memory space, processing resources and power consumption (e.g., battery power). If the discarded display frame becomes active again, its discarded resources may be recreated. Alternatively, an idle display component may be passed to a separate application and may be reclaimed by a requiring application when the idle display component becomes active again.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 22, 2014
    Assignee: Microsoft Corporation
    Inventors: Tyler Robert Adams, Michael Ivan Borysenko, Warren Leung, Barry Christopher Allyn
  • Patent number: 8781297
    Abstract: A method for providing a content entity from a storage disc is described. The storage disc comprises at least one further content entity. Each content entity comprises a main menu and at least one submenu accessible via the main menu. The storage disc further comprises an entity selection menu. The entity selection menu comprises a link to the main menu of the content entity to be provided. The method comprises providing the entity selection menu for reproduction, receiving a selection of the content entity to be provided, detecting that the storage disc comprises a plurality of content entities, mapping a pre-defined start address to a different start address and providing the selected content entity for reproduction based on the different start address. The pre-defined start address is mapped to a different start address of the storage disc associated with the main menu of the selected content entity to be provided.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 15, 2014
    Assignee: Nero AG
    Inventor: Richard Lesser
  • Patent number: 8780114
    Abstract: An embodiment can include an interactive memory map that includes a graphical representation of a region of memory used by a program. The memory map may dynamically update as the program executes and may provide a user with indicators that identify how the program interacts with the memory. The indicators may identify memory locations that are being written by the program and/or memory locations that are being read by the program while the program executes. The memory map may assist a user in understanding how the executing program interacts with memory. The interactive memory map may further allow the user to manipulate how information is stored in the memory by allowing the user to select, add, remove, modify, move, etc., program information stored in the memory.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: July 15, 2014
    Assignee: The MathWorks, Inc.
    Inventors: Robyn Arthur Jackey, Arvind Suresh Hosagrahara
  • Patent number: 8760460
    Abstract: One embodiment of the present invention sets forth a technique for using a shared memory to store hardware-managed virtual buffers. A circular buffer is allocated within a general-purpose multi-use cache for storage of primitive attribute data rather than having a dedicated buffer for the storage of the primitive attribute data. The general-purpose multi-use cache is also configured to store other graphics data sinces the space requirement for primitive attribute data storage is highly variable, depending on the number of attributes and the size of primitives. Entries in the circular buffer are allocated as needed and released and invalidated after the primitive attribute data has been consumed. An address to the circular buffer entry is transmitted along with primitive descriptors from object-space processing to the distributed processing in screen-space.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: June 24, 2014
    Assignee: NVIDIA Corporation
    Inventors: Emmett M. Kilgariff, Steven E. Molnar, Sean J. Treichler, Johnny S. Rhoades, Gernot Schaufler, Dale L. Kirkland, Cynthia Ann Edgeworth Allison, Karl M. Wurstner, Timothy John Purcell
  • Publication number: 20140152681
    Abstract: A rendering apparatus acquires graphic information of a figure to be rendered in a rendering area; specifies for each division area of the rendering area, graphic information of a figure to be rendered in the division area; calculates based on data size of the specified graphic information and for each division area, total data size of graphic information of the figure to be rendered in the division area; selects a division area as a rendering destination, based on each calculated total data size and a data capacity of a memory area to which graphic information is to be stored that is among the acquired graphic information and for the figure to be rendered; writes to the memory area, the graphic information of the figure to be rendered in the selected division area; and generates based on the written graphic information, an image for the selected division area.
    Type: Application
    Filed: November 21, 2013
    Publication date: June 5, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Yasushi SUGAMA
  • Patent number: 8743129
    Abstract: The present invention relates to a display device for a glass cockpit of an aircraft, intended to provide video streams to a plurality of viewing screens of said glass cockpit, said aircraft being partitioned into a secured area, a so-called avionic world (AW), and a non-secured area, a so-called open world (OW), said system comprising at least one first port intended to receive first data to be displayed from a system (210, 310, 410) belonging to the avionic area and at least one second port intended to receive second data to be displayed from a system (220, 320, 420) belonging to the open world, the display device comprising: predetermined hardware resources allocated to the processing of the second data; a processor (241, 341, 441), belonging to the avionic area, adapted to controlling the hardware resources used by said processing and interrupting this processing if said hardware resources used exceed said allocated resources.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: June 3, 2014
    Assignee: Airbus Operations S.A.S.
    Inventors: Lionel Cheymol, Vincent Foucart, Simon Innocent
  • Patent number: 8723860
    Abstract: There are provided methods and apparatus for generating a 3-dimensional computer image. The image includes a number of objects and is divided into separate areas. Control data to link to object data stored in a memory for each object is derived for two objects at a time. Two or more separate areas can be processed in parallel by deriving control data for the two separate areas at a time. To avoid fetching data for both areas, which is actually only applicable to one area, encoding is used in the control data. The object data can be stored on one or across two memory pages, and the control data includes one memory page address in the former case and two memory page addresses in the latter case. The object data can also be stored across two non-contiguous memory pages, by using a look-up table with contiguous portions allocated for each object's object data.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: May 13, 2014
    Assignee: Imagination Technologies, Ltd.
    Inventors: Jonathan Redshaw, Xile Yang