Memory Allocation Patents (Class 345/543)
  • Patent number: 8823720
    Abstract: Methods, systems and data structures produce a rasterizer. A graphical state is detected on a machine architecture. The graphical state is used for assembling a shell rasterizer. The machine architecture is used for selecting replacement logic that replaces portions of shell logic in the shell rasterizer. The machine architecture is used for selectively inserting memory management logic into portions of the shell logic to produce.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: September 2, 2014
    Assignee: Intel Corporation
    Inventors: William A. Hux, Stephen Junkins
  • Publication number: 20140240335
    Abstract: System and method for operating a solid state memory containing a memory space. The present invention provides a computerized system that includes a solid state memory having a memory space; a controller adapted to use a first portion of the memory space as a cache; and a garbage collector adapted to use a second portion of the memory space to collect garbage in the solid state memory. The controller is adapted to change a size of at least one of the first portion and the second portion of the memory space during operation of the solid state memory.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: International Business Machines Corporation
    Inventors: Xiao-Yu Hu, Nikolas Ioannou, Ioannis Koltsidas
  • Patent number: 8817033
    Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Young Hur, Sang woo Rhim, Beom Hak Lee
  • Patent number: 8810588
    Abstract: Provided is a display switching apparatus that reduces delayed display, and the like, of frame images. An information processing terminal 1 is provided with a first rendering component 61 that, in each first time interval, generates and writes an image to a buffer, a second rendering component 62 that, in each second time interval, generates and writes an image to a buffer, a frame buffer management unit 11 that allocates a high-speed frame buffer 31 on a high-speed memory device 18 and a universal frame buffer 32 on a universal memory device 19, and a display switching apparatus 12 that includes a switching determination unit 81 that repeatedly calculates a rendering load for each rendering component and a switching performance unit 82 that switches the buffers allocated to the rendering components when the high-speed frame buffer 31 is not allocated to the rendering component with the higher rendering load.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventor: Kazutoshi Kashimoto
  • Patent number: 8806325
    Abstract: Methods and apparatuses that identify one of a plurality of modes from a web page associated with a document received at a browser are described. An identified mode may correspond to a user interface configuration. A portion of content may be extracted from the document for a presentation configured by the user interface configuration. A presentation of the extracted content may be displayed on a display screen while excluding a reset of the document without displaying the web page.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: August 12, 2014
    Assignee: Apple Inc.
    Inventors: Kevin Decker, Giovanni Donelli
  • Patent number: 8797815
    Abstract: A measuring device for the efficient storage of test values and associated addresses provides a first storage region (30) and a second storage region (33). The first storage region (30) comprises a first number of memory cells (32) of a first cell size (31). The second storage region (33) comprises a second number of memory cells (35) of a second cell size (34). The measuring device further provides a third storage region (36) made from a second number of memory cells (38). A memory cell (38) of the third storage region (36) is rigidly assigned to each memory cell (35) of the second storage region (33).
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: August 5, 2014
    Assignee: Rohde & Schwarz GmbH & Co. Kg
    Inventor: Andrew Schaefer
  • Publication number: 20140204106
    Abstract: A system, method, and computer program product are provided for determining a size of an attribute storage buffer. Input attributes read by a shader program to generate output attributes are identified. A portion of the output attributes to be consumed by a destination shader program is identified. The size of the attribute storage buffer that is allocated for execution of the shader program is computed based on the input attributes and the portion of the output attributes.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ziyad Sami Hakura, Emmett M. Kilgariff
  • Patent number: 8786620
    Abstract: Memory storage and processing for idle computer-generated graphical display components are discarded for conserving memory capacity, processing resources and power consumption. If a computer-generated display frame goes idle for a prescribed duration, for example, 30 seconds, wherein no user action or processor action is performed on the idle display frame, stored data representing the idle display frame is discarded from memory and processing for the idle display component is ceased, thus conserving memory space, processing resources and power consumption (e.g., battery power). If the discarded display frame becomes active again, its discarded resources may be recreated. Alternatively, an idle display component may be passed to a separate application and may be reclaimed by a requiring application when the idle display component becomes active again.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 22, 2014
    Assignee: Microsoft Corporation
    Inventors: Tyler Robert Adams, Michael Ivan Borysenko, Warren Leung, Barry Christopher Allyn
  • Patent number: 8780114
    Abstract: An embodiment can include an interactive memory map that includes a graphical representation of a region of memory used by a program. The memory map may dynamically update as the program executes and may provide a user with indicators that identify how the program interacts with the memory. The indicators may identify memory locations that are being written by the program and/or memory locations that are being read by the program while the program executes. The memory map may assist a user in understanding how the executing program interacts with memory. The interactive memory map may further allow the user to manipulate how information is stored in the memory by allowing the user to select, add, remove, modify, move, etc., program information stored in the memory.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: July 15, 2014
    Assignee: The MathWorks, Inc.
    Inventors: Robyn Arthur Jackey, Arvind Suresh Hosagrahara
  • Patent number: 8781297
    Abstract: A method for providing a content entity from a storage disc is described. The storage disc comprises at least one further content entity. Each content entity comprises a main menu and at least one submenu accessible via the main menu. The storage disc further comprises an entity selection menu. The entity selection menu comprises a link to the main menu of the content entity to be provided. The method comprises providing the entity selection menu for reproduction, receiving a selection of the content entity to be provided, detecting that the storage disc comprises a plurality of content entities, mapping a pre-defined start address to a different start address and providing the selected content entity for reproduction based on the different start address. The pre-defined start address is mapped to a different start address of the storage disc associated with the main menu of the selected content entity to be provided.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 15, 2014
    Assignee: Nero AG
    Inventor: Richard Lesser
  • Patent number: 8760460
    Abstract: One embodiment of the present invention sets forth a technique for using a shared memory to store hardware-managed virtual buffers. A circular buffer is allocated within a general-purpose multi-use cache for storage of primitive attribute data rather than having a dedicated buffer for the storage of the primitive attribute data. The general-purpose multi-use cache is also configured to store other graphics data sinces the space requirement for primitive attribute data storage is highly variable, depending on the number of attributes and the size of primitives. Entries in the circular buffer are allocated as needed and released and invalidated after the primitive attribute data has been consumed. An address to the circular buffer entry is transmitted along with primitive descriptors from object-space processing to the distributed processing in screen-space.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: June 24, 2014
    Assignee: NVIDIA Corporation
    Inventors: Emmett M. Kilgariff, Steven E. Molnar, Sean J. Treichler, Johnny S. Rhoades, Gernot Schaufler, Dale L. Kirkland, Cynthia Ann Edgeworth Allison, Karl M. Wurstner, Timothy John Purcell
  • Publication number: 20140152681
    Abstract: A rendering apparatus acquires graphic information of a figure to be rendered in a rendering area; specifies for each division area of the rendering area, graphic information of a figure to be rendered in the division area; calculates based on data size of the specified graphic information and for each division area, total data size of graphic information of the figure to be rendered in the division area; selects a division area as a rendering destination, based on each calculated total data size and a data capacity of a memory area to which graphic information is to be stored that is among the acquired graphic information and for the figure to be rendered; writes to the memory area, the graphic information of the figure to be rendered in the selected division area; and generates based on the written graphic information, an image for the selected division area.
    Type: Application
    Filed: November 21, 2013
    Publication date: June 5, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Yasushi SUGAMA
  • Patent number: 8743129
    Abstract: The present invention relates to a display device for a glass cockpit of an aircraft, intended to provide video streams to a plurality of viewing screens of said glass cockpit, said aircraft being partitioned into a secured area, a so-called avionic world (AW), and a non-secured area, a so-called open world (OW), said system comprising at least one first port intended to receive first data to be displayed from a system (210, 310, 410) belonging to the avionic area and at least one second port intended to receive second data to be displayed from a system (220, 320, 420) belonging to the open world, the display device comprising: predetermined hardware resources allocated to the processing of the second data; a processor (241, 341, 441), belonging to the avionic area, adapted to controlling the hardware resources used by said processing and interrupting this processing if said hardware resources used exceed said allocated resources.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: June 3, 2014
    Assignee: Airbus Operations S.A.S.
    Inventors: Lionel Cheymol, Vincent Foucart, Simon Innocent
  • Patent number: 8723860
    Abstract: There are provided methods and apparatus for generating a 3-dimensional computer image. The image includes a number of objects and is divided into separate areas. Control data to link to object data stored in a memory for each object is derived for two objects at a time. Two or more separate areas can be processed in parallel by deriving control data for the two separate areas at a time. To avoid fetching data for both areas, which is actually only applicable to one area, encoding is used in the control data. The object data can be stored on one or across two memory pages, and the control data includes one memory page address in the former case and two memory page addresses in the latter case. The object data can also be stored across two non-contiguous memory pages, by using a look-up table with contiguous portions allocated for each object's object data.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: May 13, 2014
    Assignee: Imagination Technologies, Ltd.
    Inventors: Jonathan Redshaw, Xile Yang
  • Patent number: 8707132
    Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akio Nakagawa, Hisashi Ishikawa
  • Patent number: 8687009
    Abstract: An image processing apparatus for managing a memory device having a plurality of storage areas including a storage area storing out-of-use information and a free area storing no information, the image processing apparatus comprises memory control unit adapted to determine whether or not there is a storage area storing the out-of-use information based on a request for storing information and determining the storage area storing the out-of-use information as an area for storing the information, in a case where the storage area exists; and information writing unit adapted to overwrite generated information to the storage area determined by the memory control unit.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: April 1, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideyuki Kitani
  • Patent number: 8681166
    Abstract: A method according to an embodiment of a system for efficient resource management of a signal flow programmed digital signal processor code is provided and includes determining a connection sequence of a plurality of algorithm elements in a schematic of a signal flow for an electronic circuit, the connection sequence indicating connections between the algorithm elements and a sequence of processing the algorithm elements according to the connections, determining a buffer sequence indicating an order of using the plurality of memory buffers to process the plurality of algorithm elements according to the connection sequence, and reusing at least some of the plurality of memory buffers according to the buffer sequence.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: March 25, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Mohammed Chalil, John Joseph
  • Publication number: 20140063030
    Abstract: Aspects include a pixel source that produces data for a rendered surface divided into regions. A mapping identifies memory segments storing pixel data for each region of the surface. The mapping can identify memory segments storing pixel data from a prior rendered surface, for regions that were unchanged during rendering the rendering. Such changed/unchanged status is tracked on a region by region basis. A counter can be maintained for each memory segments to track how many surfaces use pixel data stored therein. A pool of free memory segments can be maintained. Reading a surface, such as to display a rendered surface by a display controller, includes identifying and reading the mapping to identify each memory segment storing pixel data for regions of the surface, reading such, and updating the counters for the memory segments that were read.
    Type: Application
    Filed: September 2, 2013
    Publication date: March 6, 2014
    Applicant: IMAGINATION TECHNOLOGIES LIMITED
    Inventor: John A. Metcalfe
  • Patent number: 8665283
    Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: March 4, 2014
    Assignee: Ambarella, Inc.
    Inventor: Melvyn Lim
  • Publication number: 20140049551
    Abstract: A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.
    Type: Application
    Filed: August 17, 2012
    Publication date: February 20, 2014
    Applicant: INTEL CORPORATION
    Inventors: Jayanth N. Rao, Ronald W. Silvas, Ankur N. Shah
  • Patent number: 8627036
    Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: January 7, 2014
    Assignee: Microsoft Corporation
    Inventors: Steve Pronovost, Maxwell Abernethy, Rudolph Balaz, Ameet Chitre
  • Patent number: 8619866
    Abstract: A method for processing digital image data is provided that includes compressing a block of the digital image data to generate a compressed block, storing the compressed block in an external memory when a number of bits in the compressed block does not exceed a first compression threshold, and storing the block in the external memory when the number of bits in the compressed block exceeds the first compression threshold.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: December 31, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Minhua Zhou, Ching-Yu Hung
  • Publication number: 20130342552
    Abstract: Various embodiments are presented herein that may allow an application direct access to graphical processing unit memory. An apparatus and a computer-implemented method may include accessing allocated graphical processing unit memory of a second resource via a link from a first resource. The allocated graphical processing unit memory may be mapped into one or more page tables of a central processing unit. A virtual address of the graphical processing unit memory from the one or more page tables of the central processing unit may be sent to the application.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Inventor: Michael Apodaca
  • Patent number: 8610729
    Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: December 17, 2013
    Assignee: Graphic Properties Holdings, Inc.
    Inventors: John M. Airey, Mark S. Peercy, Robert A. Drebin, John Montrym, David L. Dignam, Christopher J. Migdal, Danny D. Loh
  • Patent number: 8610716
    Abstract: Among other disclosure, a computer-implemented method for retaining a surface detail includes identifying a surface that is to be used for generating an image in a rendering process. The surface includes polygons to be changed from an initial size to a larger size as the surface is changed to a lower resolution as part of tessellating the surface. The surface includes at least one surface detail smaller than the larger polygon size. The method includes storing information corresponding to at least a portion of the surface that includes polygons forming the surface detail. The method includes tesselating the surface, wherein the surface assumes the lower resolution. The method includes determining, while the image is at the lower resolution and using the stored information, a shading sample for at least one of the polygons of the larger size that includes the surface detail. The method includes storing the shading sample.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: December 17, 2013
    Assignee: Lucasfilm Entertainment Company Ltd.
    Inventors: Patrick N. P. Conran, Domenico Porcino
  • Patent number: 8610732
    Abstract: A system and method for facilitating access to graphics memory wherein the graphics memory can be shared between a graphics processor and general system application. The method includes detecting an idle state of a graphics processing unit (GPU). The GPU uses graphics memory operable for storing graphics data. The method further includes determining an amount of available memory of the graphics memory of the GPU and signaling an operating system regarding the available memory. Memory data transfers are then received to store data into the available memory of the graphics memory wherein the data is related to general system application. Memory accesses to the available memory of the GPU are translated into a suitable format and executed so that the graphics memory is shared between the GPU and the operating system.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: December 17, 2013
    Assignee: Nvidia Corporation
    Inventor: Rambod Jacoby
  • Patent number: 8605100
    Abstract: A drawing device includes a distinguish unit for distinguishing figure description information in scene data of each figure in a display screen, for tiles included in the display screen; an aggregation unit for aggregating a data size of the figure description information corresponding to the tiles; an address determination unit for determining a leading address in a memory area for storing the figure description information corresponding to each of the tiles, based on an aggregation result of each tile; and a memory write unit for sequentially writing, in the memory area, the figure description information distinguished as corresponding to the tiles, starting from the leading address determined for each corresponding tile, wherein the address determination unit determines the leading addresses so that the memory areas for storing the figure description information corresponding to the tiles are arranged in a physical address space in an order of drawing the tiles.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 10, 2013
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Yasushi Sugama, Masayuki Nakamura
  • Patent number: 8601223
    Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced page table entries are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can redirect one or more pending page table entry fetch requests to an appropriate coalesced page table entry.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: December 3, 2013
    Assignee: Nvidia Corporation
    Inventor: Lingfeng Yuan
  • Publication number: 20130293561
    Abstract: An image data producing apparatus includes: a page dividing portion that divides data described in a page description language into a page unit; a plurality of image processors that form raster data from divided data; and a controlling portion that allocates pages on which the raster data is formed to each of the plurality of the image processors, and causes each of the plurality of the image processors to execute registration of a printing resource on respective pages with at least a change of the printing resource by controlling each of the plurality of the image processors irrespective of a page allocation.
    Type: Application
    Filed: July 8, 2013
    Publication date: November 7, 2013
    Inventor: Takeshi TORII
  • Patent number: 8576258
    Abstract: For improving the brightness decay of a display due to its aging, a non-volatile memory such as Flash can be used to store a brightness accumulation value of each point of the display, and each point can be compensated for its brightness accordingly. However, the non-volatile memory suffers from incorrect write-in data or temporary power disconnection, and thus the error will exist all the time to make the display non-even. Hence, the present invention uses a multiple data backups and CRC error detection, plus new/old data comparison to protect data the non-volatile memory from incorrect brightness compensation value so as to uniform the brightness of the display.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 5, 2013
    Assignee: Holtek Semiconductor Inc.
    Inventors: Tzong-Kwei Chen, Chun-Lin Shen, Yi-Chen Liu, Chen-Ting Kuan
  • Patent number: 8547385
    Abstract: Various systems and methods are described for accessing a shared memory in a graphics processing unit (GPU). One embodiment comprises determining whether data to be read from a shared memory aligns to a boundary of the shared memory, wherein the data comprises a plurality of data blocks, and wherein the shared memory comprises a plurality of banks and a plurality of offsets. A swizzle pattern in which the data blocks are to be arranged for processing is determined. Based on whether the data aligns with a boundary of the shared memory and based on the determined swizzle pattern, an order for performing one or more wrapping functions is determined. The shared memory is accessed by performing the one or more wrapping functions and reading the data blocks to construct the data according to the swizzle pattern.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: October 1, 2013
    Assignee: Via Technologies, Inc.
    Inventor: Yang (Jeff) Jiao
  • Patent number: 8531468
    Abstract: An apparatus for use in image processing is set forth that comprises a pixel processor, context memory, and a context memory controller. The pixel processor is adapted to execute a pixel processing operation on a target pixel using a context of the target pixel. The context memory is adapted to store context values associated with the target pixel. The context memory controller may be adapted to control communication of context values between the pixel processor and the context memory. Further, the context memory controller may be responsive to a context initialization signal or the like provided by the pixel processor to initialize the content of the context memory to a known state, even before the pixel processor has completed its image processing operations and/or immediately after completion of its image processing operations. In one embodiment, the pixel processor executes a JBIG coding operation on the target pixel.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 10, 2013
    Assignee: Marvell International Ltd.
    Inventors: Amit Joshi, Akash Sood, Rakesh Pandey
  • Patent number: 8531471
    Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Hu Chen, Ying Gao, Zhou Xiaocheng, Shoumeng Yan, Peinan Zhang, Mohan Rajagopalan, Jesse Fang, Avi Mendelson, Bratin Saha
  • Patent number: 8531470
    Abstract: A method and an apparatus for maintaining separate information for graphics commands that have been sent to a graphics processing unit (GPU) and for graphics commands that have been processed by the GPU are described. The graphics commands may be associated with graphics resources. A manner to respond to a request for updating the graphics resources may be determined based on examining the separate information maintained for the graphics commands. The request may be received from a graphics API (application programming interface). Responding to the request may include at least one of notifying the graphics API regarding a status of the graphics resources and updating the graphics resources identified by the request.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: September 10, 2013
    Assignee: Apple Inc.
    Inventors: Michael James Elliott Swift, Richard Schreyer
  • Patent number: 8514235
    Abstract: The present disclosure describes implementations for performing register accesses and operations in a graphics processing apparatus. In one implementation, a graphics processing apparatus comprises an execution unit for processing programmed shader operations, wherein the execution unit is configured for processing operations of a plurality of threads. The apparatus further comprises memory forming a register file that accommodates all register operations for all the threads executed by the execution unit, the memory being organized in a plurality of banks, with a first plurality of banks being allocated to a first plurality of the threads and a second plurality of banks being allocated to the remaining threads. In addition, the apparatus comprises address translation logic configured to translate logical register identifiers into physical register addresses.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: August 20, 2013
    Assignee: Via Technologies, Inc.
    Inventor: Yang (Jeff) Jiao
  • Patent number: 8510531
    Abstract: A method for storing information may include determining whether a received data object fits inside a particular one of a plurality of free blocks in a memory bitmap. Each of the plurality of free blocks may include a column of the memory bitmap with a top margin, a bottom margin, and a predetermined width. If the received data object fits, the received data object may be stored in the particular one of the plurality of free blocks, starting at the top margin of the particular one of the plurality of free blocks. The particular one of the plurality of data blocks may be resized by moving the top margin to start below the stored received data object. The determining may include, for each of the plurality of free blocks, a height of the received data object may be compared with a height of each of the free data blocks.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: August 13, 2013
    Assignee: Google Inc.
    Inventors: Chet Haase, Raphael Linus Levien, Romain Guy
  • Patent number: 8502831
    Abstract: Apparatus, methods, and systems are disclosed to manage memory in an embedded system. The system registers video applications and video sources with a memory manager. The memory manager in turn provides memory to the video applications and video sources. The system has an input to receive an output from at least one video source. The memory manager receives a frame from the video source and transfers the frame to memory. Once the frame is in memory the video application may work with the frame. All of these operations are conducted with the memory manager actively managing and allocating the memory resources.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: August 6, 2013
    Assignee: Digi International Inc.
    Inventors: Adam D. Dirstine, Steven L. Halter, David J. Hutchison, Pamela A. Wright, Jeffrey M. Ryan
  • Patent number: 8504791
    Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 6, 2013
    Assignee: Hicamp Systems, Inc.
    Inventors: David R. Cheriton, Alexandre Y. Solomatnikov
  • Patent number: 8493415
    Abstract: A method for processing video data includes performing by one or more processors and/or circuits in a video processing device, the one or more processors and/or circuits including a video scaler, a memory, and a scaler engine, functions including receiving a video image by the video processing device. The functions also include determining whether the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory or after reading the video image from the memory, and scaling the video image based on the determination. If the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory, performing by the one or more processors and/or circuits scaling of the video image in the video scaler using a video input clock of the video scaler to generate a first scaled video image.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: July 23, 2013
    Assignee: Broadcom Corporation
    Inventors: Alexander G. MacInnis, Chengfuh Jeffrey Tang, Xiaodong Xie, James T. Patterson, Greg A. Kranawetter
  • Patent number: 8493396
    Abstract: A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: July 23, 2013
    Assignee: Nvidia Corporation
    Inventors: Ashish Karandikar, Shirish Gadre, Stephen D. Lew, Christopher T. Cheng
  • Patent number: 8487946
    Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 16, 2013
    Assignee: Apple Inc.
    Inventors: John Stauffer, Michael K. Larson, Charlie Lao
  • Publication number: 20130162664
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching during media content rendering. In one aspect, a method performed by data processing apparatus includes receiving a request to load a digital image object for rendering; generating a first object from the digital image object; and managing the first object in a cache memory using a management object that is added to and removed from the cache memory along with the first object. In another aspect, a system includes a display device; a computer storage medium containing a cache memory; and a processor programmed to manage caching of data objects to be rendered using management objects that are cached along with the data objects, where at least one of the management objects includes a reference to a corresponding data object and an interface through which release and restoration of the corresponding data object is effected.
    Type: Application
    Filed: September 3, 2010
    Publication date: June 27, 2013
    Applicant: ADOBE SYSTEMS INCORPORATED
    Inventors: Gavin Murray Peacock, Werner Leland Sharp, Angus Ward Davis
  • Patent number: 8471859
    Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: June 25, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chia-Lung Hung, Tzuo-Bo Lin, Hsien-Chun Chang, Yu-Pin Chou
  • Patent number: 8456480
    Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: June 4, 2013
    Assignee: Calos Fund Limited Liability Company
    Inventors: Donald James Curry, Ujval J. Kapasi
  • Patent number: 8456481
    Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: June 4, 2013
    Assignee: Nvidia Corporation
    Inventors: Walter E. Donovan, Emmett M. Kilgariff, Karim M. Abdalla, Joel J. McCormack
  • Patent number: 8456479
    Abstract: Methods, systems and data structures produce a rasterizer. A graphical state is detected on a machine architecture. The graphical state is used for assembling a shell rasterizer. The machine architecture is used for selecting replacement logic that replaces portions of shell logic in the shell rasterizer. The machine architecture is used for selectively inserting memory management logic into portions of the shell logic to produce.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: William A. Hux, Stephen Junkins
  • Patent number: 8436868
    Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 7, 2013
    Assignee: NVIDIA Corporation
    Inventors: Walter E. Donovan, Emmett M. Kilgariff, Karim M. Abdalla, Joel J. McCormack
  • Patent number: 8433747
    Abstract: Systems and methods to implement a graphics remoting architecture for rendering graphics images at remote clients are disclosed. In one implementation, when a D3D application hosted on a remote server is used by a remote client, the graphics associated with the D3D application are created and rendered at the remote client. For this, the D3D commands and D3D objects corresponding to the graphics are abstracted into data streams at the remote server. The data streams are then sent to the remote client. At the remote client, the D3D commands and D3D objects are extracted from the data streams and executed to create the graphics images. The graphics images are then rendered and displayed using output devices at the remote client.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: April 30, 2013
    Assignee: Microsoft Corporation
    Inventors: Kan Qiu, Nadim Y. Abdo
  • Patent number: 8427495
    Abstract: Write operations to a unit of compressible memory, known as a compression tile, are examined to see if data blocks to be written completely cover a single compression tile. If the data blocks completely cover a single compression tile, the write operations are coalesced into a single write operation and the single compression tile is overwritten with the data blocks. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: April 23, 2013
    Assignee: NVIDIA Corporation
    Inventors: John H. Edmondson, Robert A. Alfieri, Michael F. Harris, Steven E. Molnar
  • Patent number: 8427494
    Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 23, 2013
    Assignee: Nvidia Corporation
    Inventors: Ram Prabhakar, Neal Meininger, Lefan Zhong, Cahide Kiris, Ed Ahn