Memory Allocation Patents (Class 345/543)
  • Patent number: 7643038
    Abstract: Apparatus are provided, including an embedded display processor on a given chip. The apparatus may be an embedded device, for example, a mobile wireless communications device. More specifically, the apparatus may be a mobile phone, a portable gaming device, a video streaming device, or a GPS map drawing device. The display processor includes, on the same given chip, a rendering memory, from which pixels are rendered to a display device. The display processor further includes an image manipulation mechanism to manipulate pixels of a given image frame from source positions in a pre-manipulation buffer, to target positions in the rendering memory, the target positions corresponding to rendered positions in the given image frame.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: January 5, 2010
    Assignee: QUALCOMM Incorporated
    Inventor: Scott Howard King
  • Publication number: 20090322771
    Abstract: This disclosure describes a method for allowing multiple users to independently run graphical applications on a Windows computer at the same time by loading private instances of the graphics subsystem for each user at different virtual addresses within the kernel address space.
    Type: Application
    Filed: March 13, 2009
    Publication date: December 31, 2009
    Inventors: Eldad Eilam, Yonatan Doron, Russ Osterlund, David Sleeper
  • Patent number: 7636131
    Abstract: A video data displaying device is disclosed. The video data displaying device is used to drive a displayer according to a first display data set to display a first picture, the displaying device comprises a memory for storing the first display data set, and a display engine which is electrically connected to the memory for storing a part of the first display data set stored in the memory, wherein the display engine selects a specific display data set from the first display data set according to a display area of the displayer, and the display engine does not output the specific display data to the displayer.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: December 22, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ming-Jane Hsieh, Yi-Shu Chang, Te-Ming Kuo
  • Patent number: 7629979
    Abstract: A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: December 8, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Darel N. Emmot, Byron A. Alcorn, Ronald D. Larson
  • Publication number: 20090295814
    Abstract: An operation displaying device including: an operation screen which receives an instruction for operation; a computing device which executes computation; and a performance monitoring unit which monitors a performance of an application software that executes display processing, wherein: when an operation mode of the operation displaying device is in a power saving mode and a remaining memory capacity of a memory, which is used as temporary storage by the computing device, is less than or equal to than a predetermined threshold, the performance monitoring unit restarts the application software which is running.
    Type: Application
    Filed: May 22, 2009
    Publication date: December 3, 2009
    Inventors: Tetsuya MATSUSAKA, Toshimasa TAKAOKA
  • Patent number: 7623133
    Abstract: A computer system including a processor, a display, and a graphics unit coupled between the processor and the display, in which the processor is configured to perform multi-display operations which generate multiple frames of display data for simultaneous display, and a graphics unit for use in such a system. Typically, the graphics unit includes graphics memory that includes at least two frame buffers, and the processor operates as if it were independently asserting multiple streams of display data to multiple frame buffers for driving multiple displays independently. Another aspect of the invention is a system that displays data from a frame buffer on a screen.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: November 24, 2009
    Assignee: NVIDIA Corporation
    Inventors: Abraham B. de Waal, Walter E. Donovan
  • Publication number: 20090284537
    Abstract: Described herein is a system and method for facilitating large volume data processing and rendering. An exemplary system includes at least one processor coupled to a first memory, wherein the processor is configured to organize the large volume data in the first memory into one or more bricks. In addition, at least one graphics processing unit (GPU) is coupled to the processor and a second memory. The GPU is configured to process at least one or more bricks transferred from the first memory to the second memory to produce intermediate processing results, and to further render the intermediate processing results.
    Type: Application
    Filed: February 17, 2009
    Publication date: November 19, 2009
    Applicant: Siemens Corporate Research, Inc.
    Inventors: Wei Hong, Wei Li
  • Patent number: 7616200
    Abstract: An apparatus and method of displaying a first image on a display device with a plurality of pixels assigns one of a plurality of sample patterns to each pixel on the display device. Each pixel is assigned the one of a plurality of patterns based upon its unique location on the display device. Each sample pattern has at least one sample location. It then is determined if the first image intersects any of the sample locations on each pixel. Pixels determined to have at least one sample location that intersect the first image thus are illuminated.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: November 10, 2009
    Assignee: 3Dlabs Inc. Ltd.
    Inventors: Steven J. Heinrich, Mark A. Mosley, Clifford A. Whitmore, James L. Deming, Stewart G. Carlton, Matt E. Buckelew, Dale L. Kirkland, Timothy S. Johnson
  • Patent number: 7613895
    Abstract: A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, where the method includes the steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently in use, determining usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: November 3, 2009
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Hiroyasu Nishimura, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga, Munetoshi Eguchi
  • Patent number: 7612781
    Abstract: A graphic memory is space-divided into a first area and a second area. In the first area, a task corresponding to a predetermined application is executed regardless of which task is processed by a main processor. A switchable area is divided in time so that data related to tasks corresponding to a plurality of applications is sequentially stored in the switchable area in accordance with task switching in the main processor.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: November 3, 2009
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Yoshinori Washizu, Motoi Kaneko, Sachiyo Aoki, Kaoru Yamanoue
  • Publication number: 20090251476
    Abstract: Embodiments of systems and methods for managing a constant buffer with rendering context specific data in multithreaded parallel computational GPU core are disclosed. Briefly described, one method embodiment, among others, comprises responsive to a first shader operation, receiving at a constant buffer a first group of constants corresponding to a first rendering context, and responsive to a second shader operation, receiving at the constant buffer a second group of constants corresponding to a second context without flushing the first group.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 8, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Yang (Jeff) Jiao, Yijung SU, John Brothers
  • Patent number: 7599716
    Abstract: A method is provided for processing data in a mobile communication terminal including a first data memory for storing first data indicating user-stored information and a second data memory for storing second data indicating user-stored information. The method includes creating a first data list corresponding to the first data and a second data list corresponding to the second data and displaying items of the first data list and items of the second data list on a screen of the mobile communication terminal in response to a user's data movement request, selecting at least one item from one that is selected from the first data list and the second data list that are separately displayed based on user's selection information, and storing data of the selected item in the first data memory or the second data memory into the other memory if a predetermined key is input.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: October 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Sun Yoon, Dong-Wook Kwon
  • Patent number: 7598960
    Abstract: A method of storing a digital image in a computer memory includes providing a N-dimensional digital image, defining an offset for each image element (x1, . . . , xN) by the formula offset ? ( x 1 , … ? , x N ) = ? i ? ? n = 1 N ? K x n ? ( i ) ? x ni , where i is summed over all bits and n is summed over all dimensions. The coefficient K for the ith bit of the nth dimension is defined as K x n ? ( i ) = ( ? j = 1 n - 1 ? f ? ( x j , 2 i + 1 , sx j ) ) ? 2 i ? ( ? j = n + 1 N ? f ? ( x j , 2 i , sx j ) ) , where xj is the jth dimension, f(x,G,sxj)=min(G,sxj??x?G) G is a power of 2, sxj represents the size associated with a given dimension, and ?x?G=x?x mod G. Image elements are stored in the computer memory in an order defined by the offset of each image element.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: October 6, 2009
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Pascal Cathier, Senthil Periaswamy
  • Patent number: 7592970
    Abstract: A tiled display device is formed from display tiles having picture element (pixel) positions defined up to the edge of the tiles. Each tile includes a memory which stores display data, and pixel driving circuitry which controls the scanning and illumination of the pixels on the tile. The tiles are formed in two parts, an electronics section and a display section. Each of these parts includes connecting pads which cover several pixel positions. Each connecting pad makes an electrical connection to only one row electrode or column electrode. The connecting pads on the display section are electrically connected and physically joined to corresponding connecting pads on the electronics section to form a complete tile.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: September 22, 2009
    Inventors: Dennis Lee Matthies, Roger Green Stewart, James Harold Atherton, Dennis J. Bechis, Heinz H. Busta, Zilan Shen
  • Patent number: 7589738
    Abstract: A cache memory method and corresponding system for two-dimensional data processing, and in particular, two-dimensional image processing with simultaneous coordinate transformation is disclosed. The method uses a wide and fast primary cache memory (PCM) and a deep secondary cache memory (SCM), each with multiple banks to access data simultaneously. A dedicated pre-fetching logic is used to obtain pixel data from an external memory upon receiving control parameters from an external processor system (PU1), and to store that data in the PCM based on a secondary control queue. The data are then prepared in specific block sizes and in specific format, and then stored in the PCM based on optimally sized pre-fetching primary control queue. The prepared data are then read by another external processor system (PU2) for processing. The cache control logic ensures the coherency of data and control parameters at the input of the PU2.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: September 15, 2009
    Assignee: Integrated Device Technology, inc.
    Inventor: Frederick Christopher Candler
  • Patent number: 7589736
    Abstract: A system and method for converting a pixel rate of a digital image frame is provided. The system includes a display controller with an embedded buffer and programmable input and output buffers. The input buffer writes lines of the frame at a source pixel rate while the output pointer reads out lines of the frame at a display pixel rate thereby allowing display of an image having a source pixel rate that is different, e.g., higher, than a display pixel rate.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: September 15, 2009
    Assignee: Pixelworks, Inc.
    Inventor: Michael G. West
  • Patent number: 7573484
    Abstract: An image processing apparatus for managing a memory device having a plurality of storage areas including a storage area storing out-of-use information and a free area storing no information, the image processing apparatus comprises memory control unit adapted to determine whether or not there is a storage area storing the out-of-use information based on a request for storing information and determining the storage area storing the out-of-use information as an area for storing the information, in a case where the storage area exists; and information writing unit adapted to overwrite generated information to the storage area determined by the memory control unit.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: August 11, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideyuki Kitani
  • Patent number: 7573481
    Abstract: System and method for the management of bit plane resources are presented. Because of the scarcity of processing element (PE) memory in a SIMD architecture, it is important to ensure that it is used with optimal efficiency. The Invention discloses methods for managing PE memory at runtime such that nearly 100% utilization is achieved. The method employed allows memory to be allocated and deallocated in single bit plane increments. Runtime allocation and deallocation occurs continuously such that it is impossible to guarantee availability of contiguous blocks of PE memory. The method employed by the invention allows scattered bit planes to be used without the necessity of expending execution time to perform “garbage collection”.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: August 11, 2009
    Assignee: Teranex Systems, Inc.
    Inventor: Woodrow L. Meeker
  • Patent number: 7564460
    Abstract: Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system are provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modem graphics chips.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: July 21, 2009
    Assignee: Microsoft Corporation
    Inventors: Michele B. Boland, Charles N. Boyd, Anantha R. Kancherla
  • Publication number: 20090167774
    Abstract: Device, system, and method of user-interface rendering. In some demonstrative embodiments, a mobile device may include a display having a first display area; a first user-interface application to render a first user-interface on the display; a second user-interface application to render a second user-interface adapted to be displayed on a second display having a display area larger than the first display area; a frame buffer allocated to buffer information of the first user-interface application; a second frame buffer allocated to buffer information of the second user-interface application; a wireless communication module to communicate with an external display over a wireless communication link; and a remote-frame-buffer protocol to transfer the information of the second user-interface from the second frame buffer to the second display via a wireless communication link. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Roy Want, Trevor Pering
  • Publication number: 20090153575
    Abstract: The present invention provides a method for sharing a graphics card among multiple Operation Systems (OSs) and a computer system. The method comprises: detecting a first GOS to be displayed, the first GOS being one of at least two GOSs; calling a correspondence table to determine a first display control register bank corresponding to the first GOS, the first display control register bank including display mode parameters therein; controlling the first display control register bank to connect to a display output port; and displaying the first GOS based on the display mode parameters. According to the inventive method and computer system, it is possible to achieve sharing of the graphics card among the multiple OSs and quick display of the GOS to be displayed, without simulating registers of the graphics card.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 18, 2009
    Applicants: Beijing Lenovo Software Ltd., Lenovo (Beijing) Limited
    Inventors: Bibo Wang, Yongfeng Liu, Chunmei Liu, Jun Chen
  • Patent number: 7545383
    Abstract: An information processing system includes a first information processor to process data to be displayed in a first display unit and a second information processor to indicate the data displayed in the first display unit. The first information processor includes a first display control unit to control the data to be displayed; a first communication unit to receive operation information from the second information processor and transmit data information about a piece of data indicated by the second information processor; and a first detecting unit to detect a position on the first display unit indicated by the second information processor. The second information processor includes an accepting unit to accept an operation by a user; a second communication unit to transmit operation information to the first information processor and receive the data information from the first information processor; and a received data storage unit to store the data information.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: June 9, 2009
    Assignee: Sony Corporation
    Inventor: Tadashi Morita
  • Patent number: 7538783
    Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. A video scaling system preferably conserves memory by downscaling video prior to capturing the video in memory and upscaling video after the video is called out of memory.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: May 26, 2009
    Assignee: Broadcom Corporation
    Inventors: Alexander G. MacInnis, Chengfuh Jeffrey Tang, Xiaodong Xie, James T. Patterson, Greg A. Kranawetter
  • Patent number: 7528838
    Abstract: A video memory manager manages and virtualizes memory so that an application or multiple applications can utilize both system memory and local video memory in processing graphics. The video memory manager allocates memory in either the system memory or the local video memory as appropriate. The video memory manager may also manage the system memory accessible to the graphics processing unit via an aperture of the graphics processing unit. The video memory manager may evict memory from the local video memory as appropriate, thereby freeing a portion of local video memory use by other applications. In this manner, a graphics processing unit and its local video memory may be more readily shared by multiple applications.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: May 5, 2009
    Assignee: Microsoft Corporation
    Inventors: Anuj Gosalia, Steve Pronovost, Bryan Langley
  • Patent number: 7526134
    Abstract: An image processing apparatus includes a decompressing unit decompressing image data having a first data compression format, an obtaining unit obtaining a second data compression format that is applicable for decompression by another image processing apparatus, a re-compressing unit re-compressing the decompressed image data with the second data compression format obtained by the obtaining unit, and a transmitting unit transmitting the re-compressed image data to the other image processing apparatus.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: April 28, 2009
    Assignee: Ricoh Company, Ltd.
    Inventor: Akio Matsubara
  • Patent number: 7526024
    Abstract: Presented herein is a system for storing macroblocks for concatenated frames. A decoder system comprises a frame buffer. The frame buffer comprises one or more rows. A particular one of the rows stores macroblocks from a plurality of frames.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: April 28, 2009
    Assignee: Broadcom Corporation
    Inventors: Sathish Kumar, Lakshmanan Ramakrishnan, Darren Neuman
  • Publication number: 20090096802
    Abstract: The present invention provides an apparatus for programming functions of a display. The apparatus comprises a memory, a programming device, and a program code checking unit. The memory is for storing a program code. The programming device coupled to the memory is for reading the program code with a predetermined length from the memory. The program code with the predetermined length is part of the program code. The program code checking unit coupled to the programming device is for checking whether the program code with the predetermined length is consistent with a predetermined state, and for selectively generating a control signal. Under control of the control signal, the programming device determines whether to write the program code with the predetermined length into a memory of the display.
    Type: Application
    Filed: October 2, 2008
    Publication date: April 16, 2009
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: CHIEN-LIANG CHEN, CHIH-CHIANG CHIU
  • Patent number: 7518615
    Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: April 14, 2009
    Assignee: Silicon Graphics, Inc.
    Inventors: John M. Airey, Mark S. Peercy, Robert A. Drebin, John Montrym, David L. Dignam, Christopher J. Migdal, Danny D. Loh
  • Patent number: 7515293
    Abstract: An image forming apparatus and a method of acquiring a memory area are disclosed for preventing a problem that image data cannot be converted due to failure of memory acquisition. The image forming apparatus includes an image data conversion part, a resource management part and an image data management part. The image data conversion part has at least one conversion function to convert a format of image data. The resource management part determines a memory size required for a conversion function to convert the format of the image data. The image data management part acquires a memory area corresponding to the determined memory size.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: April 7, 2009
    Assignee: Ricoh Company, Ltd.
    Inventors: Osamu Kizaki, Hidenori Shindoh, Kiyotaka Moteki, Takao Okamura
  • Publication number: 20090085921
    Abstract: A method, system and computer usable medium are disclosed for managing the display of content elements within a predetermined display area of a user interface. Content requests are submitted from a browser to a content server. In response, the content server acquires candidate content elements for display within the browser. A content element manager determines the dimensions of a target display area within the user interface (UI) of the browser. The content element manager then determines the space required to display each of the candidate content elements. Calculations are then performed to determine the maximum number of content elements that will fit within the dimensions of target display area. Once determined, the content elements are selected and displayed in the display area.
    Type: Application
    Filed: October 1, 2007
    Publication date: April 2, 2009
    Inventors: Lydia Mai Do, Fu Yi Li, Pamela Ann Nesbitt, Lisa Anne Seacat
  • Patent number: 7495669
    Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: February 24, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsutoshi Ushida, Yuichi Naoi, Yoshiaki Katahira, Yasuyuki Nakamura, Koichi Morishita, Makoto Fukuo
  • Publication number: 20090027409
    Abstract: An interface apparatus and a method of writing an extended display identification data (EDID) are provided. The interface apparatus includes a data processing unit, a memory unit and a switching unit. The memory unit is coupled to a connector corresponding to the memory unit and the data processing unit via the switching unit. When the interface apparatus is being initialized, the data processing unit detects whether or not the EDID stored in the memory unit is correct. If the EDID stored in the memory unit is incorrect, the data processing unit rewrites the EDID to the memory unit.
    Type: Application
    Filed: December 4, 2007
    Publication date: January 29, 2009
    Applicant: CORETRONIC CORPORATION
    Inventors: Ming- Chih Kao, Chun-Chieh Chen, Wen- Chin Chen
  • Patent number: 7477267
    Abstract: It is determined whether or not blocks of a main scanning direction-wise pixel line of an LCD and a sub-image data of an image information table are superposed. When they are determined to be superposed, a reading out address of the sub-image data is calculated, a sub-image block data is read out from the calculated reading out address, and the obtained sub-image block data is stored in a block buffer. After the superposition has been realized for all the sub-image data of the image information table, and then the sub-image block data have been stored in the block buffers, the plural sub-image block data stored in the block buffers are compounded.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: January 13, 2009
    Assignee: FUJI FILM Corporation
    Inventor: Katsumi Takayama
  • Publication number: 20090009524
    Abstract: A method for the incrementation of counter statuses in memory cells, which are arranged respectively in rows and columns of a first memory adds a “1” to the memory content of a memory cell of a second memory, which corresponds to the memory cell at the start of a sequence of memory cells to be incremented in a row or column of the first memory in the case of every incrementation of a sequence of memory cells of the first memory, and adds a “?1” to the memory content of a memory cell of the second memory, which corresponds to the memory cell immediately following the memory cell at the end of the sequence of memory cells to be incremented associated with the start of the sequence, in the case of every incrementation of a sequence of memory cells of the first memory.
    Type: Application
    Filed: September 26, 2007
    Publication date: January 8, 2009
    Inventor: Kurt Schmidt
  • Publication number: 20080316220
    Abstract: A common module for a double data rate-synchronous II synchronous dynamic random access memory (DDRII SDRAM) and a DDRIII SDRAM applied in a computer is provided. The common module includes a first bus, a termination circuit card, a first slot, and a second slot. The first bus transmits a plurality of signals. The termination circuit card comprises a plurality of termination resistors. The first slot is disposed on the common module and coupled to the first bus. The DDRII SDRAM is installed in the first slot. The second slot is disposed on the common module and coupled to the first bus. The DDRIII SDRAM or the termination circuit card is installed in the second slot. When the DDRII SDRAM is installed in the first slot, the termination circuit card is installed in the second slot.
    Type: Application
    Filed: June 25, 2007
    Publication date: December 25, 2008
    Inventors: Chin-Hui Chen, Hou-Yuan Lin
  • Patent number: 7450116
    Abstract: An apparatus for storing, displaying and recalling data, includes a display field for displaying data, a memory for storing said data, a keypad for entering the data into the memory, and a field button associated with the display field for initiating entry of the data into the apparatus. The field button is adjacent to the display field. A recall button for recalling stored data and for causing the recalled stored data to appear on the display field is also provided adjacent to the display field.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: November 11, 2008
    Assignee: Flight Vitals, Inc.
    Inventor: Marc Howard Greenstein
  • Patent number: 7450125
    Abstract: A method and system for compressing and displaying a digital ink trace. Raw ink data is smoothed, and sharp points of the smoothed line are found. Curve-fitting is then used to generate a mathematical expression that defines the line segments between adjacent sharp points. The ink trace then is represented by a backbone spline that includes the sharp points and the mathematical expressions for the line segments. Thickness information, such as pressure or acceleration information, is combined with the backbone spline to provide a compressed ink file that represents a contour curve of the original ink trace. A display module uses an algorithm to separate the contour curve into a sequence of straight lines. A set of pixels is then generated for the display of each straight line using a novel antialiasing method. The pixels at the ends of adjacent straight lines are aligned using a weighting algorithm.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: November 11, 2008
    Assignee: Microsoft Corporation
    Inventors: Jian Wang, Yu Zou, Liyong Chen, Siwei Lyu
  • Publication number: 20080266306
    Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.
    Type: Application
    Filed: June 13, 2008
    Publication date: October 30, 2008
    Inventor: William Radke
  • Patent number: 7417600
    Abstract: A data processing system and method in which, by way of example, a memory system is coupled to a video game program processing system. The video game program processing system has a predetermined address space for executing programs stored in a program memory portion of the memory system. The contents of a plurality of storage locations determine a configuration of the memory system depending on which of a plurality of different game programs is to be executed by the video game program processing system.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: August 26, 2008
    Assignee: Nintendo Co., Ltd.
    Inventors: Darren C. Smith, Kenji Nishizawa, David J. McCarten, Ramin Ravanpey, Russell G. Braun
  • Patent number: 7414619
    Abstract: A control method to control a display unit in which a video signal is supplied by an external device to display the video signal, the control method including: dividing EDID information of the display unit in essential EDID information that is required to display the video signal and non-essential EDID information excluding the essential EDID information; and storing the essential EDID information in a non-changeable memory and at least a part of the non-essential EDID information in the changeable memory.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: August 19, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-chan Kim
  • Patent number: 7403203
    Abstract: Storing frames of data in frame buffers sized to match the frame size when the frame size is not a power-of-two number of bytes is disclosed. The buffer size is chosen to be the largest power-of-two that is less than the frame size. When a frame of data is to be stored, the buffer number of a free buffer is effectively multiplied by the buffer size to obtain a partial frame buffer address Q. The buffer size subtracted from the frame size is referred to as a residual buffer size, and the buffer number is effectively multiplied by the residual buffer size to obtain a residual frame buffer address R. The full frame buffer starting address S=Q+R. For implementations where the difference between the frame size and the buffer size is a power-of-two value, binary shifts and addition can be used instead of a multiplier.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: July 22, 2008
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: Bradley Eugene Roach, Raul Bersamin Oteyza, David James Duckman
  • Publication number: 20080170083
    Abstract: Embodiments of efficient memory implementations for novel display system are herein disclosed. One embodiment comprises a display system comprising a display, said display comprising a plurality of logical pixels wherein said logical pixels further comprise a first number of center-subpixels and a memory, said memory storing said image data to be rendered by said display; wherein said memory is mapped such that said center-subpixels are stored in addressable memory cells.
    Type: Application
    Filed: April 4, 2006
    Publication date: July 17, 2008
    Applicant: CLAIRVOYANTE, INC
    Inventors: Seok Jin Han, Thomas Lloyd Credelle, Moonhwan Im
  • Patent number: 7397477
    Abstract: A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memory in accordance with a first memory address allocation format and the memory addresses are decoded to access the addressable memory locations of a second block of memory in accordance with a second memory address allocation method different from the first memory address allocation format.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: July 8, 2008
    Assignee: Micron Technology, Inc.
    Inventor: William Radke
  • Patent number: 7397480
    Abstract: Systems and methods for displaying volume data on an arbitrary three-dimensional polygonal surface are disclosed. For each polygon in the polygonal surface, a two-dimensional texture tile is created and these texture tiles are combined to form texture atlases. Each texture atlas is allocated a specific amount of memory in a texture cache. Each polygon in the polygonal surface may be scan-converted and the resulting texels may be placed in the texture cache. Voxels that do not intersect any polygon in the polygonal surface may not be scan-converted. This method may result in reduced use of texture cache.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: July 8, 2008
    Assignee: Landmark Graphics Corporation
    Inventor: Sean Spicer
  • Patent number: 7394466
    Abstract: In a method for memory allocation for images, when storing data describing an image (10) in operating memory (1), the image (10) is divided into lines, and each line is described by a separate subset of data from which at least one set of data is created, to which a free segment of operating memory (1) is assigned. The creation of sets of data is performed until data describing the whole image (10) is assigned to the sets of data, and when reading the image (10), consecutive lines are read from the operating memory (1), until the whole image (10) is read.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: July 1, 2008
    Assignees: Advanced Digital Broadcast Polska SP. Z.O.O., Advanced Digital Broadcast, Ltd.
    Inventor: Pawel Wróbel
  • Publication number: 20080143732
    Abstract: In one embodiment, a predetermined amount of bitmap data is accumulated in a first cache memory, a predetermined amount of arrangement-converted bitmap data is accumulated in the second cache memory, the number of instances of switching between value 0 and value 1 when transferring/outputting bitmap data is compared to the number of instances of switching between value 0 and value 1 when transferring/outputting arrangement-converted bitmap data, and the bitmap data or the arrangement-converted bitmap data with the lesser number of instances of switching is transferred/output to a RAM; thus, the power consumption when transferring/outputting data to the RAM via a data bus is reduced.
    Type: Application
    Filed: October 31, 2007
    Publication date: June 19, 2008
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Seiya Shiozaki
  • Patent number: 7386651
    Abstract: Presented herein is a system for storing macroblocks for such that all vertically, horizontally, and diagonally adjacent macroblock are stored in different banks. When fetching a block from a reference frame that overlaps four macroblocks, each of the overlapped macroblocks can be fetched substantially concurrently.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: June 10, 2008
    Assignee: Broadcom Corporation
    Inventors: Ramanujan Valmiki, Sathish Kumar
  • Patent number: 7369134
    Abstract: Methods and associated systems that allow a plurality of real-time multimedia applications to operate concurrently within a computer system with constrained primary memory. In particular, the methods and systems of the present invention allow for a plurality of real-time multimedia applications to operate concurrently while adapting to changing memory constraints imposed by the dynamic allocation and release of primary memory in a shared primary memory space.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: May 6, 2008
    Assignee: Anark Corporation
    Inventors: Scott Collins, Mattias Fornander, Justin Ebert, Scott Saad
  • Publication number: 20080084426
    Abstract: An off-screen buffering management device and method are disclosed. In the device, an application unit creates a window to be displayed on a screen, and makes a request for a drawing of the created window. An off-screen buffering area for storing off-screen data corresponding to the window is set in a back buffer, and a buffer manager draws the window, if a request for drawing the window is made, in the set off-screen buffering area in the back buffer and stores the window.
    Type: Application
    Filed: April 18, 2007
    Publication date: April 10, 2008
    Inventor: Sang-jung Park
  • Patent number: 7355601
    Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: April 8, 2008
    Assignees: International Business Machines Corporation, Microsoft Corporation
    Inventors: Jeffrey A. Andrews, Nicholas R. Baker, J. Andrew Goossen, Russell D. Hoover, Eric O. Mejdrich, Sandra S. Woodward