Abstract: A technique for caching coverage information for edges that are shared between adjacent graphics primitives may reduce the number of times a shared edge is rasterized. Consequently, power consumed during rasterization may be reduced. During rasterization of a first graphics primitive coverage information is generated that (1) indicates cells within a sampling grid that are entirely outside an edge of the first graphics primitive and (2) indicates cells within the sampling grid that are intersected by the edge and are only partially covered by the first graphics primitive. The coverage information for the edge is stored in a cache. When a second graphics primitive is rasterized that shares the edge with the first graphics primitive, the coverage information is read from the cache instead of being recomputed.

Abstract: In contrast to a conventional computing system in which the graphics processor (graphics processing unit or GPU) is treated as a slave to one or several CPUs, systems and methods are provided that allow the GPU to be treated as a central processing unit (CPU) from the perspective of the operating system. The GPU can access a memory space shared by other CPUs in the computing system. Caches utilized by the GPU may be coherent with caches utilized by other CPUs in the computing system. The GPU may share execution of general-purpose computations with other CPUs in the computing system.

Abstract: An image processing apparatus has a plurality of functions and is capable of executing a job relating to any of the plurality of functions. The image processing apparatus includes a memory management unit to secure a storage region in a first storage device for program execution, a save unit to save information from the storage region in the first storage device to a second storage device, a history recording unit to record a history relating to execution of the job each time the image processing apparatus executes the job, and a save restriction unit to restrict saving of information from the storage region in the first storage device to the second storage device in order to execute a job relating to a function which is specified based on a job history recorded by the history recording unit from among the plurality of functions.

Abstract: A system, method, and computer program for high-speed, efficient text rendering are disclosed. In accordance with certain embodiments of the present invention, an image resource architecture is provided for optimal sub-image uploads to keep the glyph cache up to date. A glyph cache is divided into zones, or sub-caches, wherein requests for writing a glyph bitmap to the cache may be handled by destroying or clearing an entire zone. In accordance with other embodiments of the present invention, a highly efficient method of rendering is provided wherein commands are automatically combined and made into larger commands for the GPU. Alternatively, rather than performing a command stream flush upon each intersection, a texture cache flush may be implemented. All source glyph bitmaps may be placed into one texture.

Abstract: Modification messages may be filtered to reduce the load on a message channel between a render cache and a frame buffer compression. A group of cache lines may be checked to see whether both a subspan request hits an unlit bit and a modify message was already sent. If so, the modification message may be filtered.

Abstract: An image displaying device with an image cache data storage unit, including: an image cache identifier generating unit that obtains a hash value of a fixed length from sampling data of original image data and generates an image cache identifier unique to said original image data based on the hash value of a fixed length; an image cache searching unit that checks whether image cache data to which the generated image cache identifier is added is stored in said image cache memory or not; and an image cache generating unit that, when the image cache data has been not stored in said image cache memory, generates image cache data by adding the image cache identifier generated by said image cache identifier generating unit to the original image data and stores the image cache data in said image cache memory.

Abstract: A method includes searching storage media of a computing appliance for application-specific configuration files by executing a configuration utility from a non-transitory storage medium of the computing appliance, upon finding an application-specific configuration file, directing a graphics processing unit (GPU) driver to partition a portion of GPU random access memory (RAM) as cache, and loading data specified in the configuration file to the cache portion partitioned in the GPU RAM.

Abstract: A method of operating a pixel cache having a plurality of linefill units and configured to fetch an image stored in a main memory includes receiving a request for data of one or more image planes from a processor, and if the request for at least one image plane is determined as a “hit”, outputting the requested data of the at least one image plane and fetching the requested data from main memory of at one other image plane determined as not a “hit”. A “hit” is determined for each image plane of the one or more image planes based on whether data of the image plane is stored in one of the plurality of linefill units. The image plane may include at least two rows and at least two columns of pixels and has a size substantially identical to a capacity of the linefill unit.

Abstract: A system, method, and computer program product are provided for GPU demand paging. In operation, input data is addressed in terms of a virtual address space. Additionally, the input data is organized into one or more pages of data. Further, the input data organized as the one or more pages of data is at least temporarily stored in a physical cache. In addition, access to the input data in the physical cache is facilitated.

Abstract: An image browsing method, system and computer storage media are disclosed. The method includes: obtaining a user's operation request for an image; comparing the operation request with a preset condition, and determining whether to cache the image into a main cache. When it is required to cache the image into the main cache, further determining whether it is the first time that the image is rendered; if yes, employing a main thread to cache the image into the main cache, to obtain the image from the main cache, and to render the image. Otherwise, employing a main thread to obtain an image adapted to the capacity of the main cache from an image chain, and to render the image; and displaying the image rendered. This avoids unsmooth browsing of the image due to time-consuming creation of the images to be rendered, thereby allowing smooth image browsing.

Abstract: A printer interprets the input print data and determines whether or not a rendering command targeted for reusable data included in print data depends on a placement location for placement of the rendering result in a physical coordinate space based on the interpretation result of the PDL data. When the rendering command depends on a placement location for placement of the rendering result in a physical coordinate space, the printer generates cache data without graphic processing for the rendering command targeted for reusable data and stores the generated cache data in a storage unit. When the rendering command does not depend on a placement location for placement of the rendering result in a physical coordinate space, the printer performs graphic processing for the rendering command targeted for the reusable data, generates cache data based on the result of the graphic processing, and stores the generated cache data in a storage unit.

Abstract: Data for data elements (e.g., pixels) can be stored in an addressable storage unit that can store a number of bits that is not a whole number multiple of the number of bits of data per data element. Similarly, a number of the data elements can be transferred per unit of time over a bus, where the width of the bus is not a whole number multiple of the number of bits of data per data element. Data for none of the data elements is stored in more than one of the storage units or transferred in more than one unit of time. Also, data for multiple data elements is packaged contiguously in the storage unit or across the width of the bus.

Abstract: An apparatus and system for accessing an image in a memory storage is disclosed herein. The apparatus includes logic to pre-fetch image data, wherein the image data includes pixel regions. The apparatus also includes logic to arrange the image data as a set of one-dimensional arrays to be linearly processed. The apparatus further includes logic to process a first pixel region from the image data, wherein the first pixel region is stored in a cache. Additionally, the apparatus includes logic to place a second pixel region from the image data into the cache, wherein the second pixel region is to be processed after the first pixel region has been processed, and logic to process the second pixel region. Logic to write the set of one-dimensional arrays back into the memory storage is also provided, and the first pixel region is evicted from the cache.

Abstract: A graphics system includes a graphics processor and a cache memory system. The graphics processor includes processing units that perform various graphics operations to render graphics images. The cache memory system may include fully configurable caches, partially configurable caches, or a combination of configurable and dedicated caches. The cache memory system may further include a control unit, a crossbar, and an arbiter. The control unit may determine memory utilization by the processing units and assign the configurable caches to the processing units based on memory utilization. The configurable caches may be assigned to achieve good utilization of these caches and to avoid memory access bottleneck. The crossbar couples the processing units to their assigned caches. The arbiter facilitates data exchanges between the caches and a main memory.

Abstract: One embodiment of the present invention sets forth a technique for using a shared memory to store hardware-managed virtual buffers. A circular buffer is allocated within a general-purpose multi-use cache for storage of primitive attribute data rather than having a dedicated buffer for the storage of the primitive attribute data. The general-purpose multi-use cache is also configured to store other graphics data sinces the space requirement for primitive attribute data storage is highly variable, depending on the number of attributes and the size of primitives. Entries in the circular buffer are allocated as needed and released and invalidated after the primitive attribute data has been consumed. An address to the circular buffer entry is transmitted along with primitive descriptors from object-space processing to the distributed processing in screen-space.

Abstract: Systems, methods and computer-readable storage media are disclosed for accelerating bitmap remoting by extracting non-grid tiles from source bitmaps. A server takes a source image, identifies possibly repetitive features, and tiles the image. For each tile that contains part of a possibly repetitive feature, the server replaces that part with the dominant color of the tile. The system then sends to a client a combination of new tiles and features, and indications to tiles and features that the client has previously received and stored, along with an indication of how to recreate the image based on the tiles and features.

Abstract: A color buffer cache may be implemented in a way that reduces memory bandwidth. In one embodiment this may be done by determining whether a corresponding tile being rendered is completely inside a triangle. If so, the cache lines that correspond to this tile may be marked as “less useful”. As a result of being marked as less useful, those cache lines may be replaced before other cache lines in one embodiment. Thus a color buffer cache is used for those tiles that overlap with at least one triangle edge. The use of such a color buffer cache scheme may be more efficient and therefore may reduce memory bandwidth in some embodiments.

Abstract: There is provided an information processing apparatus including a storage unit for storing a transition frequency database storing transition frequency information representing a frequency of a state transition of a display content displayed on a display screen from a display state displaying the display content to another display state, and a cache control unit for predicting the another display state to which a transition may occur based on the transition frequency database and the display content displayed on the display screen, and preparing a resource needed by the another predicted display state before the transition occurs.

Abstract: Systems and methods for an efficient display data transfer algorithm over a network are disclosed. A compressed frame buffer update transmitted from a server via a network is received by a hardware decompression engine. The hardware decompression engine identifies one or more palette entries indicated in the compressed frame buffer update and determines whether the one or more palette entries is stored in a palette cache of the hardware decompression engine. If the one or more palette entries is not stored in the palette cache, the hardware decompression engine writes the one or more palette entries from an external palette memory to the palette cache. Decompressed display data is generated based on the compressed frame buffer update using the palette cache. The decompressed display data is written to an output buffer of the hardware decompression engine.

Abstract: An image processing apparatus is provided that includes a main memory; at least one sub-memory that stores data, a cache memory that temporarily stores data, and controller that controls whether to temporarily store the data in the cache memory selectively with respect to each of the at least one sub-memory.

Abstract: One embodiment of the present invention includes approaches for processing graphics primitives associated with cache tiles when rendering an image. A set of graphics primitives associated with a first render target configuration is received from a first portion of a graphics processing pipeline, and the set of graphics primitives is stored in a memory. A condition is detected indicating that the set of graphics primitives is ready for processing, and a cache tile is selected that intersects at least one graphics primitive in the set of graphics primitives. At least one graphics primitive in the set of graphics primitives that intersects the cache tile is transmitted to a second portion of the graphics processing pipeline for processing. One advantage of the disclosed embodiments is that graphics primitives and associated data are more likely to remain stored on-chip during cache tile rendering, thereby reducing power consumption and improving rendering performance.

Abstract: One embodiment of the present invention includes techniques for adaptively sizing cache tiles in a graphics system. A device driver associated with a graphics system sets a cache tile size associated with a cache tile to a first size. The detects a change from a first render target configuration that includes a first set of render targets to a second render target configuration that includes a second set of render targets. The device driver sets the cache tile size to a second size based on the second render target configuration. One advantage of the disclosed approach is that the cache tile size is adaptively sized, resulting in fewer cache tiles for less complex render target configurations. Adaptively sizing cache tiles leads to more efficient processor utilization and reduced power requirements. In addition, a unified L2 cache tile allows dynamic partitioning of cache memory between cache tile data and other data.

Abstract: One embodiment of the present invention includes a graphics subsystem that includes a tiling unit, a crossbar unit, and a screen-space pipeline. The crossbar unit is configured to transmit primitives interleaved with state change commands to the tiling unit. The tiling unit is configured to record an initial state associated with the primitives and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a first cache tile. The tiling unit is further configured to transmit the initial state to the screen-space pipeline and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a second cache tile. The tiling unit includes a state filter block configured to determine that a first state change in the state change commands is followed by a second state change, without an intervening primitive, and to forego transmitting the first state change in response.

Abstract: An exemplary method for emulating a graphics processing unit (GPU) includes executing a graphics application on a host computing system to generate commands for a target GPU wherein the host computing system includes host system memory and a different, host GPU; converting the generated commands into intermediate commands; based on one or more generated commands that call for one or more shaders, caching one or more corresponding shaders in a shader cache in the host system memory; based on one or more generated commands that call for one or more resources, caching one or more corresponding resources in a resource cache in the host system memory; based on the intermediate commands, outputting commands for the host GPU; and based on the output commands for the host GPU, rendering graphics using the host GPU where output commands that call for one or more shaders access the one or more corresponding shaders in the shader cache and where output commands that call for one or more resources access the one or more

Abstract: A parallel processing subsystem includes a plurality of general processing clusters (GPCs). Each GPC includes one or more clipping, culling, viewport transformation, and perspective correction engines (VPC). Since VPCs are distributed per GPC, each VPC can process graphics primitives in parallel with the other VPCs processing graphics primitives.

Abstract: Disclosed is a system for producing images including an application program interface. The system includes an API and techniques for creating images by defining relationships between filters and images, such relationships programmatically assembled in an object by a cooperative session between a requesting application and a graphics services resource. The system also includes aspects regarding optimization of the programmatically assembled object and techniques for rendering in multi-processor environment.

Abstract: A system, method, and computer program product are provided for optimizing use of a vertex cache. In use, information is identified, where such information is associated with vertex data stored in a vertex cache. To this end, use of the vertex cache may be optimized utilizing the information. In one embodiment, the information may include new information derived from the vertex data, and optionally index data, prior to processing of the vertex data. Further, the vertex cache may optionally utilize the information to optimize performance of the vertex cache by minimizing a number of cache misses.

Abstract: The present invention relates to a method for processing data entities by a data processing system, wherein: a first and a second set of data entities are stored in a main memory and associated with a respective first and second set of points of a domain; the first set of data entities is loaded into a local storage; one or more first calculations are performed using the first set of data entities to generate first calculated data; the second set of data entities is determined according to at least some of the first calculated data; the determined second set of data entities is loaded into the local storage; and one or more second calculations are performed using the second set of data entities resulting in second calculated data.

Abstract: In certain embodiments, methods and systems for multimedia data processing are provided. In an embodiment, a method for processing multimedia data includes defining one or more pixel block regions in a first cache so as to cache a plurality of reference pixel blocks corresponding to reference data. A reference pixel block from among the plurality of reference pixel blocks is assigned to a pixel block region from among the one or more pixel block regions based on a predetermined criterion. The reference pixel block is associated with a tag based on the pixel block region so as to facilitate a search of the reference data in order to process a plurality of pixel blocks associated with a multimedia frame of the multimedia data.

Abstract: Embodiments of the present invention provide a system for performing image conversion operations. The system starts by receiving a request from a client for one or more pixel buffers containing a pixel-formatted, cropped, geometrically transformed, and/or color matched version of an image representation. The system then determines if a provider can provide the one or more pixel buffers. If so, the system calls the provider to generate the one or more pixel buffers containing the pixel-formatted, cropped, geometrically transformed, and/or color matched version of the image representation. Otherwise, the system calls the provider to generate one or more intermediate pixel buffers, generates a sequence of converters for converting the one or more intermediate pixel buffers, and calls the sequence of converters to generate the one or more pixel buffers containing the pixel-formatted, cropped, geometrically transformed, and/or color matched version of the image representation.

Abstract: The embodiment of the disclosure discloses a method and terminal for implementing display cache, which comprise storing, in memory, texts to be displayed as text component objects; creating a cache image object with a same size as a stored text component when displaying the text component on a screen. In the solution of display cache according to the embodiment of the disclosure, cache images are only created for text regions. Memory that would be occupied by creating cache images for non-text regions, can be saved, which offers the cache images a smaller area and a less memory occupation. By means of the solution according to the embodiment of the disclosure, a lot of running memory can be saved for programs and memory requirements of a lot of product characteristics can be met, without affecting fast display.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: An instruction cache and data cache used to virtualize the storage of global data and instructions used by graphics shaders. Present day hardware design stores the global data and instructions used by the shaders in a fixed amount of registers or writable control store (WCS). However, this traditional approach limits the size and the complexity of the shaders that can be supported. By virtualizing the storage of the global data and instructions, the amount of global or state memory available to the shader and the length of the shading programs are no longer constrained by the physical on-chip memory.

Abstract: Techniques are described to configure a cache line structure based on attributes of a draw call and access direction of a texture. Attributes of textures (e.g., texture format and filter type), samplers, and shaders used by the draw call can be considered to determine the line size of a cache. Access direction can be considered to reduce the number of lines that are used to store texels required by a sample request.

Abstract: Techniques are described to generate an index for a texture. The index can be used to retrieve a portion of one or more textures from a cache. The index can be adapted based on static texture attributes or direction attributes in order to attempt to achieve texture cache efficiency. Static texture attributes can include, bit are not limited to, 1-dimensional texture, 2-dimensional texture, 3-dimensional texture, or MIPmaps texture, original memory address. Direction attributes can be, but are not limited to, u-major or v-major directions.

Abstract: According to one embodiment, a method includes: displaying an image in an orientation of an image capturing device associated with the mobile device rendered during a capture of the image; providing a user interface configured to process a user input for reorienting the image into a second orientation by displaying a thumbnail image of the image and a graphical user interface in a shape of a wheel surrounding the thumbnail image and rotating the thumbnail image to the second orientation when the user input is applied to the graphical user interface in the shape of the wheel to a degree of rotation corresponding to the second orientation; and displaying the image into the second orientation in response to the user input by reorienting the image in the second orientation when the user input applied to the graphical user interface in the shape of the wheel is released.

Abstract: A vector graphics data management unit 24 has a management table 25 holding pointers and priority ranks of caches to a cache unit 23. The management table 25 also holds a pointer whose priority rank is lower than those of pointers pointing to data cached by the cache unit 23. When receiving a drawing command, the vector graphics data management unit 24 carries out determination of whether a pointer included in the drawing command exists in the management table 25 and management of the management table 25 on the basis of a predetermined insertion rank when the pointer does not exist in the management table.

Abstract: GPU fragment programs can be used to render images in a computer system. These fragment programs are generated from render trees, which specify one or more filters or functions to be applied to an input image to render an output image. It is not uncommon for successive frames to require application of substantially the same filters. Therefore, rather than regenerate and recompile new fragment programs for successive corresponding render trees, the render trees are substantially uniquely identified and cached. Thus, when a render tree is received, it can be identified, and this identifier (such as a hash) can be used to determine whether a corresponding fragment program has already been generated, compiled and cached. If so, the corresponding cached fragment program is retrieved and executed. If not, a fragment program for the newly received render tree is generated and cached.

Abstract: Techniques for surface caching are described in which a cache for surfaces is provided to enable existing surfaces to be reused. Surfaces in the cache can be assigned to one of multiple surface lists used to service requests for surfaces. The multiple lists can include at least a main list and an auxiliary list configured to group existing surfaces according to corresponding surface constraints. When a surface is requested, the multiple lists can be searched to find an existing surface based on constraints including, for example, the type of surface and size requirements for the requested surface. If an existing surface is discovered, the existing surface can be returned to service the request. If a suitable surface is not found in the multiple lists, a new surface is created for the request and the new surface can be added to a corresponding one of the multiple surface lists.

Abstract: The present invention discloses a character display method and apparatus. The method includes: obtaining a display color value of a character; obtaining a background color value of the character according to a position of the character; obtaining a difference between the display color value and the background color value; obtaining an outline of the character when the difference is smaller than a preset threshold; and displaying the character that has the outline. By adopting the present invention, the character may be clearly displayed in a background without changing a color of the character and a color of the background.

Abstract: A method, apparatus, system and medium for reading data from a tiled memory. In some embodiments a method may, include for one tiled-X cache read request, requesting two cache lines from the tiled memory without fragmenting the tiled-X cache read request, and returning data associated with the two requested cache lines.

Abstract: A display device that comprises a flag memory containing state flags of pixel areas of the image is provided. The display device comprises a display screen and a graphical generation unit implementing at least three functions for displaying an image, i.e. a first data erasure function, a second function for generating an image comprised of pixels in a first memory, and a third function for displaying the image by reading the pixels in said memory and controlling the screen, in which an image is divided into a plurality of separate pixel areas and in that each area is addressed by a flag, wherein the display device further includes a memory that stores the flag states so that the graphical generation unit can execute the display function on the basis of the flag states. The generation of images having a predominantly uniform background can, in particular, be used for application in aeronautics.

Abstract: Systems and methods for cache-based compressed display data storage are provided. One system includes memory operable to store compressed display data, a processor comprising a processing core and a cache, a cache storage module operably coupled to the memory and the processor, wherein the cache storage module is to initiate a storage of at least a portion of the compressed display data in the cache in response to an indication that the processing core is in an inactive mode. One method comprises, in response to an indication that a processor is in an inactive mode, transferring compressed display data from a frame buffer in memory to a cache associated with the processor, obtaining a first compressed display data from the cache, and decompressing the first compressed display data to generate a first uncompressed display data.

Abstract: Provided is a video signal generation apparatus and method that may minimize crosstalk between a luminance signal and color difference signals. The video signal generation apparatus may generate the luminance signal using a nonlinear Y signal and then generate color difference signals using a nonlinear XYZ signal to maximize a de-correlation characteristic between the luminance signal and the color difference signals.

Abstract: Methods are described for determining an optimal path for creating a scheme for dividing a text line of Chinese, Japanese or Korean (CJK) characters into character cells prior to applying classifiers and recognizing characters. Gaps between characters are found as a window is moved down the text line. Finding gaps may involve finding 4-connected paths. A histogram is built based on distances from start of window to a respective gap. The window is moved to the end of each gap after each gap is found and distances measured. Process is repeated until window reaches the end of the text line and all gaps found. A linear division graph (LDG) is constructed according to detected gaps. Penalties for certain distances are applied. An optimum path is one with a minimal penalty sum and can be used as a scheme for dividing text lines into character cells.

Abstract: Systems and methods for improving throughput of a graphics processing unit are disclosed. In one embodiment, a system includes a multithreaded execution unit capable of processing requests to access a constant cache, a vertex attribute cache, at least one common register file, and an execution unit data path substantially simultaneously.

Abstract: An image generating apparatus comprises an image data storage unit configured to store an original image data therein, and an image data buffering unit that allows data to be read out therefrom at a higher speed than the image data storage unit. A display times counting unit divides a whole of the original image data into a plurality of blocks and counts the number of times each of the blocks has been referenced or utilized for the generation of the image data to be displayed, as the number of display times. A priority order setting unit sets a priority order on a block-by-block basis based on the number of display times thus counted. A buffering control unit performs a control such that image data in a block which is given a higher priority order is stored in the image data buffering unit more preferentially.

Abstract: A computer readable medium is provided embodying instructions executable by a processor to perform a method for caching video data in a two-dimensional cache. The method includes storing the video data in the two-dimensional cache, addressing stored video data in the two-dimensional cache using a first tag for referencing video data of a first dimension, addressing the stored video data in the cache in terms of a second tag for referencing video data of a second dimension, and retrieving and outputting a portion of the stored video data from the two-dimensional cache according to one of the first tag and the second tag.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: A method for storing information may include determining whether a received data object fits inside a particular one of a plurality of free blocks in a memory bitmap. Each of the plurality of free blocks may include a column of the memory bitmap with a top margin, a bottom margin, and a predetermined width. If the received data object fits, the received data object may be stored in the particular one of the plurality of free blocks, starting at the top margin of the particular one of the plurality of free blocks. The particular one of the plurality of data blocks may be resized by moving the top margin to start below the stored received data object. The determining may include, for each of the plurality of free blocks, a height of the received data object may be compared with a height of each of the free data blocks.