Abstract: A Procesor-In-Memory (PIM) includes a digital accelerator for image and graphics processing. The digital accelerator is based on an ALU having multipliers for processing combinations of bits smaller than those in the input data (e.g., 4×4 adders if the input data are 8-bit numbers). The ALU implements various arithmetic algorithms for addition, multiplication, and other operations. A secondary processing logic includes adders in series and parallel to permit vector operations as well as operations on longer scalars. A self-repairing ALU is also disclosed.

Abstract: A method, apparatus and article of manufacture are provided for performing rasterization using alternating sense point traversal. Upon receipt of a primitive, i.e. a triangle, a plurality of points are positioned on or near the primitive. Such points define an enclosed convex region and may be located at corners of the convex region. In operation, the points and convex region are moved in an alternating manner for the purpose of identifying an area in the primitive for rendering pixels therein. In particular, the points are moved in a boustrophedonic manner.

Abstract: A method, apparatus and article of manufacture are provided for sequencing graphics processing in a transform or lighting operation. A plurality of mode bits are first received which are indicative of the status of a plurality of modes of process operations. A plurality of addresses are then identified in memory based on the mode bits. Such addresses are then accessed in the memory for retrieving code segments which each are adapted to carry out the process operations in accordance with the status of the modes. The code segments are subsequently executed within a transform or lighting module for processing vertex data.

Abstract: A method and graphics accelerator apparatus for pipelined generation of output values for a sequence of pixels, with generation of output values for each of at least two textured pixels during each pipeline clock interval. The apparatus includes a combiner stage capable of producing output values during each clock interval of the pipeline, wherein the output values are indicative of a blend of a plurality of textures with a single pixel when the combiner stage operates in a first mode, and the output values are indicative of a blend of an individual texture with two pixels when the combiner stage operates in a second mode.

Abstract: A rendering apparatus has an image generation unit for generating a source image, an address generation unit for generating the read and write addresses of a bitmap memory, a DMA read unit for directly reading out data from the bitmap memory in accordance with the generated address, an input data holding unit for holding the data read from the bitmap memory, a logic operation unit for making a logic operation on the basis of the read data and data of the source image, an output data holding unit for holding the logically operated data, and a DMA write unit for writing the held data in the bitmap memory in accordance with the generated address, and synchronously processes a data input process for reading out data from the bitmap memory and holding that data in the input data holding unit, the logic operation, and an output process for writing the logic operation result at a predetermined address of the bitmap memory parallel to each other.

Abstract: A method and system for processing graphics data in a computer system are disclosed. The method and system including providing a general-purpose processor and providing a vector co-processor coupled with the general-purpose processor. The general-purpose processor includes an instruction queue for holding a plurality of instructions. The vector co-processor is for processing at least a portion of the graphics data using a portion of the plurality of instructions. The vector co-processor is capable of performing a plurality of mathematical operations in parallel. The plurality of instructions is provided using software written in a general-purpose programming language.

Abstract: The invention relates to a communication method for exchanging data between an operating device for a light source and a control device in the case of equipment for projecting images. Simple signals present are used to transmit complex information. The information is imaged in this case by the pulse duration or the amplitude of the signals.

Abstract: A method, graphics engine boolean logic unit and digital video system that provide a raster operation unit capable of providing a raster and non-raster operation function(s) is provided. The raster operation may simultaneously conduct a raster function and non-raster operation function(s) by modification of at least one of a rasterop code and a pattern operand. The invention saves considerable logic since different functions are no longer executed separately and then multiplexed.

Abstract: An image processing system comprises: a plurality of operation pipelines to operate an inputted image data; a switching channel to switch a data transfer path to input operation results, which are outputted from the plurality of operation pipelines, to the plurality of operation pipeline again; and a control circuit to control switching of the data transfer path by the switching channel and to control an operation in the plurality of operation pipelines, the control circuit carrying out a scheduling of a plurality of operations, which form (n−k+1) unit operations from a unit operation k (1<k<n) to a unit operation n (n is a positive integer) of unit operations 1 to n, the plurality of operations prevented from overlapping with each other at the same predetermined operation time in the same operation pipeline when a unit operation included in the plurality of operations is executed by the plurality of operation pipelines.

Abstract: A parallel processing processor for processing images including &agr; data indicative of pixel transparency. The parallel processing processor comprises: a plurality of execution units for executing in parallel arithmetic and logical operations under control of a single instruction; general purpose registers which are connected to the execution units via a data path, which input data to the execution units and which receive results of operations from the execution units; &agr; data dedicated registers which are connected to the execution units via another data path and which input data to the execution units; and a control circuit for directing data from the general purpose registers and &agr; data dedicated registers into each of the execution units under control of a single instruction.

Abstract: A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

Abstract: A method, apparatus and system for storing data wherein pieces of data are selectively combined at times when a storage device is not able to accept requests to store data for a duration sufficient that multiple additional pieces of data have been received since the last request to store data was made and at least two of those pieces of data are able to be combined into a piece of data that is better configured for storage.

Abstract: The object is to increase the efficiency of processing by conferring the residual image function on hardware and to provide an image processing device wherein processing is implemented at higher speed. In an image processing device equipped with an image memory and a control section that writes generated image data to the image memory, there is provided a blend circuit that reads image memory or image data from image memory and attenuates the read image data and that writes this together with newly generated image data into another image memory, thereby producing a residual image effect.

Abstract: The invention provides a method of generating cache indexes that reduces the likelihood that adjacent addresses will map to the same cache regions. The hashing process is optimized to be sensitive to small changes in the input data so that similar sets of input data will preferably not result in the same or even similar output data. Memory accesses of the sort performed when rendering graphical images may involve numerous accesses to relatively similar memory locations Therefore, hashing of the index values that determine where the information from the memory locations will be stored while that information is in cache decreases the likelihood of similar memory locations being stored at the same cache location. Consequently, cache efficiency and performance is improved.

Abstract: The occurrence of an (n+m) input operand instruction that requires more than n of its input operands from an n-output data source is recognized by a programmable vertex shader (PVS) controller. In turn, the PVS controller provides at least two substitute instructions, neither of which requires more than n operands from the n output data source, to a PVS engine. A first of the substitute instructions is executed by the PVS engine to provide an intermediate result that is temporarily stored and used as an input to another of the at least two substitute instructions. In this manner, the present invention avoids the expense of additional or significantly modified memory. In one embodiment of the present invention, a pre-accumulator register internal to the PVS engine is used to store the intermediate result. In this manner, the present invention provides a relatively inexpensive solution for a relatively infrequent occurrence.

Abstract: A high-performance band combine function to transform a source image of n bands to a destination image of m bands. A source image vector is multiplied with a transformation matrix having n+1 columns and m rows. The values in the transformation matrix may be user-selected. The product of the source image and the transformation matrix is a destination image vector. The destination image vector may be displayed on a computer monitor. To perform the function in a digital system, the pixels of the source image are converted to a partitioned format. The source image is multiplied with the transformation matrix values using partitioned arithmetic. In the digital system, a plurality of partitioned arithmetic operations may be performed in parallel.

Abstract: A method and apparatus are provided for a lighting system for graphics processing. Included is a plurality of input buffers adapted for being coupled to a transform system for receiving vertex data therefrom. The input buffers include a first input buffer, a second input buffer and a third input buffer. An input of the first buffer, the second input buffer and the third input buffer are coupled to an output of the transform system. Further included is a multiplication logic unit having a first input coupled to an output of the first input buffer and a second input coupled to an output of the second input buffer. An arithmetic logic unit has a first input coupled to an output of the second input buffer. The arithmetic logic unit further has a second input coupled to an output of the multiplication logic unit. An output of the arithmetic logic unit is coupled to the output of the lighting system.

Abstract: A tile-oriented graphics processing system in which an additional level of caching is provided locally, at the output of a patch-processing graphics computation block. This additional local storage buffers the current tile, so that repeated accesses to the same tile can avoid pipelining delays connected with access to the main cache. (Even an on-chip cache, in a large chip, can impose access delays which are significant in relation to the computation speeds involved.

Abstract: A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

Abstract: A method and circuit for determining the address of texture maps in memory, when only the base address of the primary texture map is known. The various maps associated with a given texture are sized and stored in a manner that allows any texel in any of the maps to be located based on the map number and the base address of the primary map. A circuit is provided that determines the necessary addresses with minimal calculations.

Abstract: A graphics memory system for managing image data for a volumetric display that displays volumetric images, the system including a first buffer memory with a first predefined address space for holding image data for a three-dimensional image; a second buffer memory with as second predefined address space for holding image data for a three-dimensional image, wherein the first and second predefined address spaces are the same; and a voxel router in communication with both the first and second buffer memories, wherein the voxel router is configured to use a selectable one of the first and second buffer memories as an active memory out of which stored image data is to be read for display on the volumetric display and to use the other of the first and second buffer memories as an inactive memory into which image data is to be written.

Abstract: The present invention is generally directed to a system and method for performing accumulation buffer operations using texture mapping hardware. In accordance with one aspect of the invention, a method is provided that operates by allocating a texture map of equal size as a display screen and copying contents of a frame buffer to the allocated texture map. The method then identifies an accumulation buffer operation and performs the accumulation buffer operation in a fragment unit. Preferably, the fragment unit includes an arithmetic logic unit (ALU) to perform high-speed mathematical operations. Finally, the method directs results of the accumulation buffer operation to the frame buffer, and copies contents of the frame buffer to the allocated texture map.

Abstract: A digital differential analyzer (DDA) with parallel processing paths. The parallel processing paths can be provided through the use of a pipeline in which some of the input data registers are implemented with double buffers. Each double buffer includes an external register that corresponds to a setup path and an internal register that corresponds to a render path. While the rendering phase is being performed for the current primitive using the internal registers, the setup phase for the next primitive can be performed and the external registers can be updated. The two paths are synchronized with a prepare-to-render message. The DDA can include multiple arithmetic units to allow concurrent processing of multiple fragments of an object. The elements within the DDA (e.g., the internal registers, multiplexers, output registers, and so on) can be configured to provide more efficient implementations of scan conversion and subpixel correction than those of conventional DDAs.

Abstract: A graphic processor including a rendering control circuit which carries out weighted averaging on pieces of pixel data of source image information arranged to form a pixel-data matrix corresponding to a pixel matrix with columns of the pixel-data matrix being oriented perpendicularly to a scanning direction in order to compute a weighted average of pieces of pixel data on rows of the pixel-data matrix adjacent to each other and on a column of the pixel-data matrix perpendicular to the scanning direction in so-called blend processing. The rendering control circuit reads out pieces of pixel data from the pixel-data matrix sequentially in a direction perpendicular to the scanning direction and computes a weighted average of the pieces of data. Image data subjected to blend processing is displayed by adopting an interlace scanning technique thereby eliminating undesired flicker.

Abstract: A method and apparatus for performing scan conversion in a computer graphics display system to determine pixel locations in screen space which correspond to a primitive being scan converted. The apparatus of the present invention comprises logic configured to convert a primitive into pixel locations in screen space. The logic, which is referred to hereinafter as the hierarchical tiler, subdivides the screen space into a plurality of regions, each of which comprises a plurality of pixel locations in screen space. The hierarchical tiler then determines whether a particular one of the regions is entirely outside of the primitive, entirely inside of the primitive, or partially inside of the primitive. If the hierarchical tiler determines that a particular region is entirely inside of the primitive, it converts the particular region into pixel locations in screen space.

Abstract: An information processing apparatus secures a wide band width in a graphics bus and draws graphics at high speed and low cost. The apparatus employs graphics processing units connected in parallel. Each of the units is formed on a chip and has a graphics processor and a graphics memory, to provide color information and select information. The outputs of the units are selected through a tournament.

Abstract: A system, method and computer program product are provided for a hardware implementation of a blending of “skinning,” during graphics processing in a graphics pipeline. During processing in the pipeline, a plurality of matrices and a plurality of weight values are received. Also received is vertex data to be processed. A sum of a plurality of products may then be calculated by the multiplication of the vertex data, one of the matrices, and at least of the weights. Such sum of products is then outputted for additional processing.

Abstract: A method used to test the correctness of image data transited between the system memory and display memory is described as follows. First, a image data A is stored in a location B of the system memory. Then, the data of image A and a location C of display memory are stored into a Bitblt temporary storage means. The Bitblt engine is used to transit the data of image A stored in the location B of system memory to the location C of display memory. Then, the data of location C, location D of display memory, and image A are input into the Bitblt temporary storage means. The Bitblt engine is used to transit the data of image A from the location C to the location D of display memory. The data of image A and location E are input into the Bitblt temporary storage means. The Bitblt engine is used to transit the data of image A from the location D into the location E of the system memory.

Abstract: A clear color and count are stored in a frame buffer controller and in a video controller. The image buffer is cleared by writing the clear color into a color bit field and the count into a count bit field of each pixel. For each frame drawn, the count bit field of each pixel modified is updated with the count stored in the frame buffer controller. The counts stored in the frame buffer controller and the video controller are incremented with each new frame. When the counts reach maximum, the process repeats. Each time a pixel is read, the pixel's color bit field is replaced with the stored clear color if the pixel's count bit field is not equal to the stored count. The color bit field and the count bit field may be part of the same word of frame buffer memory. Or, the count value may be stored in an alpha bit field in lieu of an alpha value.

Abstract: A method, apparatus and article of manufacture are provided for a transform system for graphics processing as a computer system or on a single integrated circuit. Included is an input buffer adapted for being coupled to a vertex attribute buffer for receiving vertex data therefrom. A multiplication logic unit has a first input coupled to an output of the input buffer. Also provided is an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit. Coupled to an output of the arithmetic logic unit is an input of a register unit. An inverse logic unit is provided including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation. Further included is a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit. In use, the conversion module serves to convert scalar vertex data to vector vertex data.

Abstract: A command parser 308 is coupled to an incoming data stream to insert an end of state token at the end of a group of state data 480 and an end of primitive token at the end of a group of primitive data 484 to create a parsed data stream. The parsed state data stream is transmitted to a state controller 420 which loads state data 480 into shadow stages 412. The state controller 420 validates a shadow stage 412 upon receiving an end of state group token. The parsed primitive data 484 are also transmitted to primitive controllers 424. The primitive controllers 424 prevent primitive data from being transmitted into a processing element 464 responsive to receiving an end of primitive_B token. Upon receiving an end of primitive_E token, the primitive controller 424 ascertains whether the first shadow stage 412 has been validated.

Abstract: A method and apparatus for blending textures and other operands in a video graphics system using a single blend unit is accomplished through the following steps. A first set of control information is received. A first portion of the first set of control information is sued to select a first blend operand, which is preferably a texture in a graphics processing system. A second blend operand is selected based on a second portion of the first set of control information. The first and second blend operands are combined using an operation selected by a third portion of the first set of control information. The combination of the first and second blend operands produces a first combination result. A second set of control information is received, and a first portion of the second set of control information selects a third blend operand. The first combination result is then selected as a fourth blend operand using a second portion of the second set of control information.

Abstract: Palettized image data for two or more images, represented by color lookup table (CLUT) indices, are mapped to an index space. Blended pixels are generated from the pixels in the index space using alpha blending. The blended pixels are mapped back to CLUT indices to generate palettized blended image data. In a preferred embodiment, in which the CLUT is generated based on a characterized structure in YUV space, the CLUT indices are mapped to Y and UV indices in a YUV index space. The Y and UV indices are then used to generate three-coordinate blended pixels. The three-coordinate blended pixels are then mapped back to CLUT indices of a palettized blended image. Table lookups are used to generate the blended pixels from the Y and UV indices and to map the blended pixels back to CLUT indices.