Abstract: A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Abstract: An original media object, such as an image, is edited without loss of the data comprising the media object. Changes applied to the media object are defined by metadata associated with the media object. For example, metadata define the cropping of an original JPEG image without loss of the original image. The metadata from a previous editing session can be used to further revising a change to the media object. Preferably, the metadata are stored as a stream in a substorage of an object linking and embedding (OLE) file. For display purposes, and for ease of modification, an edited version of the media object is stored as another stream of data in the substorage of the OLE file. The edited version of the media object is preferably compressed and serves as an intermediate object for faster display during editing and as a surrogate if the original media object is unavailable.

Abstract: A method and computer program are provided for controlling access to a memory device wherein, even with a complex data storage structure, access is made to memory areas within the memory device with a minimal number of selection inputs required for selection of a desired memory area.

Abstract: A method of addressing multistable nematic liquid crystal devices, in particular bistable nematic liquid crystal devices is provided. The method is a line at a time addressing scheme where one of at least two data waveforms is applied simultaneously to each of the column electrodes whilst a strobe waveform is applied to a row. The strobe waveform comprises a blanking portion sufficient to cause the liquid crystal material to blank, irrespective of which data waveform is applied, immediately followed by a discriminating portion which is such that in combination with an appropriate data waveform allows for selective latching. At least part of both the blanking portion and the discriminating portion are applied during the line address time for the particular row of interest.

Abstract: A memory controller is coupled to a memory device via a memory channel. The memory controller includes a command-per-clock detection unit that compares a portion of a current address with a portion of a previous address. If there is a match, then the memory controller can continue to assert a chip select line coupled to the memory device. The command-per-clock detection unit checks to see whether only certain low-order bits of the address lines are toggling between the current and previous addresses. Additional copies of address lines for particular low-order bits are provided to the memory device to reduce loading on the low order bit address lines, allowing the low order bit address lines to toggle quickly in order to avoid the necessity of inserting a one clock period wait state. If the command-per-clock detection unit does not find a match (meaning that more than the low order address bits are toggling) then the wait state is inserted by deasserting the chip select line for a clock period.

Abstract: In a computer system, an address range is defined within the memory map. Addresses within the address range are mapped to other addresses within the memory map using an address relocation mechanism (e.g. the GART mechanism). The address range is divided into two portions. A graphics device may use the first portion to address a contiguous address space, and the addresses are remapped to other address using the address relocation mechanism. Particularly, the contiguous address space used by the graphics device may be remapped to non-contiguous pages elsewhere in the memory map. Other peripheral devices may use the second portion when performing data transfers to portions of the memory map above a predefined limit. The predefined limit may be the highest memory location in the memory map for which the peripheral device is capable of directly generating the address (e.g. 4 GB for a 32 bit address).

Abstract: Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.

Abstract: A system and method are disclosed for reproducing a pre-selected larger 2-D sample location pattern from a smaller one by means of X,Y address permutation. This method, for example, allows hardware to effectively reproduce a pre-selected set of sample locations for an array of 128×128 sample bins from a smaller set of pre-selected sample locations for an array of 2×2 sample bins. A permutation logic unit may use a first portion of an address for a sample bin B to identify a corresponding 2-D transformation, apply the inverse of the transformation to a second portion of the sample bin address to identify the corresponding bin of the 2×2 array of sample bins, and apply the transformation to the sample locations stored in the corresponding bin to reproduce the sample locations pre-selected for sample bin B.

Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: A method for antialiased imaging of graphical objects on a pixel oriented display by rasterizing input pixel data as virtual pixels into a memory with a virtual resolution that is a factor higher than the physically displayed pixel resolution. In accordance with the invention, the existing color value of the physical pixel that corresponds to a virtual pixel to be modified is retrieved from the memory, the input color value of said virtual pixel to be rasterized is derived from the pixel input data, and split in its basic red, green and blue color components. The existing and the input color value are linearly combined for each color component in accordance with: ((N−1)*existing color value+M*input color value)/N, in which M represents a value at least equal to one and N being R2, and the result thereof used to overwrite the existing color value of the physical pixel at the memory location of said physical pixel.

Abstract: A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine generated, and also enables the decoder to calculate on the fly which driver lines to stimulate in response to each address value. Furthermore, different resolutions may be provided to enable groups of the electrodes to be addressed simultaneously. Such a decoder arrangement may also be used with an electrode arrangement in which each electrode is connected to only two of the driver lines, in order to achieve addressing schemes in which up to t consecutive electrodes can be driven simultaneously. The invention is applicable, for example, to liquid crystal displays, arrays of memory elements and arrays of sensors such as light-sensors.

Abstract: An address relocation cache includes a plurality of entries. Each of the plurality of entries is configured to store at least a portion of an input address, at least a portion of an output address to which the input address translates, and a destination identifier corresponding to the output address. An input address may be translated to the output address and the corresponding destination identifier may be obtained concurrently for input addresses which hit in the address relocation cache. If an input address misses in the address relocation cache, a translation corresponding to the address may be located for storing into the address relocation cache. The output address indicated by the translation may be passed through the address map to obtain the destination identifier, and the destination identifier may be stored in the address relocation cache along with the output address.

Abstract: A system and method are disclosed for reproducing a pre-selected larger 2-D sample location pattern from a smaller one by means of X,Y address permutation. This method, for example, allows hardware to effectively reproduce a pre-selected set of sample locations for an array of 128×128 sample bins from a smaller set of pre-selected sample locations for an array of 2×2 sample bins. A permutation logic unit may use a first portion of an address for a sample bin B to identify a corresponding 2-D transformation, apply the inverse of the transformation to a second portion of the sample bin address to identify the corresponding bin of the 2×2 array of sample bins, and apply the transformation to the sample locations stored in the corresponding bin to reproduce the sample locations pre-selected for sample bin B.

Abstract: Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.

Abstract: The AGP graphics card queries the system to determine whether the chipset is symmetric or asymmetric. If the chipset is symmetric and other devices can access the graphics address re-mapping table, the graphics aperture is reserved from the system memory. Other devices are denied access to the portion of the system memory reserved for the graphics aperture. The graphics address re-mapping table is then filled to map input addresses in the graphics aperture to identical output addresses. If the chipset is asymmetric and only the Accelerated Graphics Port graphics card can access the graphics address re-mapping table, no system memory is reserved for the graphics aperture, and other devices can access the portion of memory whose addresses are used by the graphics aperture. Then, as the graphics aperture needs additional memory blocks, they are allocated from the system, and input addresses are mapped to the allocated memory blocks within the graphics address re-mapping table.

Abstract: A method and apparatus for compressing parameter values for pixels within a frame is accomplished by first grouping pixels in the display frame into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. For at least one of the pixel blocks, the parameter values for the pixel block are translated into a column-wise differential slope representation that represents the parameter values as a plurality of reference points, a plurality of slopes, and a plurality of slope differentials. The column-wise differential slope representation is then transformed into a planar differential slope representation that reduces the representation of the plurality of reference points and the plurality of slopes to a single reference pixel value, two reference slopes, and a plurality of slope differentials.

Abstract: The present invention relates a texture mapping system which can access texture data in parallel. The texture mapping system includes: a memory controller; a main memory storing filtered texture images; a cache memory receiving data of the texture image from the main memory, and separately storing texture data in odd-number columns and even-number columns; a texture address converter converting an address from the memory controller, and generating a read/write address of the cache memory; and an interpolator interpolating the texture data outputted from the cache memory, and forming a pixel data. Accordingly, when the texture data is mapped according to a bi-linear filtering method and the like in the three-dimensional graphic system, the cache memory is accessed as many as a half of the number of the necessary texture data, thereby improving the graphic performance.

Abstract: In order to enable the gentlest possible scrolling of an image to be presented on a display unit, without restricting the scrolling range and with a low outlay, an image area is defined that is larger than the image area that can be presented on the display unit. This larger image area is subdivided into a number of image area sections to which the image data of a corresponding memory section of a frame buffer provided for storing the image data of the image area are assigned by means of corresponding address information items.

Abstract: A serial access memory having a first memory cell array and a second memory cell array. The serial access memory is provided with a control circuit for controlling the Most Significant Bit (MSB) of an address supplied to each of the first and second memory cell arrays. The control circuit causes the operations of circuits in the first memory cell array to become identical to those of circuits in the second memory cell array, thereby making it possible to read data at a high speed. An STN type LCD including the serial access memory, has a display device that facilitates production of memory maps in the memory cells without a need for externally-mounted elements such as a multiplexer.