Abstract: When television screen setting is not set and thus a television screen setting completion flag is not set, and a terminals-connection judgment pin takes a low level, an i/p selection screen is initially displayed on a progressive display device. However, the i/p selection screen is not displayed on an interlaced display device. When processing performed for the i/p selection screen is completed, or when the terminals-connection judgment pin takes a high level, indicating that the video input D-terminal of the display device is not connected to the video output D-terminal, an aspect ratio setting screen is displayed. After aspect ratio setting is completed, the television screen setting completion flag is set. This eliminates the need to perform the television screen setting again.

Abstract: Uncompressed video information is transmitted over a wireless communication medium from a wireless sender device to a wireless receiver device. Progressive transmission data rate adaptation is performed on original uncompressed video pixel information. The progressive transmission data rate adaptation is performed on selected pixel information to obtain a rate-reduced pixel information. The rate-reduced pixel information requires a lower transmission data rate than the original frame. The rate-reduced pixel information is transmitted over the wireless communication medium to the wireless receiver device. At the receiver, a reverse operation is performed to recover the original uncompressed video pixel information.

Abstract: An image conversion apparatus and method for converting a progressive image into an interlaced image in an image processing system are provided. A controller determines a number of frames to be used to convert a progressive image into an interlaced image. A converter generates an interpolated image for the progressive image according to the determined number of frames, and converts the progressive image into an interlaced image using the interpolated image.

Abstract: The present invention provides a system and method for processing a High Definition Television (HDTV) image. Specifically, the system and method of the present invention provides a plurality of programmable encoders connected in parallel and directly (i.e., gluelessly) attached to a HDTV video source. The system and method of the present invention allows a fall HDTV image to be received by each encoder at 74.25 MHz directly from the HDTV video source. Based on programming, each encoder will process only a portion of the full image.

Abstract: An imaging apparatus includes an imaging section which captures an object to obtain a first image signal of interlace scan type, a motion vector detection section which detects a motion vector by use of the first image signal, a vibration correction section which corrects, according to the motion vector detected by the motion vector detection section, vibration of an object image included in the first image signal, and a conversion section which converts, according to the motion vector detected by the motion vector detection section, the first image signal to a second image signal of progressive scan type.

Abstract: A moving image processing apparatus, includes a low-speed clock generation source to generate a low-speed clock signal of a first frequency, a high-speed clock generation source to generate a high-speed clock signal of a second frequency which is higher than the first frequency, an image data source to output progressive-type image data, a PI converter to convert the progressive-type image data output from the image data source into interlaced-type image data forming a field and to output the interlaced-type image data, and an arithmetic part to process the interlaced-type image output from the PI converter by use of only one of a pair of fields each formed by the interlaced-type image output from the PI converter. The high-speed clock generation source supplies the high-speed clock signal to the image data source and the PI converter, and the low-speed clock generation source supplies the low-speed clock signal to the arithmetic part.

Abstract: The invention is related to methods and apparatus that can advantageously alter a playback rate of a multimedia presentation, such as a video clip. One embodiment of the invention permits a multimedia presentation to be sped up or slowed down with a controlled change in pitch of the sped up or slowed down audio. In one embodiment, this controlled change in the pitch permits the sped up or slowed down audio to retain a same sounding pitch as at normal playback speeds. In one embodiment, a duration is specified and playback of the video clip is advantageously sped to complete playback within the specified duration. In another embodiment, a finish by a time is specified, and the playback of the video clip is advantageously sped to complete playback by the specified time.

Abstract: A memory sharing method provided, comprising determining a type of an input video signal, sharing an SRAM (static random access memory) pool among at least two different processing units of the video system, wherein the SRAM pool comprises a plurality of SRAM units having different sizes, and an SRAM unit size is determined as a common factor of memory sizes required by at least two processing units, and allocating a combination of SRAM units in the SRAM pool to each processing unit processing the input video signal according to the type of the input video signal.

Abstract: One embodiment disclosed relates to the use of object motion estimation to interlace a progressive video sequence. One of a plurality of consecutive frames is segmented and motion vectors for each segment are determined though object motion estimation. Interpolated motion vectors are used to construct at least one intermediate frame, and interlaced fields are extracted from the new sequence of frames that includes intermediate frames. An interlaced sequence with smooth, incremental motion is thus constructed from a progressive video sequence.

Abstract: Systems and methods are provided for receiving and encoding 3D video. The receiving method comprises: accepting a bitstream with a current video frame encoded with two interlaced fields, in a MPEG2, MPEG4, or H.264 standard; decoding a current frame top field; decoding a current frame bottom field; and, presenting the decoded top and bottom fields as a 3D frame image. In some aspects, the method presents the decoded top and bottom fields as a stereo-view image. In other aspects, the method accepts 2D selection commands in response to a trigger such as receiving a supplemental enhancement information (SEI) message, an analysis of display capabilities, manual selection, or receiver system configuration. Then, only one of the current frame interlaced fields is decoded, and a 2D frame image is presented.

Abstract: A video signal display system includes: a reproducing apparatus including a decoder that decodes input video data to produce a video signal, an IP converter that, when the video signal produced by the decoder is an interlaced video signal, converts the interlaced video signal into a progressive video signal, a pseudo-interlacing unit that performs pseudo-interlacing in which the progressive video signal converted by the IP converter undergoes pseudo-interlacing so that the progressive video signal is converted into a pseudo-interlaced signal, and a first controller; and a display apparatus including a display processor that carries out a display process for displaying a video signal, and a display that can at least display the video signal that has undergone the display process in the display processor.

Abstract: A sum of pixel values of pixels corresponding to respective two scanning lines of 1 and 2, 3 and 4, 5 and 6, . . . of progressive-input image data in the order of scanning lines is output for the first frame, and a sum of pixel values of pixels corresponding to respective two scanning lines of 2 and 3, 4 and 5, 6 and 7, . . . of the image data is output for the second frame, sequentially in time series, repeatedly for each frame.

Abstract: A method and apparatus are provided for displaying progressive material on an interlaced display where the number of lines of the source frame is equal to or less than the number of lines in a display field, where such lines in the display field are derived from all of the lines of the source frame.

Abstract: A method for scaling subpicture data comprises receiving a video data stream and a subpicture data stream; pre-parsing the subpicture data stream to obtain line information of subpicture data, the subpicture data containing both top field pixel data and bottom field pixel data; calculating the number of lines contained in the top field pixel data and the bottom field pixel data from the pre-parsed line information; interlacing the top field pixel data and the bottom field pixel data; and scaling the top and bottom field pixel data together in interlaced form for adjusting the number of lines contained in the top field pixel data and the bottom field pixel data.

Abstract: A video signal transformation method and device for adapting display devices to heterogeneous signal formats, the method comprising the steps of: detecting a source video signal and the display format of a display device; and transforming the source video signal into the format of the display device for using the transformed video signal as the input of the display device while the source video signal is not conformed with the format of the display device. In addition, the device includes a detection device and a processing device, wherein this detection device detects the source video signal and the display format of the display device, whilst the processing device configured to convert the source video signal and output it to at least one corresponding display device, whereby a method and device for outputting various video signals can be achieved, and avoid users from the trouble at the time of transition period of display system.

Abstract: Methods and systems for the efficient and non-redundant transmission of a single video program in multiple frame rates, optionally employing a combination of video coding standards, in a way that is backwards-compatible with legacy receivers only supportive of some subsection of frame rates or of some subsection of video coding standards.

Abstract: Methods and systems for the efficient and non-redundant transmission of a single video program in multiple frame rates, optionally employing a combination of video coding standards, in a way that is backwards-compatible with legacy receivers only supportive of some subsection of frame rates or of some subsection of video coding standards.

Abstract: Methods and systems for the efficient and non-redundant transmission of a single video program in multiple frame rates, optionally employing a combination of video coding standards, in a way that is backwards-compatible with legacy receivers only supportive of some subsection of frame rates or of some subsection of video coding standards.

Abstract: Methods and systems for the efficient and non-redundant transmission of a single video program in multiple frame rates, optionally employing a combination of video coding standards, in a way that is backwards-compatible with legacy receivers only supportive of some subsection of frame rates or of some subsection of video coding standards.

Abstract: Disclosed herein is a time code processing apparatus including a time code reading section configured to read each of the first time code values; a phase detection section configured to detect a phase in a sequence of the pulldown process; and a time code generation section configured to use the first time code value as the second time code value when both the phase detected by the phase detection section and the first time code value obtained by the time code reading section have changed, and generate the second time code value while performing an interpolation based on the first time code value when at least one of the phase detected by the phase detection section and the first time code value obtained by the time code reading section has not changed.

Abstract: A double rate processing part generates, at a double rate, a non-interlaced image signal every frame to twice generate a double-rate non-interlaced signal which has identical information duplicately. An interlace part, after a predetermined process is carried out on the double-rate non-interlaced signal twice generated by the double rate processing part, extracts an odd scan lines from one of the twice generated double-rate non-interlaced signal to generate an odd scan line image signal, extracts an even scan lines from the other of the twice generated double-rate non-interlaced signal to generate an even scan line image signal, so as to obtain an interlaced image signal for one frame.

Abstract: Techniques for performing combined scaling, filtering, and/or scan conversion are disclosed that reduce the amount of line buffer space required in the overall design of a video processing system. In particular, coefficients from all or a sub-set of the scaling, filtering (smoothing/sharpening), and scan conversion filters are combined into one representative coefficient that can be applied in a single generic algorithm. Thus, implementation costs are reduced, particularly in a system-on-chip implementations.

Abstract: In an arrangement for processing video signals provided as interlaced video signals generated in the interlaced scanning mode, in which two fields constitute one frame, and/or as pseudo-interlaced video signals derived from non-interlaced video signals obtained by means of progressive scanning, flexible use of the arrangement with a minimal number of components for this arrangement is achieved in that at least one video signal-processing unit (1) is provided which receives at least an interlaced video signal or at least a pseudo-interlaced video signal and processes these video signals in dependence upon control data generated by means of a control unit (2), and in that a clock generator (4) is provided which controls the control unit (2) and/or the video signal-processing unit (1) in such a way that, when processing an interlaced video signal or a pseudo-interlaced video signal, possibly new control data are generated and/or taken into account as from the start of its next field or its next frame, respective

Abstract: Display structures and methods are provided that introduce redundancy and use this redundancy with different mapping rules on different interleaved display lines to visually diffuse display artifacts. The artifacts are typically produced by errors in the transmission and recovery of analog display signals that subsequently drive digital displays. This visual diffusion substantially reduces the display artifacts and, because these visual improvements require only one element (an ADC) in the display system to be configured at a higher resolution, the visual advantageous are realized with relatively low cost.

Abstract: Apparatus for display processing includes a host interface, which is arranged to accept graphical information from a first computer. A first display head is arranged to produce a first digital video signal including first frames representing the graphical information at a first frame rate, for displaying the graphical information on a local display of the first computer. A second display head is arranged to produce a second digital video signal including second frames representing the graphical information at a second frame rate that is lower than the first frame rate. A video redirection module is arranged to regulate a transmission rate of the second digital video signal from the second display head, to capture the second frames that are generated by the second display head and to forward the captured frames to a second computer.

Abstract: A method is provided for displaying progressive video content on an interlaced display device. The method comprises vertically phase shifting video lines of the progressive video content to correctly position the video lines with respect to a video field of the interlaced display device. The method further comprises scaling the video lines of progressive video content to match a vertical size of a video field of the interlaced display device.

Abstract: A workstation for processing and producing a video signal comprises a video input system, a video graphics processor, and a video output system. The video input system may comprise a video input module, a first video pipeline, and a second video pipeline. The video output system may comprise a receiver, a video pipeline and a video output module. In addition, the video input system may comprise a video input module having a specific configuration and a video processing module having a connector for coupling the video input module, the specific configuration of the video input module setting the characteristics of the video processing module. The video output system may comprise a video processing module having a connector for coupling a video output module and a video output module having a specific configuration, the specific configuration of the video output module setting the characteristics of the video processing module.

Abstract: A workstation for processing and producing a video signal comprises a video input system, a video graphics processor, and a video output system. The video input system may comprise a video input module, a first video pipeline, and a second video pipeline. The video output system may comprise a receiver, a video pipeline and a video output module. In addition, the video input system may comprise a video input module having a specific configuration and a video processing module having a connector for coupling the video input module, the specific configuration of the video input module setting the characteristics of the video processing module. The video output system may comprise a video processing module having a connector for coupling a video output module and a video output module having a specific configuration, the specific configuration of the video output module setting the characteristics of the video processing module.

Abstract: An apparatus (24) is provided for interlacing a plurality of input images (I0, I1) to form an output image (O). The interlacing apparatus (24) comprises a programmable memory (20) for storing one or more interlacing configuration patterns (P1, P2 and P3) which define a mapping from pixels of the input images (I0, I1) to pixels of the output image (O). The interlacing apparatus (24) also comprises a pixel data rearranger or interlacer (16) for rearranging pixel data in accordance with a pattern (P) stored in the memory (20). A pattern controller (18) is provided for selecting any one of the patterns (P1, P2 and P3) for use in the interlacer (16). Such an interlacing apparatus (24) can be used to drive a display device such as a multiple view directional display device or an autostereoscopic display device. A deinterlacer, an image compressor and an image decompressor are also provided.

Abstract: In the scanning conversion apparatus, a first converter converts input interlaced scan data into progressive scan data, and a second converter converting the progressive scan data output from the first converter to interlaced scan data.

Abstract: One embodiment disclosed relates to the use of object motion estimation to interlace a progressive video sequence. One of a plurality of consecutive frames is segmented and motion vectors for each segment are determined though object motion estimation. Interpolated motion vectors are used to construct at least one intermediate frame, and interlaced fields are extracted from the new sequence of frames that includes intermediate frames. An interlaced sequence with smooth, incremental motion is thus constructed from a progressive video sequence.

Abstract: The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit 8 for outputting the data from the memory 7 at a third transfer rate. The transfer rate between the memories 3, 7 and the memory 5 is twice as fast as the first or third transfer rate, whichever is faster, and the memories 3 has data storage capacities greater than an amount of the data to be written into the memory 5 in each write period, and the memories 7 has data storage capacities greater than an amount of the data to be read from the memory 5 in each read period.

Abstract: Techniques to switch between video display modes are described. An apparatus may include a graphics device to generate first synchronized timing signals with a first phase differential to indicate a first display mode for first display data, and to generate second synchronized timing signals with a second phase differential to indicate a second display mode for second display data. Other embodiments are described and claimed.

Abstract: A video signal processing apparatus includes a main picture processor, an interlace recovering module and a video encoder. The main picture processor produces corresponding main picture signals based on video signals from a memory. The main picture signals are converted to progressive scan signals through a predetermined video signals processing. The interlace recovering module receives the progressive scan signals, retrieves the even portion and the odd portion of the progressive video signals alternately, and generates a set of interlace-scan signals. The video encoder receives both the progressive scan signals and the interlace scan signals and generates a set of progressive video signals and a set of interlace video signals to corresponding video display apparatuses. Thereupon, the video reproduction system can simultaneously provide both the progressive video signals and interlace video signals to the video display apparatuses.

Abstract: A methodology and structure is described for processing a video signal comprising a plurality of fields. Each of the fields of the video signal are partitioned into a plurality of regions. Statistical measurements are then performed on each field to detect a field-level temporal periodic pattern and on each region within the fields to detect a region-level temporal periodic pattern. The regions in each field are then processed using the field-level temporal periodic pattern and the region-level temporal periodic pattern.

Abstract: Data intended to be displayed on a higher resolution display such as a non-interlaced display used as a computer monitor may be converted for display on a lower resolution display such as an interlaced display. The conversion may be done in a way that preserves the intended frame format while enhancing readability. For example, in one embodiment, the frames intended for non-interlaced display may be preserved in size for display in the same frame format on a lower resolution interlaced display. Local magnification may be selectively implemented for particular regions to enhance the readability of those regions. Upon selection, such local magnification may provide pixel loss and color corrections in addition to local magnification. In this way the frame format may be preserved while enhancing readability.

Abstract: Signal processing device for providing multiple output images by processing input images of an interlaced video signal, comprising a temporal interpolater circuit (18) and a memory buffer (26, 27) connected to the temporal interpolater circuit. The memory buffer (26, 27)is arranged for storing at least part of a previous input image (11, 13) and a current input image (12). The temporal interpolater circuit (18) is arranged for receiving at least the previous and current input image from the memory buffer (26, 27) and for providing multiple interlaced or de-interlaced frame data (15) at temporal positions between the previous input image temporal position and the current input image temporal position.

Abstract: Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use in, for example, digital video compression systems and methods. Film material may be encoded as video material with an intended field polarity and an explicit 3:2 pull-down operation for interlaced display (e.g., a 30-frames-per-second display).

Abstract: An image display apparatus has an image display including scanning lines, modulation lines and display devices driven through the scanning lines and modulation lines, a scanning circuit for supplying a scanning signal to the scanning line, a modulating circuit for supplying a modulation signal to the modulation line, and a converting circuit for converting the number of scanning lines of an input image signal. In addition, a selecting section selects a scan method of any of a first scan method and a second scan method and a changing section changes a vertical scaling filter characteristic of the converting circuit in accordance with the selected scan method. The vertical scaling filter characteristic in the case of the first scan method is a characteristic having a weaker elimination effect on high frequency components as compared with the vertical scaling filter characteristic in the case of the second scan method.

Abstract: In an image sensing apparatus using a non-interlace scanning type image sensing element, image data as well as a signal indicating whether the image data is sensed in a mode which is suitable for sensing a moving image (field image sensing mode) or sensed in a mode which is suitable for sensing a still image (frame image sensing mode) are recorded in a recording medium. In reproducing the image data from the recording medium, in a case where the recorded image data is sensed in the frame image sensing mode and a moving image output is required, an interpolation filter controller controls an interpolation filter to generate and output field images interpolated between consecutive frame images on the basis of the reproduced even or odd line field image data of the two consecutive frame images, thereby obtaining a smooth moving image.

Abstract: The present invention provides a system, method and computer program product for reducing fill and improving quality of interlaced displays using multi-sampling. In an embodiment of the invention, a frame buffer for a interlaced display is filled. Initially, a first multi-sample of the first line of the first field is calculated. The bottom sub-pixels of the first multi-sample are the top sub-pixels of a multi-sample of the first line of the second field. The first multi-sample is written into the frame buffer. Then, a second multi-sample of the second line of the first field is calculated. The top sub-pixels of the second multi-sample are the bottom sub-pixels of a multi-sample of the first line of the second field. Also, the bottom sub-pixels of the second multi-sample are the top sub-pixels of the second line of the second field. The second multi-sample is written into the frame buffer.

Abstract: A de-interlacing methodology generates frames from interlaced video signals by incorporating data from multiple fields into an interpolation-based de-interlacing process. Pixels directly above and below a blank pixel location and pixels immediately before and after the blank pixel location (in the fields immediately preceding and following, respectively, the blank pixel field) can be used to interpolate a pixel value for the blank pixel location. The use of pixel data from multiple fields improves the resolution of the interpolation process, thereby improving output frame accuracy. Adjacent pixel values can also be adjusted to further improve the consistency of the visual display provided by the output frames.

Abstract: An image data conversion processing device including an issue unit, plural line storing units, and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines of the image data to be converted and the number of lines of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.

Abstract: A method for processing an image to convert a non-interlacing scan data into an interlacing scan data is disclosed. The method includes the steps of receiving a non-interlacing scan data, the non-interlacing scan data including plural pixels, replacing a color space value of a selected one of the pixels in the non-interlacing scan data with a combination of color space values of the selected one pixel and at least one adjacent pixel to obtain a blurringly filtered non-interlacing scan data, scaling the blurringly filtered non-interlacing scan data according to a specific algorithm, and converting the blurringly filtered non-interlacing scan data into an interlacing scan data. An image-processing device for converting a non-interlacing scan data into an interlacing scan data is also disclosed. The device includes a blurring filter, a scaler and a converter.

Abstract: A graphics controller for flicker filtering interlaced image data is provided. The graphics controller includes a buffer and a memory region. A flicker filter for reducing a flicker of a display presented through an interlaced scan is also provided. The flicker filter is configured to receive interlaced image data prior to any received image data being stored in the memory region. The flicker filter outputs filtered data defining a pixel. The filtered data is stored in the memory region such that two pixels can be output in one memory access to the memory region. Flicker filter enabling circuitry in communication with the buffer is provided. The flicker filter enabling circuitry is configured to supply an even segment and a corresponding odd segment of the interlaced image data to the flicker filter. An apparatus and methods for processing and storing image data having an interlaced format are also provided.

Abstract: The present invention discloses a method for driving a full-color LED display board with high resolution. It features three original color LED pixels that are arranged in a diamond pattern to form LED array, and an interlacing scan circuit is used to control the LED array. As a result, the display of a new pixel can be inserted between two contiguous pixels and the resolution of the full-color LED display board increases.

Abstract: A method and apparatus are provided for displaying progressive material on an interlaced display where the number of lines of the source frame is equal to or less than the number of lines in a display field, where such lines in the display field are derived from all of the lines of the source frame.

Abstract: An apparatus and method to delay a field of video by one row in a two field frame to reduce DC build-up or stick caused by textual image.

Abstract: Disclosed is an apparatus and method for image conversion and automatic error correction for a digital television receiver (TV) which can improve the picture quality by converting an image signal for a TV or PC that displays an image having an RGB format into an image signal of YPbPr for the digital TV and automatically correcting an error produced in the received image signal.

Abstract: The present invention provides a system, method and computer program product for reducing fill and improving quality of interlaced displays using multi-sampling. In an embodiment of the invention, a frame buffer for a interlaced display is filled. Initially, a first multi-sample of the first line of the first field is calculated. The bottom sub-pixels of the first multi-sample are the top sub-pixels of a multi-sample of the first line of the second field. The first multi-sample is written into the frame buffer. Then, a second multi-sample of the second line of the first field is calculated. The top sub-pixels of the second multi-sample are the bottom sub-pixels of a multi-sample of the first line of the second field. Also, the bottom sub-pixels of the second multi-sample are the top sub-pixels of the second line of the second field. The second multi-sample is written into the frame buffer.