Progressive To Interlace Patents (Class 348/446)
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Patent number: 6441857Abstract: An apparatus and method for converting pixel data from a computer video format to a television-compatible composite video waveform. A color space converter converts RGB or YCrCb pixel data into YUV pixel data. The YUV pixel data is supplied to an encoder which encodes the data into a composite video waveform. A clock generator generates an encoder clock frequency based on the horizontal resolution of the incoming computer pixel data. The encoder clock frequency is sufficient to allow encoding of all incoming pixels in the active video portion of the waveform without physically scaling or altering the pixel data. Sync and burst processors in the encoder encode sync pulses and burst waveforms at proper timing intervals despite the variable encoder clock frequency by accessing sync pulse and burst waveform values and timing parameters appropriate to ranges of clock frequencies that are stored in a ROM.Type: GrantFiled: January 28, 1999Date of Patent: August 27, 2002Assignee: Conexant Systems, Inc.Inventors: David J. Wicker, Benjamin E. Felts, III
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Patent number: 6442206Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.Type: GrantFiled: January 25, 1999Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventor: David A. Hrusecky
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Publication number: 20020113891Abstract: One disclosed embodiment comprises a vertical scaler receiving a first number of video lines at a first frequency. The vertical scaler outputs a second number of video lines at the first frequency. A FIFO has as an input from the vertical scaler the second number of video lines at the first frequency. The FIFO outputs the second number of video lines at a second frequency. Another disclosed embodiment further comprises a modulator/timing generator having as an input from the FIFO the second number of video lines at the second frequency. The second number of video lines can be in a first video format. The first video format can be a high resolution video format. The modulator/timing generator converts the second number of video lines in the first video format into a second video format. The second video format can be a low resolution video format.Type: ApplicationFiled: February 5, 2001Publication date: August 22, 2002Applicant: Conexant Systems, Inc.Inventor: Benjamin E. Felts
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Publication number: 20020101535Abstract: The television system for displaying images on a television display has a source of a series of video fields. An active de-interlacer receives first field data from a first field of the series of video fields and second field data from a second field of the series of video fields, and produces de-interlaced data and control data. A format converter has a vertical scaler then directly receives the de-interlaced data and produces vertically scaled data therefrom. The format converter also has a re-interlacer that receives the vertically scaled data and the control data, and produces a re-interlaced frame. A horizontal scaler is connected to receive the re-interlaced frame and to produce therefrom a horizontally scaled re-interlaced frame. Display drivers receive the horizontally scaled re-interlaced fame and produce therefrom television display signals for forming images on a television, a high definition television of other type of television display.Type: ApplicationFiled: January 29, 2001Publication date: August 1, 2002Inventor: Philip L. Swan
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Patent number: 6414718Abstract: The present invention relates to converting a video signal comprising input image samples conforming to an interlace scanning lattice into a video signal comprising output image samples conforming to a progressive scanning lattice. First and second temporal filters receive and divide the input image samples into first and second temporal sub-bands. First and second low-pass vertical filters vertically filter each temporal sub-band such that the higher temporal sub-band is vertically filtered to a greater degree than the lower temporal sub-band. The filtered image samples from each sub-band are combined to form a filter output signal and a re-sampler re-samples the filter output signal to form the output image samples.Type: GrantFiled: November 22, 1999Date of Patent: July 2, 2002Assignee: Tandberg Television ASAInventors: Stuart McDonald, Robert Beattie
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Patent number: 6414725Abstract: A data storage system is described that simultaneously stores incoming data in a plurality of different digital formats linked together to permit economical accessibility and browsing of stored content by providing user access to reduced-resolution versions of stored format. Synchronization information correlates the same content stored in different digital formats to provide a means to reflect an edit of content in one format to the content stored in the other formats without manual editing of content in each format.Type: GrantFiled: April 16, 1998Date of Patent: July 2, 2002Assignee: Leitch Technology CorporationInventors: Edsel A. Clarin, Hilton S. Creve, Richard A. Kupnicki, Mihai G. Petrescu, Todd S. Roth
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Publication number: 20020063793Abstract: A method of optimizing the display of an up-converted interlaced video frame signal from a received progressive video frame signal (11) comprises the steps of receiving a progressive video frame signal, decoding (12) the progressive video frame signal using an interpolation function (18) to provide an interpolated interlaced video signal, deinterlacing (14) the interpolated interlaced video signal, and deinterpolating (16) the deinterlaced interpolated interlaced video signal to provide an optimized progressive video frame signal (17).Type: ApplicationFiled: June 27, 2001Publication date: May 30, 2002Inventor: Donald Henry Willis
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Patent number: 6396542Abstract: A television receiver receives HDTV video signals and scan converts them to a lower line scanning rate with field-to-field interlace. This scan conversion is done to conserve the power consumption by the magnetic deflection system for the kinescope, which has a display screen with a 16:9 aspect ratio and a dot pitch for displaying a 480 scan line frame. The receiver receives scan converts NTSC video signals using time compression circuitry to present them in variants of letter-box form in which the images fill the full height of the display screen, but not its full width.Type: GrantFiled: August 2, 1996Date of Patent: May 28, 2002Assignee: Samsung Electronics Co., Ltd.Inventor: Chandrakant B. Patel
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Patent number: 6392706Abstract: A first interlaced video signal of a first number of scanning lines is converted into a second interlaced video signal of a second number of scanning lines. The first and second numbers are different from each other. The first interlaced video signal is converted into a first progressive video signal of the first number of scanning lines by interpolating the first interlaced video signal with scanning lines which have been decimated from the first interlaced video signal. The first number of scanning lines of the first progressive video signal is converted into the second number of scanning lines by re-sampling, to generate a second progressive video signal of the second number of scanning lines. The second progressive video signal is then converted into the second interlaced video signal by decimating the second number of scanning lines of the second progressive video signal.Type: GrantFiled: September 30, 1999Date of Patent: May 21, 2002Assignee: Victor Company of Japan, Ltd.Inventor: Kenji Sugiyama
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Publication number: 20020039147Abstract: A transforming device for transforming computer graphics signals to television signals is provided. The transforming device includes a scaled-down line generating unit that receives the computer vertical line and generates the scaled-down vertical line, a controller that receives the scaled-down vertical line, and a scaled-down buffer that stores the scaled-down vertical line or the value of the scaled-down vertical line performed by the weighted-averages method. The content of the scaled-down buffer is transmitted to a weighted-averages operation unit, and then it is performed by the weighted-averages method with the next scaled-down vertical line. When a TV line is generated, it is the output of the transforming device. The present invention has the advantage of reducing the needed buffers in the transforming process and thereby reducing the cost.Type: ApplicationFiled: September 28, 2001Publication date: April 4, 2002Inventors: Yi-Chieh Huang, Chun-An Lin
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Patent number: 6359653Abstract: A VGA to TV data transformation system uses a background-based adaptive flicker reduction method. Information in a picture displayed on a screen of a monitor is divided as graphic and video information. Graphic information which includes cursor, graphic data, and sub-picture of video data in video information is prone to flicker. A background-based adaptive flicker reduction is applied to pixels in regions containing graphic information. A current pixel and the adjacent pixels directly above and below the current pixel are used to compute Mean and Diff values. The background state of a current pixel is determined by comparing the Mean value with a threshold value. The background state, the Mean value and the Diff value are then used to select a flicker reduction mode that may be strong reduction, median reduction, mild reduction or no reduction. An anti-flicker pixel is generated according to the flicker reduction mode.Type: GrantFiled: June 22, 1999Date of Patent: March 19, 2002Assignee: Silicon Integrated Systems Corp.Inventor: Chien-Hsiu Huang
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Publication number: 20020018144Abstract: A signal processing apparatus and method up or down convert an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.Type: ApplicationFiled: May 8, 2001Publication date: February 14, 2002Inventor: Nobuo Ueki
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Publication number: 20020009295Abstract: A video signal reproduction apparatus for receiving an information signal including a video signal and a determination signal indicating a type of the video signal, and reproducing the video signal included in the information signal. The apparatus comprises a conversion section for converting the video signal to a progressive scan video signal, and an aspect ratio conversion section for converting an aspect ratio of the progressive scan video signal output from the conversion section and outputting the converted progressive scan video signal to a progressive scan video monitor. The aspect ratio conversion section converts the aspect ratio of the progressive scan video signal based on the determination signal indicating the type of the video signal and monitor information indicating a type of the progressive scan video monitor.Type: ApplicationFiled: June 28, 2001Publication date: January 24, 2002Inventor: Tetsuya Itani
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Patent number: 6337716Abstract: A receiver for simultaneously displaying signals having different display formats and/or different frame rates, and a method thereof are provided. The receiver includes a signal generator, a first display processor, and a second display processor. The signal generator generates a first vertical synchronous signal for a high definition (HD) image, a first field identification signal for coping with a case in which an HD image is an interlace image, a second vertical synchronous signal for a standard image, and a second field identification signal for a standard image. The first display processor processes a received HD decoded image to an HD display format according to the first vertical synchronous signal and the first field identification signal.Type: GrantFiled: December 8, 1999Date of Patent: January 8, 2002Assignee: Samsung Electronics Co., Ltd.Inventor: Myung-sik Yim
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Patent number: 6333762Abstract: A scan format converter for converting a video format by bi-sigmoid interpolation. In the scan format converter, a memory controller has a look-up table at which first and second displacement values for pixel points of a video format to be converted are stored, controls transmission of color signals input from an external device, and reads the first and second displacement values for the pixel points of the color signals from the look-up table. A mode detector detects horizontal and vertical sync signals input from the external device and outputs a video format detection signal representing a mode of the currently input video format to the memory controller. A memory temporarily stores the color signals.Type: GrantFiled: January 7, 1999Date of Patent: December 25, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Joong-Sun Yoo, Chang-Wan Hong, Jong-Chul Choi, Yeon-Mo Jeong, Jae-Jun Lee
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Patent number: 6281933Abstract: A two-dimensional (2D) filter is disclosed that accomplishes flicker filtering with virtually no loss of image resolution. The 2D filter operates without adaption and only on the non-detail portions of the original image. The filter works first in the horizontal (x-axis) direction by separating the high-pass (detail, high-resolution) image elements from the low-pass (blurred, low-resolution) elements. A vertical (y-axis) flicker filter is applied to the low-pass elements and the result is summed with the high-pass elements. Thus, the detail elements are not subjected to flicker filtering and, as a result, remain well-defined while flicker is eliminated from the overall image.Type: GrantFiled: December 11, 1997Date of Patent: August 28, 2001Assignee: Chrontel, Inc.Inventor: David W. Ritter
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Patent number: 6275266Abstract: A software architecture for a personal computer enables control of an attached television set as a graphic output device, where the software architecture includes a dynamically linked library storing executable library routines that can be called by a computer system routine across an application programming interface, and a hardware extraction layer having hardware-specific routines that are called by a selected library routine to perform a specific hardware operation. The hardware-specific routines control operation of a graphics core configured to control the television set, for example by detecting whether the television set is attached to thecomputer system. Additional operations supported by the dynamically linked library include automatically adjusting the size and resolution of Windows (or portions thereof) output to the television set.Type: GrantFiled: November 12, 1997Date of Patent: August 14, 2001Assignee: Philips Electronics North America CorporationInventors: Charles F. Morris, Gregory T. Lydon, Mark Keith Reha
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Patent number: 6271881Abstract: A color image pickup apparatus includes a photo-to-electric conversion section subjected to progressive scanning. A first delay circuit defers an output signal of the photo-to-electric conversion section. A first adder combines the output signal of the photo-to-electric conversion section and an output signal of the first delay circuit. A second delay circuit defers the output signal of the first delay circuit. A second adder combines the output signal of the photo-to-electric conversion section and an output signal of the second delay circuit. A third delay circuit defers an output signal of the first adder. A first subtracter implements subtraction between the output signal of the first adder and an output signal of the third delay circuit. A fourth delay circuit defers an output signal of the second adder. A second subtracter implements subtraction between the output signal of the second adder and an output signal of the fourth delay circuit.Type: GrantFiled: April 27, 1998Date of Patent: August 7, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yuichirou Takahashi, Atsuto Kanazawa, Masaki Kariya, Masayuki Serizawa, Kenji Tamura, Kikuo Kobayashi, Masaaki Nakayama, Hiromichi Tanaka
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Patent number: 6266093Abstract: A method for generating interlaced video signals representative of color images of a scene includes the following steps: deriving a progressively scanned luminance signal representative of the scene at a first frame rate; deriving interlaced scanned color component signals and a color-derived luminance component representative of the scene; high pass filtering and scan converting the luminance signal to obtain an interlaced detail luminance component; low pass filtering the interlaced color component signals and color-derived luminance component to obtain interlaced chrominance output signals and an interlaced low pass luminance component; and combining the detail luminance component and the low pass luminance component to obtain an interlaced luminance output signal.Type: GrantFiled: July 28, 1999Date of Patent: July 24, 2001Assignee: Florida Atlantic UniversityInventor: William E. Glenn
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Patent number: 6256450Abstract: A progressive scanned signal processing apparatus for inputting progressive scanned image signals and processing them as 420P signals comprises a signal processing means and a storing means in order to prevent the qualities of images of color difference signals from being lowered. A delay time required for carrying out a whole signal processing is expressed by 2×N×F (herein, N>0, N is an integer and F is time necessary for a period of one frame). Accordingly, the delay time necessary for the signal processing is expressed by the frames of even number, so that a main signal can be prevented from being replaced by a sub-signal.Type: GrantFiled: December 12, 1997Date of Patent: July 3, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tokuji Kuroda, Tatsushi Bannai
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Patent number: 6229571Abstract: The present invention relates to a scan converter with an interpolating function comprising: a plurality of frame buffers for dividing and storing video data of a first scan system and for reading the video data at a timing in accordance with a second scan system; and an interpolator for performing interpolation in the vertical direction for the video data read from the frame buffers.Type: GrantFiled: July 22, 1999Date of Patent: May 8, 2001Assignee: NEC CorporationInventor: Shinobu Sato
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Patent number: 6226040Abstract: Apparatus for generating at least a selected area in a picture is disclosed herein. The picture and the selected area are displayed on a video display means, and the user can optionally adjust the position and size of the selected area. The apparatus including the following devices. A first converting device that is used to generate a digital signal and a pointer defining signal according to a computer video signal. The picture is transferred from the computer video signal, and the selected area is defined in the pointer defining signal. A first adapting device that is utilized to adapt the format of the computer video signal to suit a digital display format corresponding to the pointer defining signal. A storage device determines said display timing of all the pixels of the picture. A pointer generating device generates a plurality of edge of the selected area according to the pointer defining signal.Type: GrantFiled: April 14, 1998Date of Patent: May 1, 2001Assignees: Avermedia Technologies, Inc. (Taiwan Company), Avermedia Technologies, Inc. (U.S.A. Company)Inventors: Chung-Song Kuo, Yung-Che Chang, Kun-Chou Chen, Hsien-Wen Cheng
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Patent number: 6212238Abstract: A device having alternative intercommunication formats, and an automated method of selecting the appropriate format to use, in dependence upon the ability of the device to which it is interconnected to utilize this format. Many devices utilize standard analog formats, such as NTSC, PAL, SECAM, and others, to communicate with other devices; many of these devices utilize digital formats, such as MPEG and others, for internal processing or storage. By appending a supplemental signal to the analog signal, the ability of the device to use a digital format can be communicated to the device to which it is interconnected. By communicating their capabilities, devices which have the ability to utilize the same digital format can automatically switch to this digital format for intercommunication, thereby avoiding the signal degradations typically associated with conversions to and from an analog form.Type: GrantFiled: December 19, 1997Date of Patent: April 3, 2001Assignee: Philips Electronics North America CorporationInventor: Paul Chambers
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Patent number: 6160915Abstract: The present invention enables a stable signal reproduction without overflow or underflow of a buffer in a decoder system even if a transmission bit rate is changed. In particular, when coding and transmitting a digital signal at a variable bit rate, a size of an encoder buffer for temporarily storing a coded signal in an encoder system is controlled according to a coding bit rate from a terminal. The encoder buffer has a code buffer to be used for rate control by the encoder system. The size of this code buffer is determined according to a reception buffer size of a decoder system supplied from a terminal, a maximum value of a coding bit rate supplied from a terminal, and a current bit rate.Type: GrantFiled: October 29, 1997Date of Patent: December 12, 2000Assignee: Sony CorporationInventors: Motoki Kato, Hideki Koyanagi
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Patent number: 6157412Abstract: A detector for a video signal includes a pixel comparator that compares a plurality of values of pixels of a first field of the video signal with corresponding pixels of a second field of the video signal. The second field is a second preceding field of the video signal in relation to the first field. The resultant values from the comparison is a set of pixel difference values. A counter determines a count value representative of the number of the set of pixel difference values that are either greater than a threshold value or less than the threshold value. A thresholder circuit determines a variable statistical value, such as an average, based upon a preceding series of the count values. The thresholder circuit compares the variable statistical value with the count value, or a percentage thereof, to determine whether the variable statistical value is greater than the count value or whether the statistical value is less than the count value.Type: GrantFiled: March 30, 1998Date of Patent: December 5, 2000Assignee: Sharp Laboratories of America, Inc.Inventors: Larry Alan Westerman, Prasanna L. Modem
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Patent number: 6147712Abstract: A format converter has a memory capable of storing a video signal of progressive or interlaced scan construction and having one of a plurality of video data sizes and one of a plurality of frame rates, a frame rate controller using the memory to control a frame rate of the video signal, and a conversion filter for converting a video data size of the video signal. With the above configuration, conversion of the signal is effected without losing or detracting the features of the source material of the video signal. The conversion of the video data size is preferably effected on the output having the frame rate adjusted. With the above configuration, the format of a video signal can be converted without degrading the quality of the input video signal, and at the same time the required memory capacity can be reduced.Type: GrantFiled: May 19, 1997Date of Patent: November 14, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hidemitsu Shimamoto, Takashi Shinohara, Naoki Hayashi
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Patent number: 6141055Abstract: It is disclosed herein that a system for reducing video data memory in VGA-to-TV converters that convert computer video signals to TV compliant signals for display on regular TV screens. By closely tracking two pointers, one being a write pointer responsible for writing incoming video data into the video data memory and the other being a read pointer responsible for reading out the stored video data in the video data memory, the memory is efficiently used for buffering the video data. To ensure that the read pointer always retrieves the valid video data at its own speed, an address monitoring process is provided to monitor the address difference between the write pointer and the read pointer. When the monitoring process detects that the read pointer may soon surpass the write pointer, a control process is placed on the write pointer to prevent the read pointer from passing over the write pointer.Type: GrantFiled: July 10, 1997Date of Patent: October 31, 2000Assignee: Aitech Int'l CorporationInventor: Xiao Chuan Li
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Patent number: 6124893Abstract: A versatile video transformation device and adaptive image processing methodology thereof to digitally scan convert, that is, reformat TV raster scan video and particularly high definition (HD) and/or digital DTV (particularly those for example in 1920.times.1080i or 1280.times.720p format) video data and associated synchronizing signals, for the purpose of making present standard television sets compatible at low cost with the latest advancements in free HD whilst allowing a multitude of other DTV programs and ancillary data to fill to a greater extent the remaining channel allocations by FCC to TV broadcasters.Type: GrantFiled: April 29, 1998Date of Patent: September 26, 2000Inventor: John J. Stapleton
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Patent number: 6108041Abstract: Video sources from a progressively scanned camera are processed so as to simulate a video source derived from motion picture film. The simulated film source video creates a distinctive "pseudo-film pattern," in which at least some of every SDTV video field has no motion or low motion with respect to corresponding picture areas of the SDTV video field paired with it (occasional rare camera-originated scenes result in a field in which the entire picture has high motion, breaking the pseudo-film pattern). Corresponding picture areas within the pairs of fields having no motion or low motion are merged, in the manner in which interlaced fields derived from the same motion picture frame are merged. Corresponding picture areas within the pairs of fields having high motion are subject to interlace-to-progressive scan conversion processing which is not purely a merger of fields.Type: GrantFiled: October 10, 1997Date of Patent: August 22, 2000Assignee: Faroudja Laboratories, Inc.Inventors: Yves C. Faroudja, Peter D. Swartz, Jack J. Campbell
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Patent number: 6104755Abstract: A method of measuring the motion in video image data for a pixel which uses both field-difference and frame-difference motion values to generate a motion value having increased accuracy. Image data (806) from the same pixel in a prior row of the same field (906) is compared to image data (808) from the same pixel in the prior row of the prior frame (908), and the absolute value of the difference is compared to the absolute value of the difference in image data (802) from the same pixel in a following row of the same field (902) and image data (804) from the same pixel in the following line of the prior frame (904). The minimum of these two values is the minimum frame-difference motion value which is input into a logical mixer. Also input into the logical mixer is the minimum field-difference motion value which may be determined by comparing data (802, 806) from the same pixel of an adjacent line of the same field (902, 906) with image data (810) from the same pixel of the same line of the prior field.Type: GrantFiled: September 12, 1997Date of Patent: August 15, 2000Assignee: Texas Instruments IncorporatedInventor: Kazuhiro Ohara
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Patent number: 6100934Abstract: An apparatus is disclosed to convert a non-interlaced computer graphics signal which consists of contiguous scan lines into an interlaced video signal which alternately consists of even fields and odd fields. The converting apparatus includes a receiving means, a low-pass filter and a line buffer. The receiving means sequentially receives a scan line. The line buffer stores the brightness signals of the first and the second scan lines before the received scan line. And the low-pass filter receives the sequential contiguous scan lines from the line buffer and the displaying scan line, weights the brightness signals of these scan lines and outputs the scan lines with the weighted brightness signal and a halved refresh rate to serve as the even field and the odd field of the interlace video signal.Type: GrantFiled: January 5, 1998Date of Patent: August 8, 2000Assignee: Winbond Electronics CorporationInventors: Hsiung-Hao Liu, Rong-Chuan Tsai
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Patent number: 6094226Abstract: A system and method for conversion of graphics from computer graphics formats to television formats is disclosed. More particularly, an improved scaling and flicker reduction system and method is disclosed for scaling personal computer (PC) graphics formats into different resolution television (TV) formats and for reducing flicker due to the conversion process of interlacing non-interlaced PC graphics to match interlaced TV formats. The scaling implementation reduces line buffer requirements by using a conditional scaling technique for converting graphics from a PC resolution format to a TV resolution format. The flicker reduction implementation provides a two-dimensional adaptive filter that selects between multiple filters so that different parts of an image may have different flicker reduction and different levels of trade off between flicker reduction and resolution.Type: GrantFiled: July 12, 1999Date of Patent: July 25, 2000Assignee: Cirrus Logic, Inc.Inventors: Ligang Ke, Juergen M. Lutz
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Patent number: 6084568Abstract: A device performs both 2-tap and 3-tap flicker filtering of non-interlaced lines of computer graphics data to form interlaced lines. The device includes a data packer, a data unpacker, and a filter circuit. The filter circuit combines lines that it receives to form filtered lines. The data packer writes the filtered lines to line buffers while the data unpacker reads the lines stored in the line buffers. The read lines are either sent to the filter circuit for further filtering or are outputted to be displayed as interlaced lines. Both 2-tap and 3-tap flicker filtering can be accomplished by varying the order and/or number of read, write, and filter operations.Type: GrantFiled: November 13, 1997Date of Patent: July 4, 2000Assignee: S3 IncorporatedInventors: Reena Premi, William S. Herz, Ignatius B. Tjandrasuwita
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Patent number: 6081298Abstract: This MPEG Decoder relates to the decoding of an image that can be of a bi-directional type requiring data from two previously decoded images, each image being displayed in two successive fields corresponding to lines with different parities. Each bi-directional image is decoded twice during its display time, a first time as a first field of the image is being directly displayed, and a second time as the second field is being directly displayed.Type: GrantFiled: March 7, 1996Date of Patent: June 27, 2000Assignee: SGS-Thomson Microelectronics S.A.Inventor: Alain Artieri
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Flicker filter and interlacer implemented in a television system displaying network application data
Patent number: 6072530Abstract: A television system (TV) with an interlaced display screen for displaying network application data. A flicker filter is preferably implemented as an infinite impulse response (IIR) filter to eliminate sharp transitions in the network application data images. A random access memory is used to store the lines of the filtered images and any adjacent lines used for the filtering operation. Alternate lines of the filtered images are retrieved from the random access memory to provide an interlaced image of the filtered network application data images. The interlaced images are displayed on an interlaced display unit of a television system.Type: GrantFiled: December 31, 1997Date of Patent: June 6, 2000Assignee: TeleCruz Technology, Inc.Inventor: Vlad Bril -
Patent number: 6069663Abstract: A computer-generated image signal is analyzed to derive a set of alignment parameters for a television. These alignment parameters arc then used to configure the television accordingly. The alignment parameters may include aspects of the computer-generated image signal such as a vertical period, a horizontal frequency, a horizontal front porch, a horizontal active image time and/or a maximum RGB video level. The television may be configured to reduce its raster length to accommodate the compute generated image signal. Further, the values of the horizontal measurements for the active video time, front porch and frequency of the computer-generated image signals may be used to determine values for the television's horizontal picture size and position. Such values may be determined by computation or by table look up. In addition, other television alignment parameters such as upper and lower pin cushion, vertical bow, pin amplitude and/or horizontal angle may be determined.Type: GrantFiled: October 6, 1997Date of Patent: May 30, 2000Assignees: Sony Corporation, Sony Electronics, Inc.Inventors: David H. Bessel, William McKnight
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Patent number: 6069662Abstract: An apparatus for displaying a plurality of compressed images is disclosed, in which a high quality freeze display is made possible with a high vertical resolution and a multiplicity of compressed images can be displayed at the same time on the display screen without increasing the circuit scale extremely. Different video signals are processed for image compression in a plurality of processing circuits, and a synthesized image is supplied to a display unit for displaying four compressed images on the display screen at the same time. In the case of an image sequence display, the image size is compressed into one half in horizontal and vertical directions respectively by the processing circuits, and the odd and even fields are separately written in field memories. Also, in the case of freeze display, all the lines are written alternately in the field memories without compressing them vertically by a filter circuit.Type: GrantFiled: October 29, 1996Date of Patent: May 30, 2000Assignee: Hitachi, Ltd.Inventors: Tadasu Horiuchi, Koichi Ono, Kazuya Yamashita
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Patent number: 6069664Abstract: The present invention is embodied in an apparatus and method for converting a progressive video signal to an interlaced video signal from which the progressive video signal may be recovered. The invention is further embodied in an apparatus and method for converting such an interlaced video signal to a progressive video signal. A progressive-to-interlaced video converter includes a progressive video preprocessor and a converter. The progressive video preprocessor replaces at least one scan line in a video frame by its preceding or succeeding scan line. Alternatively, the preprocessor may assign a predetermined value to one or multiple scan lines at appropriate position(s) in a frame. In either scenario, each frame will carry at least one redundant scan line. The frame modification information will be encoded to an ancillary data section of a digital video stream.Type: GrantFiled: June 4, 1997Date of Patent: May 30, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Daniel Qiang Zhu, Kaarlo Juhani Hamalainen, Thomas James Leacock, Kevin John Stec
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Patent number: 6067120Abstract: A video signal conversion device of the present includes a flicker reduction section including a plurality of line buffers for storing data in accordance with an address thereof. The flicker reduction section receives non-interlaced signals, converts the non-interlaced signals to interlaced signals and performs a flicker reduction process.Type: GrantFiled: August 26, 1998Date of Patent: May 23, 2000Assignee: Sharp Kabushiki KaishaInventors: Koji Horikawa, Hideaki Kawamura, Masayuki Ezawa
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Patent number: 6064437Abstract: Video information which is organized in a first format is converted to a second format by first scaling the video information to produce scaled video information and then color correcting the scaled video information to produce color corrected video information at a network server. Scaling the video information may be accomplished by first applying a vertical scaling process to the video information to produce vertically scaled video information. Second, an anti-flicker filter may be applied to the vertically scaled video information to produce the scaled video information. The vertical scaling process includes a pixel-by-pixel conversion process wherein, for each group of six scan lines in a frame of the video information, color information for individual pixels which make up the group of six scan lines is scaled to provide color information for pixels in a corresponding group of five scan lines of a frame of the vertically scaled video information.Type: GrantFiled: September 11, 1998Date of Patent: May 16, 2000Assignee: Sharewave, Inc.Inventors: Michael H. Phan, Joseph D. Harwood
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Patent number: 6061094Abstract: A method and apparatus is provided for the conversion of non-interlaced image data to interlaced image data while reducing flicker effects and simultaneously scaling the image data. A programmable discrete time oscillator (DTO) dynamically determines coefficients that are used in reducing flicker and vertical and horizontal scaling. The two functions are integrated which allow the flicker filter coefficient generated by the DTO to dynamically be modified and take into account desired vertical scaling. A similar DTO is provided to separately perform horizontal scaling using the dynamic coefficients.Type: GrantFiled: November 12, 1997Date of Patent: May 9, 2000Assignee: U.S. Philips CorporationInventor: Michael Maietta
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Patent number: 6058143Abstract: A transcoding method is performed by receiving a first bitstream of compressed image data having identifiable coding parameters. These parameters may relate to the GOP structure of pictures represented in the first bitstream, the size of the pictures represented in the first bitstream, whether the pictures represented in the first bitstream are field or frame pictures, and/or whether the pictures represented in the first bitstream define a progressive or interlaced sequence. First motion information is obtained from the first bitstream, and is used to extrapolate second motion information for a second bitstream of compressed image data. The second bitstream, which has one or more parameters different from the parameters of the first bitstream, is provided as a transcoded output.Type: GrantFiled: February 20, 1998Date of Patent: May 2, 2000Assignee: Thomson Licensing S.A.Inventor: Stuart Jay Golin
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Patent number: 6040872Abstract: A communication control device and method which can perform communication tasks such as computer communication, facsimile transmission and reception utilizing a television receiver. A user can select one of a television mode, a computer communication mode, and a facsimile mode by means of a television/communication switching section, thereby enjoying multifunction with the television receiver. The device includes an image interface section for performing interlaced scanning suitable for television screen display. The user may enjoy computer communication and facsimile transmission and reception as well as television function by means of a remote controller and a keyboard. The facsimile data may be recorded or reproduced by an external video recording/reproducing apparatus.Type: GrantFiled: October 27, 1995Date of Patent: March 21, 2000Assignee: LG Electronics, Inc.Inventor: Hak Lyang Kim
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Patent number: 6028589Abstract: A method of and apparatus for convolution that provides both scaling and elimination of flicker when displaying computer generated or computer processed information on an interlaced, television monitor. One preferred embodiment includes a bilinear interpolation for scaling combined with a modified three line convolution for flicker reduction. In one preferred embodiment, 8 lines of a source computer image are scaled to 7 lines of a television image for display. The weighted contribution of each input line varies according to which combination of lines contribute to each output line, and the mathematically optimal weighting factors are modified for easier implementation in hardware.Type: GrantFiled: January 10, 1997Date of Patent: February 22, 2000Assignee: Apple Computer, Inc.Inventors: Vivek Mehra, Edwin Rose
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Patent number: 6005630Abstract: A television system (TV) with an interlaced display screen for displaying network application data. Pixel data elements representing network application data display are received in a non-interlaced mode. The received data is filtered to reduce sharp transitions in the display. The filtered data is provided in an interlaced format (i.e., only alternate lines of a frame) for display on the television display screen. The interlaced image display is combined with the television signal display by selecting one of them on point by point basis. Flicker is reduced substantially in the final display of network application data due to the filtering.Type: GrantFiled: February 4, 1999Date of Patent: December 21, 1999Assignee: TeleCruz Technology, Inc.Inventor: Vlad Bril
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Patent number: 6002442Abstract: The present invention discloses a system for adaptively reducing flickers in converting non-interlaced video signals to interlaced video signals. To preserve the original image quality in the non-interlaced video signals, the disclosed system examines the pixel values in at least two adjacent lines to decide if a reduction process should be turned on. If there is a need, the reduction process further examines the difference in the pixels from the adjacent lines to determine how to adjust a corresponding output to eliminate flickers in the resultant converted video signals. The adjusting means is based on an adjusting factor or the calculated difference between pixels which is further used in a function to eventually produce a converted interlaced signal with minimum visual errors.Type: GrantFiled: April 1, 1997Date of Patent: December 14, 1999Assignee: Aitech International Corp.Inventors: Jan-Kwei Jack Li, Huang-Jen Chen
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Patent number: 5990964Abstract: A method for processing a time code including the steps of generating information, indicating whether or not a location is proper for editing when converting picture information of a predetermined system into picture information of another system, and writing the information to the time code data accompanied with the picture information of the second system.Type: GrantFiled: September 23, 1996Date of Patent: November 23, 1999Assignees: Sony Corp., Sony ElectronicsInventors: Tetsuo Ogawa, Hiroshi Kiriyama, Tomokiyo Kato, Hiroaki Kikuchi, Luke Freeman
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Patent number: 5990965Abstract: An apparatus simultaneously flicker filters and vertically contracts a plurality of original lines to form compensated lines. The device uses a coefficient calculator and a line processor, both controlled by a controller. The coefficient calculator provides compensation coefficients to the line processor. The line processor forms weighted sums of the original lines, with the weightings determined by the compensation coefficients. The compensation coefficients are chosen to simultaneously implement flicker filtering and vertical contraction. Thus, the weighted sums are the compensated lines.Type: GrantFiled: September 29, 1997Date of Patent: November 23, 1999Assignee: S3 IncorporatedInventors: William S. Herz, Yichou Lin
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Patent number: 5987215Abstract: A video signal recording apparatus including a switching device for receiving a digital progressive scan TV signal having a frame cycle which is 1/2 of the frame cycle of an interlaced scan TV signal and switching the progressive scan TV signal frame by frame alternately; a coding device for performing high-rate coding of data corresponding to one frame of the progressive scan TV signal to the same code amount as obtained by high-rate coding of data corresponding to one frame including two successive fields of an interlaced scan standard-definition TV signal; and a recording device for recording the data processed with the high-rate coding in the same number of tracks as the data corresponding to one frame of the interlaced scan standard-definition TV signal.Type: GrantFiled: October 8, 1997Date of Patent: November 16, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shiro Kato, Masakazu Nishino, Tatsuro Juri, Yuji Fujiwara, Seiichi Takeuchi
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Patent number: 5982444Abstract: A picture signal encoding method in which a picture string produced by converting non-interlaced pictures into sets of field pictures each beginning from the first field of each interlaced picture and another picture string produced by converting non-interlaced pictures into sets of field pictures each beginning from the second field of each interlaced picture are combined together to an input picture signal for encoding, is disclosed. The method includes a detection step of detecting a lone field not constituting the non-interlaced picture in the input picture signal, and an encoding step of re-constructing the picture string of the input picture signal and encoding the resulting non-interlaced picture string.Type: GrantFiled: June 10, 1998Date of Patent: November 9, 1999Assignee: Sony CorporationInventors: Motoki Kato, Katsumi Tahara