Abstract: A method of transmitting timing critical data via an asynchronous channel without changing any datum to be transmitted. The timing critical data can be an MPEG transport stream. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR, or a digital interface. The method involves tagging each transmission unit of the data stream, before inputting to the channel, with timing information, and using the timing information at the output end of the channel to recreate the proper data timing, Various schemes are described for packing the timing information tags with each or a plurality of transmission units.

Abstract: The invention provides an image processing circuit having a capability of performing a reduction (resizing) process and an enlargement process on horizontal-scanning-line data inputted in synchronization with an input horizontal synchronization signal, and subsequently adjusting the horizontal synchronization signals so that the input horizontal-scanning-line data is made transferable to external devices in real time, and an image processing method therefor. A reducing unit thins out n-lines of the input horizontal synchronization signals out of m-lines of the input horizontal synchronization signals HD. When an enlarging unit enlarges the image data by an enlargement ratio k (k: natural number) in the vertical direction, the enlarging unit inserts (k?1) lines of the second horizontal synchronization signals for data transmission EHSYNC2 in the transmitting horizontal-synchronization-signal interval time TC1 between adjacent first horizontal synchronization signals for data.

Abstract: A VSB communication system or transmitter for processing supplemental data packets with MPEG-II data packets includes a VSB supplemental data processor and a VSB transmission system. The VSB supplemental data processor includes a Reed-Solomon coder for coding the supplemental data to be transmitted, a null sequence inserter for inserting a null sequence to an interleaved supplemental data for generating a predefined sequence, a header inserter for inserting an MPEG header to the supplemental data having the null sequence inserted therein, a multiplexer for multiplexing an MPEG data coded with the supplemental data having the MPEG header added thereto in a preset multiplexing ratio and units. The output of the multiplexer is provided to an 8T-VSB transmission system for modulating a data field from the multiplexer and transmitting the modulated data field to a VSB reception system.

Abstract: The present invention provides a method for generating a scenario for a music-and-image-synchronized motion picture comprising the steps of: extracting characteristics of music; extracting structure of the music on the basis of the extracted characteristics of the music and dividing the music into multiple components on the basis of the result of the extraction; analyzing characteristics of images; associating the music and the images with each other according to the characteristics corresponding to the components of the music and the characteristics of the images; and generating a motion picture scenario that enables the associated music and images to be synchronously reproduced. According to the invention, since a component of music and images are associated with each other according to the characteristics of the images, it is possible to synchronously reproduce images that match the contents of music being reproduced, in comparison with the conventional synchronous reproduction.

Abstract: A method for deriving a synchronisation signal (35) from a video signal comprises tracking the blanking level (107) of the video signal with first and second slice level signals (26, 27) and tracking the sync tip level (110) of the horizontal sync signal (109) of the video signal with third and fourth slice level signals (28,29) for determining the blanking level (107) and the sync tip level (110). A value for an intermediate slice level signal (30) is computed from the first, second, third and fourth slice level signals (26, 27, 28, 29) so that the value of the intermediate slice level signal (30) lies approximately halfway between the blanking level (107) and the sync tip level (110).

Abstract: A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.

Abstract: When performing A/D conversion on image signals, when reducing noise that is caused by jitter by adjusting the phase of the sampling clocks, even if the input waveform has considerable waveform distortion such as a triangular wave, it is possible to reliably reduce this noise. Input analog image signals are converted into digital image data using sampling clocks from a PLL circuit by A/D conversion means. Next, image data that has delayed by a 1 clock delay circuit is subtracted from the digital data by a subtracter. The maximum value of one screen of the subtracted output is then determined, and 5 is subtracted therefrom to provide a threshold value. A comparator compares the subtracted output and the threshold value, and outputs a signal when the subtracted output is greater than the threshold value. A counter then supplies the count value of these signals to a CPU, and the CPU controls the phases of the sampling clocks using a switch.

Abstract: An external synchronous signal circuit comprises: means for measuring a phase difference between the external frame synchronous signal (FRM_SYNC) and the frame synchronous signal (FRM) of the digital video signal; means for generating a signal (EXT_H) having the same period as that of the horizontal synchronous signal (HBK) of the digital video signal, the signal (EXT_H) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video; and means for generating a signal (EXT_F) having the same period as that of the frame synchronous signal (FRM) of the digital video signal, the signal (EXT_F) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video. The generated signals (EXT_F) and (EXT_H) are outputted as an external frame timing signal and an external horizontal timing signal of an external synchronous signal.

Abstract: A sync generator (genlock) (10) for frequency and phase locking an incoming video signal to a system clock (12) includes a digitizer (16, 22) for digitizing the incoming video signal to yield a digitized color sub-carrier burst component. A numerically controlled oscillator (15) clocked by the system clock generates a phase lock reference signal for locking to the incoming video signal. Phase detection means logic unit (42, 74) sense a static phase offset magnitude from an ideal 90° phase offset between the digitized color sub-carrier burst component and the numerically controlled oscillator output signal. In accordance with the sensed static offset, a static phase error nulling circuit (70) generates a compensating offset in accordance for input to the system clock (27) to drive the static offset to zero, thus achieving frequency and phase locking.

Abstract: A synchronization detecting apparatus includes a counter, an error detector, and a line length generator. The counter counts to a predetermined counter value in response to a clock signal. The error detector generates an error, which is the difference between a current counter value received from the counter and a previous line length, in response to a synchronization flag signal. The line length generator generates a current line length based on a compensated error and the predetermined counter value. The synchronization flag signal has an active level at a transitioning edge of a synchronization pulse signal contained in an input signal.

Abstract: A method and an arrangement are disclosed for synchronizing on-screen display functions during analog signal reception in a terminal arrangement that is capable of receiving both digital and analog video signals. There are provided means (312, 313) for generating on-screen display objects. Coupled to said means for generating on-screen display objects, there are synchronization pulse generation means (314) for controlling the generation of on-screen display objects. Comparison means (322) are used for comparing synchronization pulses generated by said synchronization pulse generation means (314) with a synchronization signal obtained (320) from an analog video signal. The result of said comparing as a controlling signal is conveyed (323, 324) to a process (314, 325) of generating said synchronization pulses.

Abstract: The present invention relates to a system and method for generating a blanking period indicator signal from sync information in video timing. The invention comprises an auto polarity detect processor adapted to automatically detect the polarity of at least one sync signal and a generation processor adapted to generate a DE signal.

Abstract: A video scaling apparatus includes a receiver for receiving incoming video signals having transmitted therein a plurality of incoming frames, each incoming frame having a first plurality of synchronization signals for indicating lines in the incoming frame; a scaler with a line extender for generating outgoing video signals having transmitted therein a plurality of outgoing frames, each outgoing frame having a second plurality of synchronization signals for indicating lines in the outgoing frame, and for generating an outgoing frame for each incoming frame. The line extender ensures durations of all lines in the outgoing video signals are of substantially equal length. By ensuring that all lines in the outgoing frame are of substantially the same length, the reliability of a display device receiving the outgoing video signals is increased. Additionally, the frequency requirements of an outgoing clock for the video signals can be less stringent.

Abstract: A synchronization signal generating apparatus and method in which an input circuit is inductively coupled to an alternating current signal line. The input circuit generates a rectified signal. A switch has a switch input and a switch output in which the switch input is electrically connected to the input circuit and is enabled when the voltage of the rectified signal is greater than a predetermined voltage and is disabled when the rectified signal voltage is less than the predetermined voltage. A pulse generating circuit has a pulse generating circuit input and a pulse generating circuit output. The pulse generating circuit input is electrically connected to the switch output. The pulse generating circuit generates a pulse each time the switch is enabled. The synchronization signal generating apparatus is used in a synchronized television display system to signal a video switch to switch the video signal generated by a camera to a monitor based on the occurrence of the synchronization signal.

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700,702,704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments.

Abstract: A method for driving a display is provided which is capable of reducing current consumption. In the method above, a scanning frequency in a self-emissive display is changed based on a display content to be displayed in the self-emissive display.

Abstract: The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Abstract: A system, method and apparatus are provided for generating 98 a sandcastle signal in a television signal receiver 90, and utilizing the sandcastle signal during television signal processing. In one form, the sandcastle signal is generated by subtracting a separated synchronization signal of a television signal from a deflection retrace signal of the television signal receiver. In another form, the sandcastle signal is generated in a television and includes subtracting a separated synchronization pulse from a horizontal flyback pulse, a vertical retrace pulse, or a composite pulse formed by summation of a horizontal flyback pulse and a vertical retrace pulse. The sandcastle signal may be utilized by the television signal receiver 90 during a function of the television signal receiver 90, such as during a channel change.

Abstract: A video signal reproducing apparatus and method for adjusting a change in a horizontal synchronous signal. The video signal reproducing apparatus transforms a format of an input video signal, generates horizontal and vertical synchronous signals, and displays the video. The video signal reproducing apparatus includes a measurer, a comparator, and an adjustor. The measurer measures a period of the horizontal synchronous signal, the comparator compares the measured period of the horizontal synchronous signal with a predetermined reference range, and the adjustor adjusts a period of a clock signal for producing the horizontal synchronous signal, if the measured period of the horizontal synchronous signal fails to fall within the predetermined reference range.

Abstract: A synchronization pulse detector includes an absolute value independent shape detector for processing samples of an input signal having a synchronization pulse and a plurality of non-synchronization pulses to determine whether such samples have a predetermined sequence. The predetermined sequence includes a first and second absolute value independent time-varying portions and a first and second absolute value independent non-time varying portions. One of the first and second absolute value independent time-varying portions having a positive slope and the other one of the first and second absolute value independent time-varying portions having a negative slope.

Abstract: A transmitter is disclosed for transmitting a first and second digital information signal. Said first digital information signal comprises first frames having at least a first synchronization signal and a data portion stored in them. The transmitter processes the second digital information signal into subsequent second frames comprising blocks of information of the second digital information signal. Composite frames have been obtained by inserting a second synchronization signal and at least the data portion of the first frames into the second frames by using buried data techniques. Prior to inserting at least the data portion of the first frame into a second frame the first synchronization signal is stripped from the first frame. The sequence of composite frames is transmitted via the transmission medium.

Abstract: A clock generating apparatus is provided for producing an output clock signal responsive to a source clock signal with a source frequency and a reference clock signal with a reference frequency. The clock generating apparatus includes a counting sequence generator, a measuring value generator and a ratio counter. The counting sequence generator is used for outputting a series of counting values in response to a triggering signal with a specified period determined by the source frequency of the source clock signal and a predetermined counting value. The measuring value generator generates a measuring value by operating the series of counting values according to a predetermined formula. The ratio counter produces the output clock signal with a frequency determined by the source frequency of the source clock signal and the measuring value.

Abstract: In the case of picture insertions, such as picture-in-picture, for example, fluctuations in the line duration are manifested in position displacements relative to the desired position of the inserted pictures. In order to prevent position displacements in the horizontal direction, it is provided that the insertion position is corrected in a manner dependent on a determined line duration. The method according to the invention is suitable in particular for picture-in-picture insertions in television receivers.

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700, 702, 704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal VREF, and is connected by a resistor divider (708,710) to the negative peak detector to form the signal VTIP+VSLICE provided to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIP is compared in comparator (606) with the composite video signal to provide an overall circuit output.

Abstract: A video processing system and method are provided for generating clock and timing signals from an incoming video signal. The system includes a timing reference circuit for generating a reference clock signal, a video format detector coupled to the reference clock signal and to synchronization data derived from the incoming video signal for generating a format signal indicating the format of the incoming video signal, and a clock and timing generator circuit coupled to the format signal and the reference clock signal for generating clock and timing signals that emulate the incoming video signal, and may be locked to the incoming video signal.

Abstract: A method and circuit for generating a train of synthesized sync pulses in accordance with the Bresenham algorithm in response to an input clock having frequency Fi, such that the leading edges of the pulses occur at least nearly periodically, with time-averaged frequency at least nearly equal to (A/T)Fi, where A and T are integers, and such that the accumulated error, between the actual time interval between the first and last leading edges of Z consecutive ones of the pulses and the time ZT/(AFi), never exceeds 1/Fi. When Fi is equal to (T/A)Fo, where Fo is a predetermined output line frequency, an embodiment of the sync pulse generator includes an accumulator which stores a Count value, a comparator, and logic circuitry for generating the sync pulse train in response to a binary signal asserted by the comparator (and typically also control data that determines a configuration of the logic circuitry).

Abstract: An apparatus and method of interfacing video information which can provide an accurately displayed video picture irrespective of the type of a video input signal by interfacing the video display information between a main body and a monitor, and thus maintaining the optimum picture state. The apparatus includes a main body for outputting a video signal and information on a display type of the video signal, and a monitor for detecting the display type of the corresponding video signal in accordance with the display type information outputted from the main body and displaying on a display screen the video signal outputted from the main body to match the detected display type.

Abstract: A method for clock recovery comprises a series of steps to be performed in a decoder to adaptively estimate the ratio P/S of the frequency of an encoder system time clock and the frequency of a decoder. The steps include performing a series of overlapping trials N which calculate time differentials dP(n), dS(n), respectively) between selected pairs of temporally separated clock references CRs and arrival times STCs. Each trial concludes by calculating an estimated ratio X according to the formula: X(N)=(&Sgr;dP(n))/(&Sgr;dS(n)) A preferred embodiment of the present invention also includes the step of adjusting the decoder clock in accordance with a damped version of the estimate, thereby “recovering” the encoder STC in the decoder.

Abstract: Disclosed is an MPEG data frame and a transmitting and receiving system using the MPEG data frame for enhancing receiving performance of receiver which moves or is stationary. The digital TV broadcasting data frame according to the preferred embodiment of the present invention comprises a data frame which includes at least one data field which has 313 data segments. The first data segment of the data field is a data field sync signal which includes a training data sequence used for synchronization at the receiver, and the other 312 data segments each include a 188-byte transport packet and 20-byte error correction data. Therefore, when null packets are input to the 8 VSB transmitter, 2-level training sync signals are used as training data for an equalizer at the receiver so as to increase receiving performance of a receiver that moves or is stationary.

Abstract: The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Abstract: A digital TV receiver and a method for receiving a digital TV signal are disclosed, in which timing recovery and segment synchronizing signal recovery are independently implemented and VSB demodulation is digitally implemented.

Abstract: When a composite synchronization signal is used as a synchronization signal provided from an external source, since the period of the composite synchronization signal is irregular, it is impossible to perform phase adjustment on the composite synchronization signal before it is input to a timing controller IC.

Abstract: A method for obtaining line synchronization information items from a video signal is proposed. The inventive method is based on convolving the relevant part of an analogue video line signal with a pattern function. The result of the convolution operation is further processed to determine the time instants of the occurrence of the horizontal sync signals. The time instants are subsequently filtered to generate horizontal pulses. A video line memory allows to utilize subsequent horizontal sync signals for calculating the horizontal sync pulse of a current video line. The invention also relates to an apparatus for carrying out the method.

Abstract: A method of synchronizing a watermark decoder with a watermark encoder uses a spatio-temporal (3D) synchronization pattern added to a data pattern to produce a watermark pattern for embedment into a signal. The spatio-temporal synchronization pattern is formed by multiplying a spatial (2D) synchronization pattern with a pseudo-noise sequence for a block of signal frames having a duration of N frames. Quadrature carrier modulation may be used to increase detectability of the watermark pattern at the watermark decoder. The watermarked signal is correlated with the spatial synchronization pattern to recover a temporal synchronization signal that is used to determine a temporal offset between the watermark encoder and watermark decoder. The temporal offset is then used to synchronize the watermark decoder with the watermark encoder.

Abstract: Displaying the images encoded in a display signal which also contains synchronization signals and display enable (DE) signal. The DE signal indicates the time points at which the display data portion of the display signal contains active pixel data elements representing image frames. A display unit generates HDISP and VDISP signals (indicative of the active time in which active pixels and lines are respectively received) based on the DE signal. As the DE signal generally tracks (in the time domain) the active pixel data elements, the active pixel data elements forming image frames are accurately identified, and a superior image quality generally results.

Abstract: A first counter counts a first clock signal repeatedly in accordance with an external synchronous signal. A second counter counts a second clock signal repeatedly in every predetermined cycle, and generates an internal synchronous signal having the predetermined cycle. A controller adjusts the cycle of counting performed by the second counter by controlling the second counter. By doing so, the controller controls the internal synchronous signal to synchronize with the external synchronous signal in each horizontal period.

Abstract: A system, method and apparatus are provided for generating (98) a sandcastle signal in a television signal receiver (90), and utilizing the sandcastle signal during television signal processing. In one form, the sandcastle signal is generated by subtracting a separated synchronization signal of a television signal from a deflection retrace signal of the television signal receiver. IN another form, the sandcastle signal is generated in a television and includes subtracting a separated synchronization pulse from a horizontal flyback pulse, a vertical retrace pulse, or composite pulse formed by summation of a horizontal flyback pulse and a vertical retrace pulse. The sandcastle signal may be utilized by the television signal receiver (90) during a function of the television signal receiver (90), such as during a channel change.

Abstract: In a combined audio and video encoding system, the encoding system receiving a stream of video samples and a stream of audio samples, the encoding system producing an encoded video stream from the video samples and an encoded audio stream from the audio samples, a method for synchronizing between the encoded video stream and the encoded audio stream, the method including the steps of monitoring the encoded video stream and the encoded audio stream, detecting the amount of video data accumulated from the encoded video stream in a given time period, detecting the amount of audio data accumulated from the encoded audio stream in a given time period, increasing the number of audio samples in the audio stream, when the accumulated amount of video data is greater than the accumulated amount of audio data and decreasing the number of audio samples in the audio stream, when the accumulated amount of audio data is greater than the accumulated amount of video data.

Abstract: A sync signal generator circuit including a first counter which is reset each time it detects a reference edge of the input sync signal, a first register for holding a first value immediately before the first counter is reset, a reset signal generator for generating reset pulses, a second counter which is reset each time it receives a reset pulse, a second register for holding a second value immediately before the second counter is reset, and a sync pulse generator for generating an output sync signal on the basis of the reset pulses. The reset pulse is generated each time the counted value of the second counter matches a predetermined value or each time the first counter detects the reference edge while an absolute value of a difference between the counted value of the second counter and the second value held in the second register is not greater than a permissible value of period fluctuations.

Abstract: A method of transmitting digital data, which comprises the steps of obtaining first and second 8-bit word sequence data respectively based on luminance signal information data and chrominance signal information data which constitute a digital video signal, causing each of the first and second 8-bit word sequence data to be subjected to 8 bits to 10 bits conversion to produce first and second 10-bit word sequence data, obtaining third and fourth 8-bit word sequence data based on the first and second 10-bit word sequence data, respectively, inserting an additional word data group including 8-bit word synchronous data allotted a predetermined specific code into each of the third and fourth 8-bit word sequence data at predetermined word intervals to produce first and second composite 8-bit word sequence data, converting the first and second composite 8-bit word sequence data into first and second serial data, respectively, and transmitting the first and second serial data through first and second transmission lin

Abstract: An apparatus for generating a sync of a digital television in which an analog signal inputted to a digital television constantly provides stabilized synchronization regardless of a standard or a nonstandard so as to be processed.

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700, 702, 704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal VREF, and is connected by a resistor divider (708,710) to the negative peak detector to form the signal VTIP+VSLICE provided to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIP is compared in comparator (606) with the composite video signal to provide an overall circuit output.

Abstract: A pixel clock generating circuit is provided in which a digital circuit generates a first signal corresponding to the relative frequency of the pixel clock as compared with a predetermined desired pixel clock frequency. An analog circuit is electrically coupled to the digital circuit in which the analog circuit has a reverse biased variable capacitance device, an integrator and a comparator circuit. The reverse biased variable capacitance device has an anode and a cathode. The integrator has an input coupled to the digital circuit and an output coupled to the cathode of the reverse biased variable capacitor. The integrator is arranged to integrate the first signal received from the digital circuit and produce an output voltage across the reverse biased variable capacitance device such that the output voltage causes the capacitance of the reverse biased capacitor to change if the pixel clock is not operating at the predetermined desired pixel clock frequency.

Abstract: An apparatus and method for detecting a synchronizing signal in a digital TV receiver which adopts a VSB mode is disclosed. The apparatus includes a correlation unit for obtaining a correlation value between a received signal for each unit of symbols and a preset reference field synchronizing signal, a maximum value detector for detecting a location of the symbol having a maximum correlation value while performing counting operation for a unit of a variable constant added to the number of symbols corresponding to one field, a synchronizing lock signal generator for generating a synchronizing lock signal by testing reliability of the symbol location detected by the maximum value detector, and a synchronizing location controller for calculating a relative location of the symbol location having a maximum value to generate a corresponding synchronizing signal if the synchronizing lock signal is generated by the synchronizing lock signal generator.

Abstract: A method for detecting a synchronous signal contained in an input image signal is provided. In the method, horizontal and vertical periods are established during which horizontal and vertical synchronous signal pulses contained in the input image signal are counted, respectively. Then, minimum and maximum horizontal values which correspond to the horizontal synchronous signal pulses contained in the horizontal period are established, and minimum and maximum vertical values which correspond the vertical synchronous signal pulses contained in the vertical period are established. Afterwards, the horizontal and vertical synchronous signal pulses are counted during the horizontal and vertical periods to respectively obtain first and second counted values.

Abstract: There can be solved a problem in which a lock range is narrowed by using an oscillator such as a ceramic having a high Q and a horizontal deflection frequency generating system compatible with all horizontal deflection frequencies of a variety of television systems cannot be formed without difficulty. This system includes a frequency-fixed oscillator oscillating at a frequency f0 sufficiently higher than a deflection frequency fh in a multi-scan display, a first counter for counting a clock outputted from said oscillator in a descending order, a duration in which an integer n which results from rounding a decimal point of a value obtained by a division of f0 fh is divided by an integer m smaller than n and said first counter counts a value k thus obtained k times is set to one cycle and a duration in which a second counter for counting a value m times repeats the counting m cycles is set to one period and thereby generating a deflection frequency fh.

Abstract: A phase controller of a horizontal drive pulse fed into a horizontal deflection circuit supplying a horizontal deflection pulse, and a control method of the same are disclosed. A frequency discriminator identifies a format of video-input-signal by detecting a frequency of the horizontal sync signal. A reference phase generator generates a reference phase signal based on the output from the frequency discriminator. A sawtooth waveform generator generates a sawtooth waveform signal responsive to the output from the frequency discriminator. A phase difference voltage detector outputs a phase difference voltage responsive to the phase difference between the reference phase signal and the horizontal deflection pulse. A phase control signal generator generates a phase control signal using the phase difference voltage and the sawtooth waveform signal. Horizontal drive pulse generator outputs a horizontal drive pulse having a phase responsive to the phase control signal.

Abstract: The present invention relates to a system and method for generating a blanking period indicator signal from sync information in video timing. The invention comprises an auto polarity detect processor adapted to automatically detect the polarity of at least one sync signal and a generation processor adapted to generate a DE signal.

Abstract: A timing recovery device in a digital television receiver using a VSB system is disclosed. In the present invention, the timing recovery device independently determines whether the detected hsync signal is reliable and operates if the detected hsync signal is reliable.

Abstract: A self-diagnostic arrangement for a video display apparatus and method effectuating the same is disclosed. The apparatus according to the present invention includes a cable connector, amplifiers and a cathode ray tube and comprises a microprocessor storing information on a display status, for selectively switching signals to generate horizontal and vertical sync signals for displaying a variety of self-diagnostic displays, an on screen display IC for supplying a blanking signal and a video signal correspondingly responsive to information supplied from the microprocessor and a H/V deflection circuit for supplying on screen display video. signals to the CRT. There is also provided a method of self-diagnosis, which comprises the steps of generating internal horizontal and vertical sync.signals sync signals of predetermined frequency levels and displaying self-diagnostic screens representing video component colors and a display status.