Abstract: A frame signal phase adjuster comprises units for inputting a parallel clock and a reference signal (22-4 and 22-1); generating a frame signal from the reference signal (22-1), adjusting a phase of the frame signal (22-3), generating an adjusted frame signal synchronized by the parallel clock from the parallel clock and the adjusted frame signal (22-4), generating a frame reset pulse signal based on the parallel clock and the adjusted frame signal synchronized by the parallel clock (22-2), and outputting the frame reset pulse signal (22-2). The unit (22-4) adjusts the phase of the frame signal so that the frame signal is constantly HIGH or LOW throughout a setup time and a hold time.

Abstract: A sync generator (genlock) (10) for frequency and phase locking an incoming video signal to a system clock (12) includes a digitizer (16, 22) for digitizing the incoming video signal to yield a digitized color sub-carrier burst component. A numerically controlled oscillator (15) clocked by the system clock generates a phase lock reference signal for locking to the incoming video signal. Phase detection means logic unit (42, 74) sense a static phase offset magnitude from an ideal 90° phase offset between the digitized color sub-carrier burst component and the numerically controlled oscillator output signal. In accordance with the sensed static offset, a static phase error nulling circuit (70) generates a compensating offset in accordance for input to the system clock (27) to drive the static offset to zero, thus achieving frequency and phase locking.

Abstract: The invention provides an image display apparatus that efficiently adjusts a video display even when a change takes place in an input signal. The image display apparatus includes a video input device that receives a video signal, a video display that displays an optical image based on an input signal S1 from the video input device, and a video signal adjusting device that adjusts the display setting of the video display based on a signal mode of the input signal S1. The image display apparatus further includes a determining device that causes the video display adjusting device to adjust the display setting of the video display. The determining device includes an apparatus startup detector unit that detects whether a startup of the image display apparatus creates a change in the input signal, and a signal change detector unit that detects the change in the input signal. The determining device determines whether to cause the video display adjusting device to adjust the display setting only when it is needed.

Abstract: An optical transfer system having a transmitter and a receiver converts an externally-applied video signal into an optical signal and restores the optical signal to the original video signal The system includes a video controller, a transmitter, a transmission photo diode, an optical transmission line, a reception photo diode, and a receiver. The video controller separates color signals and a horizontal/vertical synchronous signal from the video signal, and transmits the color signals and the horizontal/vertical synchronous signal in response to externally-applied predetermined data enable and clock signals. The transmitter skew-compensates and compresses signals received from the video controller and converts the compressed signals into a driving current. The transmission photo diode converts the driving current into an optical signal and outputs the optical signal. The optical transmission line is comprised of a predetermined number of channels, and transmits the optical signal.

Abstract: The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Abstract: A display apparatus has a clock generating circuit, a drive waveform generating circuit, and a display panel. The drive waveform generating circuit is used to generate a drive waveform by using a clock from the clock generating circuit, and the display panel is used to display an image in accordance with the drive waveform. The clock generating circuit generates a clock whose frequency varies continuously. The drive waveform generating circuit drives the display panel by outputting a drive waveform whose frequency varies in accordance with the frequency varying clock so as to spread out noise that the display panel emits. Therefore, peak values of the noise can be reduced.

Abstract: A system and method for correcting non-periodic event time of arrival data in a control system. The system and methods are particularly applicable to the speed and phase control of a color wheel used with spatial light modulators. The circuitry automatically and accurately compensates for non-periodic index signals occurring when one or more index marks on the color wheel are misplaced. The system adds to or subtracts clock pulses from the actual time of arrival of a specific index mark until the corrected value equals the desired or nominal value. The system then generates a PWM signal for controlling the speed and phase of the color wheel.

Abstract: A pixel clock generating circuit is provided in which a digital circuit generates a first signal corresponding to the relative frequency of the pixel clock as compared with a predetermined desired pixel clock frequency. An analog circuit is electrically coupled to the digital circuit in which the analog circuit has a reverse biased variable capacitance device, an integrator and a comparator circuit. The reverse biased variable capacitance device has an anode and a cathode. The integrator has an input coupled to the digital circuit and an output coupled to the cathode of the reverse biased variable capacitor. The integrator is arranged to integrate the first signal received from the digital circuit and produce an output voltage across the reverse biased variable capacitance device such that the output voltage causes the capacitance of the reverse biased capacitor to change if the pixel clock is not operating at the predetermined desired pixel clock frequency.

Abstract: A device for correcting the phase of a vertically distorted digital picture receives picture data and a vertical phase correction signal, and assigns lines of the digital picture to a first half picture and to a second half picture. The lines of the second half picture are phase corrected with respect to the first half picture and the first and second half pictures are displayed sequentially. The phase correction is determined in response an increment signal that describes the change of an imaging factor in the veritcal direction of the digital picture on a line-by-line basis and a picture position signal indicative of whether the first half picture or the second half picture is being output.

Abstract: A method and apparatus for estimating a true horizontal resolution by determining a temporal spacing of a cumulated sum pattern of a detected rising feature edge. If the temporal spacing is approximately equal to n (which is a positive, non-zero integer, and is equal to the number of sub-pixels associated with a pixel) then the estimated horizontal resolution is the true horizontal resolution.

Abstract: An apparatus to compensate a color carrier in an image processing system to convert an input analog image signal into a digital image signal includes a detector, a phase-locked loop unit, a difference detector, and a color signal processor. The detector detects a frequency of the color carrier in a color signal of the digital image signal. The phase-locked loop unit generates a subcarrier frequency by performing a phase-locked loop operation on a system clock signal applied to the image processing system. The difference detector detects a difference between the frequency of the color carrier and the subcarrier frequency. The color signal processor compensates for a phase deviation of the color carrier of the color signal using the subcarrier frequency generated by the phase-locked loop unit.

Abstract: A method and an apparatus for generating a coast signal for enabling or disabling a phase comparator in a phase-locked loop of image processing apparatus. The phase-locked loop generates a sampling clock signal, which is used to convert an analog image signal into a digital image signal in response to a composite sync signal including a vertical sync signal and a horizontal sync signal. An enabled coast signal is generated at period other than detected horizontal sync period to prevent the phase comparator from comparing the composite synce signal to a reference signal, and a disabled coast is generated at periods corresponding to the horizontal sync period to permit the phase comparator to compare the composite synce signal to the reference signal.

Abstract: A method, apparatus, and system for determining a true horizontal resolution of an analog video signal arranged to display a number of features having associated feature edges on a display each of which were created with a true pixel clock is described. For a test horizontal resolution, if it is determined that substantially all of the feature edges have substantially the same phase relationship to a test pixel clock, then the test horizontal resolution is the true horizontal resolution.

Abstract: A clock generating apparatus is provided for producing an output clock signal responsive to a source clock signal with a source frequency and a reference clock signal with a reference frequency. The clock generating apparatus includes a counting sequence generator, a measuring value generator and a ratio counter. The counting sequence generator is used for outputting a series of counting values in response to a triggering signal with a specified period determined by the source frequency of the source clock signal and a predetermined counting value. The measuring value generator generates a measuring value by operating the series of counting values according to a predetermined formula. The ratio counter produces the output clock signal with a frequency determined by the source frequency of the source clock signal and the measuring value.

Abstract: A translator demodulates a received digital television signal so as to produce a digital data stream, a symbol clock, and a byte clock, wherein the symbol clock and the byte clock are corrupted by phase noise. The digital data stream is written into a buffer in response to the corrupted byte clock. The corrupted symbol clock is applied to a frequency/phase locked loop having a narrowband loop filter. The frequency/phase locked loop produces a regenerated symbol clock having substantially no phase noise. The digital data stream is read from the buffer in response to the regenerated symbol clock. The digital data stream read from the buffer and the regenerated symbol clock are applied to a modulator for re-broadcasting of the received digital television signal.

Abstract: An image processing apparatus, which displays an image corresponding to a synchronizing frequency change-image signal, which is obtained by changing a frequency of a synchronizing signal of an image signal, and an other image corresponding to an other image signal on a same display screen. The apparatus comprises a monitoring device and a synchronizing control device. The monitoring device monitors temporal relationship between the synchronizing signal of the synchronizing frequency change-image signal and a synchronizing signal of the other image signal. The synchronizing control device performs frequency regulation for the synchronizing frequency change-image signal based on the monitoring results from the monitoring device so as to prevent one of the synchronizing frequency change-image signal and the other image signal from passing the other thereof on the display screen.

Abstract: A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst signal where dramatic changes in the pixel clock frequency result.

Abstract: Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency an optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from exsisting methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

Abstract: The frequency of the dot clock in an image display device is adjusted by calculating a first image characteristic from the differences between adjacent picture elements, varying the phase of the dot clock, determining whether the frequency of the dot clock is correct from the way the first image characteristic varies according to the phase of the dot clock, and changing the frequency if it is incorrect. The first image characteristic is, for example, the maximum difference, the histogram distribution of the differences, or a ratio calculated from the histogram. The phase of the dot clock may be adjusted according to a second image characteristic, such as the difference between a single pair of pixel values, which is also measured over a range of dot-clock phase settings.

Abstract: A method of automatic generation of horizontal synchronization of an analog signal to a digital display is described. Accordingly, a number of features are found and for each of a range of test Htotal values, a pixel co-ordinate value for each of the found features is calculated. A pixel co-ordinate remainder value associated with each of the pixel co-ordinate values is determined and a maximum gap value of the pixel co-ordinate remainder values associated with a true horizontal resolution. is determined.

Abstract: A phase-locked loop is provided which is operable to lock the sampling clock (pixel clock) to the incoming horizontal sync pulse contained within composite video information. Given the input signal is a VCR signal or a normal noise-free signal, there exists two modes of operation, coarse lock mode and fine lock mode, which are used in controlling the phase-locked loop. In the coarse lock mode, coarse corrections are made to a horizontal discrete time oscillator so that a fast lock may be achieve using the fine lock mode. Coarse corrections are based on a normalized sum of weighted pixels collected within a narrow gate window. Lock is achieved when the falling edge is centered within the window. Given the input signal is a television signal having noise, there exists one mode of operation where the flat window phase detector is used instead of coarse lock mode to bring the sync edge to fall within the window, where the flat window normalization constant is tuned.

Abstract: A signal processing apparatus and method for up or down conversion of an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.

Abstract: A method to generate an optimum phase shifted sampling clock for sampling a synchronized video signal A(t) having a synchronization signal SYNC pulse is achieved. The method comprises, first, generating a sampling clock having a first edge aligned with a trailing edge of the SYNC pulse. The sampling clock period comprises the SYNC pulse period divided by M. Second, the number of sampling clock cycles N is counted from the trailing edge of the SYNC pulse until the A(t) value at the first edge of the sampling clock exceeds a minimum value. Third, the sampling clock and the SYNC pulse are phase shifted forward until the A(t) value at the first edge of the sampling clock first exceeds a minimum value on clock cycle N?1 to thereby establish a worst case phase shift of the sampling clock. Finally, A(t) is sampled at an offset from the worst case phase shift to thereby generate an optimum phase shifted sampling clock.

Abstract: In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inch to the horizontal discrete time oscillator to make corrections in its timing to maintain lock to the sync input. The horizontal discrete time oscillator output is used to produce a pixel clock which drives the color discrete time oscillator in a color phased locked loop. A microprocessor reads a phase error between the color burst input and the color local oscillator frequency and writes an increment incsc to the color discrete time oscillator to maintain lock to the color burst. The horizontal phase locked loop adjusts inch that varies about nominal increment (nom_inch) by ?h. The feed forward error correction for the adjustment to the color discrete time oscillator is the nomimal increment (nom_incsc) and a feed forwarded scaled version of ?h.

Abstract: An inexpensive and simple circuit for improving an image quality of a dynamic image, with appropriate processing flexibly performed for dynamic image qualities also for a plurality of input signal sources.

Abstract: A sampling pulse generator for an electronic endoscope that comprises a CDS circuit, OR circuits, a clock pulse generator, a shift counter, first and second switch groups, EEPROM and a CPU, is provided. The generator cyclically generates clock pulses. The pulses are cyclically counted between 0 and 9 by the counter. The counter has ten output terminals that correspond to each of the count numbers. A signal is only output to a terminal corresponding to the current count number. Each of the first and second switch groups has ten switches that are connected to each of the terminals. With data in the EEPROM, the on-off states of the switches are set by the CPU. The CCD drive pulses are generated by signals from the terminals via OR circuits. The clamp pulse and sample-hold pulse are generated by signals from the switch groups which are set in the on state.

Abstract: A frequency range bounder for limiting the frequency of a voltage controlled oscillator uses a multiplexer that responds to comparator inputs indicating whether an input control signal will allow the oscillator frequency to go beyond a predetermined range. If the control signal keeps the frequency within the range, the control signal is sent directly to an oscillator driver. If the control signal is above or below the range, the multiplexer outputs an alternative value as the control signal. As a result, the oscillator frequency is prevented from extending beyond an allowable tolerance range.

Abstract: A frequency range bounder for limiting the frequency of a voltage controlled oscillator uses a multiplexer that responds to comparator inputs indicating whether an input control signal will allow the oscillator frequency to go beyond a predetermined range. If the control signal keeps the frequency within the range, the control signal is sent directly to an oscillator driver. If the control signal is above or below the range, the multiplexer outputs an alternative value as the control signal. As a result, the oscillator frequency is prevented from extending beyond an allowable tolerance range.

Abstract: Digital filter for filtering a digital input signal with a variable filter length (l), it being possible to switch over the filter length (l) of the digital filter (8) as a function of a variable input clock frequency (fin) of the digital input signal without the ratio between the input clock frequency (fin) and an output clock frequency (fout) of the filtered digital output signal which is output by the digital filter (8) changing.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.

Abstract: A system for overlaying a motion video signal onto an analog signal on a display. The system includes a motion video processing unit for receiving and processing the motion video signal into a signal having an analog video format, a video format analyzer and synchronizer device for receiving the analog signal and for determining video timing parameters and a corresponding original pixel clock of the analog signal and for controlling video timing parameters of the motion video signal to match the video timing parameters of the analog signal determined by the video format analyzer and synchronizer device so as to provide an output motion video signal which is synchronized with the analog signal and a display determining device for determining the display of the analog output signal or the synchronized output motion video signal on the display.

Abstract: A jitter canceling apparatus is provided for canceling jitter in a video signal. For processing a video signal, using as a reference an internal synchronization signal and an external synchronization signal different from the internal synchronization signal in the jitter canceling apparatus, an external synchronization signal generator generates the external synchronization signal from an external reference signal. A jitter detector detects time difference jitter, which is jitter in a time difference between the internal and external synchronization signals. The external synchronization signal generator controls the external synchronization signal generating operation in response to the detected time difference jitter to reduce the time difference jitter.

Abstract: A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.

Abstract: A liquid crystal display apparatus comprises a PLL circuit, a phase adjuster, a picture-data-sampling circuit, a liquid crystal display driver, a video signal processor, and a liquid crystal display panel. The phase adjuster comprises a delay circuit, a comparator, a counter, and a controller. The PLL generates a dot clock which is delayed by the delay circuit by a delay time designated by the controller to be a sampling clock. The counter counts the number of sampling edges of the sampling clock from a negative edge of a horizontal synchronization signal to a positive edge of a binarized video signal supplied from the comparator. The controller observes the number of sampling edges while adjusting the delay to determine the worst sampling clock and sets the best sampling clock whose phase is at a straight angle to the phase of the worst sampling clock.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.

Abstract: A new method for phase locking the color wheel in a color field-sequential projection display. At periodic interrupts, the method determines which color wheel index mark should be driven into coincidence with the Vsync signal. It does this by measuring the delay between Vsync and any index mark and then based on the current state of the spoke-sync counter and this delay value, a new next state is determined to drive the nearest index mark to Vsync to the Vsync position. At worst case this technique requires only one-half a color wheel revolution of phase correction to re-lock the system when the TV channel is changed and for the 5/2 and 7/2 spoke-sync modes, popular 50 Hz and 60 Hz modes, only one-quarter revolution of phase correction of the color wheel is required for re-lock.

Abstract: The invention relates to a tuner with at least a first and a second frequency band and with means for effecting a switch-over between the frequency bands, which tuner comprises a signal input terminal for the supply of a frequency information signal. The invention is characterized in that the tuner comprises a band selection circuit which is provided for the selection and control of one frequency band at a time, and in that the tuner comprises a frequency search function for tuning to a frequency, which function in a first step is designed to test the tuning possibility of the frequency in the first frequency band and, if tuning in the first frequency band is not possible, in a second step is designed for testing the tuning possibility of the frequency in the second frequency band.

Abstract: The invention may relate to a digital frequency adjuster for adjusting a first frequency of a first signal. The digital frequency adjuster may comprise a first digital delay line and a first control circuit. The first digital delay line may comprise a plurality of taps. The first digital delay line may be configured to (i) receive the first signal and (ii) generate a second signal. The first control circuit may be configured to control dynamic assertion of respective ones of the taps at a rate such that the second signal has a second frequency different from the first frequency of the first signal.

Abstract: A method for monitoring the setting of the phase between the pixel clock rate of a graphics card and the sampling clock rate of a flat screen having an analog interface includes the steps of setting a flag if the phase of the flat screen has been set by the user. The flag is interrogated upon switching on the flat screen and/or upon a change of the video mode at a computer and/or an exchange of the graphics card and/or upon an exchange of the computer. A display is provided or a setting of the phase is initiated if, during the interrogation, it is ascertained that the flag is not set. A device for monitoring the setting of the phase between the pixel clock rate of the graphics card and the sampling clock rate of the flat screen is also provided.

Abstract: The present invention relates to a broadband switching drive compensating circuit for a video display device, which comprises a horizontal size detecting unit for detecting a horizontal size; a horizontal frequency detecting unit for detecting a horizontal frequency; a first DC voltage generating unit for generating a first DC voltage according to the detected horizontal size; a second DC voltage generating unit for generating a second DC voltage according to the detected horizontal frequency; a driving current compensating unit for altering a B+1 driving current according to the generated first and second DC voltages; and a horizontal deflection unit for switching a horizontal output transistor according to the altered B+1 driving current and then supplying a sawtooth current to a horizontal deflection coil.

Abstract: A method of reducing noise in a digitally sampled image in which entire frame images are sampled to form a histograms which are used to determine the relative noise level of the static image over a period of several frames. A frame of data is sampled using a pixel clock signal. A histogram of that frame is constructed which involves counting the number of occurrences of a value of color or range of colors in the image and storing that number. A second frame is sampled and a histogram is constructed for the second frame. A comparison is made between the two sets of histogram information. The difference gives the system controller a relative measure of the digital noise present in the static image. This process is repeated over time giving wherein each of the histograms shows a change. After a set number of steps are performed the pixel clock phase is set to correspond to the phase having the least change.

Abstract: An apparatus for generating a sync of a digital television in which an analog signal inputted to a digital television constantly provides stabilized synchronization regardless of a standard or a nonstandard so as to be processed.

Abstract: A PLL circuit according avoids any large change in a frequency in a VCO (5) even if an input horizontal synchronization signal suddenly changes or a level of the frequency decreases to a predetermined value or less, or disappears. The PLL circuit comprises a switch (3) to be provided on an output side of a phase comparator (2) to control an output voltage of the VCO by connecting to an AFC filter (4) and supplying a phase difference current according to a phase difference, during the time the horizontal synchronization signal is supplied. The comparator (2) compares a phase of an Hin signal through a delay circuit (1) with a phase of a return (RET) signal through a dividing circuit (6) and a delay circuit (7) from the VCO. With this structure, the comparator does not supply any phase difference current and does not make the VCO change at the time when the Hin signal is disappeared.

Abstract: Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

Abstract: A video signal processor reduces the deterioration of image quality due to the superposition of noise on a sync signal included in a luminance signal. A frequency discriminator outputs a first error signal if a ratio of the frequency of a frequency-modulated signal during a sync-signal interval to the frequency of a reference frequency signal is smaller than a predetermined ratio. Alternatively, the discriminator outputs a second error signal if the ratio is greater than the predetermined ratio. If the first error signal has been input to a frequency controller a preset number of times or more during an interval before the second error signal is input thereto, the controller instructs a frequency modulator to increase the frequency of the frequency-modulated signal.

Abstract: The process is characterized in that it stores a position of the write pointer PW on receipt of the synchronization signal S1 relating to the input signal so as to provide a value PW-IN, and on receipt of the synchronization signal S2 relating to the output signal so as to provide a value PW-OUT, in that it dynamically calculates an interpolation phase &agr; (12, 13, 14, 15) such that: α = P W ⁢   ⁢ _OUT - P W ⁢   ⁢ _IN Δ ⁢  

Abstract: A multiplier circuit multiplies a first output signal (fVCO) that has been generated by a conventional automatic phase-controlled loop circuit with a second output signal (fIF+fref) that has been generated by a phase-locked loop circuit based on a reference signal (fref). A phase difference detector circuit and an edge detector circuit receive a result of this multiplication, and carry out an edge detection (such as, for example, a pulse density corresponding to a frequency difference between a video intermediate frequency fIF and the first output signal fVCO). An automatic frequency tuning voltage is generated based on a result of this edge detection.

Abstract: Timing recovery device for recovering a symbol clock from a received broadcasting signal, wherein a sign is used as a timing error, which is extracted from a result of multiplication of a difference of two symbol samples and an intermediate sample thereof, thereby very great average gain with respect to the timing error, that shortens a time period required for capturing the timing error. Particularly, since the very great average gain is obtainable even in a case a 0 dB presents, the timing offset can be captured at a short time period.

Abstract: A phase controller of a horizontal drive pulse fed into a horizontal deflection circuit supplying a horizontal deflection pulse, and a control method of the same are disclosed. A frequency discriminator identifies a format of video-input-signal by detecting a frequency of the horizontal sync signal. A reference phase generator generates a reference phase signal based on the output from the frequency discriminator. A sawtooth waveform generator generates a sawtooth waveform signal responsive to the output from the frequency discriminator. A phase difference voltage detector outputs a phase difference voltage responsive to the phase difference between the reference phase signal and the horizontal deflection pulse. A phase control signal generator generates a phase control signal using the phase difference voltage and the sawtooth waveform signal. Horizontal drive pulse generator outputs a horizontal drive pulse having a phase responsive to the phase control signal.

Abstract: A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (Hsnyc) that controls a line scan rate, and a vertical synchronizing signal (Vsnyc) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated.