Abstract: In a multimedia SOC that includes a plurality of jack sense modules coupled to the plurality of video output pins, a processing module functions to: enable one or more of the plurality of jack sense modules to determine a video connection to the SOC, enable a video decoder in a first mode when the video connection is of a first type, and enable the video decoder in a second mode when the video connection is of a second type

Abstract: A method, apparatus, and system for determining a horizontal resolution and a phase of an analog video signal arranged to display a number of scan lines each formed of a number of pixels is described. A number of initialization values are set where at least one of the initialization values is a current horizontal resolution and then a difference value for each immediately adjacent ones of the pixels is determined. Next, an edge flag value based upon the difference value is stored in at least one of a number of accumulators such that when at least one of the accumulators has a stored edge flag value that is substantially greater than those stored edge flag values in the other accumulators, then the horizontal resolution is set to the current resolution.

Abstract: A method and apparatus for a digital video display. A digital display device receives an analog signal representing an image formed of pixels in video lines and a signal containing a synchronization waveform for the image. An analog-to-digital converter (ADC) receives the analog signal and converts it to a sampled digital waveform. A phase-locked loop including a programmable frequency divider controls the sampling time for the ADC. The programmable frequency divider is controlled by a dividing-ratio algorithm that selects a dividing ratio, measures the number of pixels in a video line using the dividing ratio, and recomputes the dividing ratio by multiplying the selected dividing ratio by the expected number of pixels in a video line and dividing by the measured number of pixels. The sampling phase for the ADC is selected by a sampling-phase control algorithm that minimizes a function representative of the flatness of the sampled digital waveform.

Abstract: A TV signal determining system utilized for determining a type of a TV signal includes: a detection unit, for utilizing a predetermined profile to detect if the TV signal has a signal segment corresponding to the predetermined profile to generate a detection result signal; and a determining unit, coupled to the detection unit, for determining the type of the TV signal according to the detection result signal. A TV signal processing system utilizing the TV signal determining system and a related method are also disclosed.

Abstract: A programmable digital black level calibration circuit comprises a combining circuit, a digital programmable gain amplifier (PGA), and a black level feedback circuit. The combining circuit combines a digital image signal for optical black (OB) pixels and a feedback signal and outputs a digital PGA input signal. The PGA amplifies the digital PGA input signal by a PGA gain value and outputs a digital PGA output signal. The black level feedback circuit receives the digital PGA output signal and a target black level and in response outputs the feedback signal such that a black level of the OB pixels is calibrated with respect to the target black level. The programmable digital black level calibration circuit calibrates the black level in pure digital domain using signed data buses. The target black level is adjustable to a desired positive or negative value independent from the PGA gain value.

Abstract: The present invention proposes a method for generating a digital video signal from an analog input video signal, which prevents picture jitter in the digitized video signal when the analog input video signal is not in complete conformity with a standard. According to the invention, the method includes the steps of: detecting the type of signal source; in case the type of signal source is a non-standard type, detecting the existence of an error state; converting the analog input video signal to a digital video signal; in case an error state exists, replacing an error prone part of the digitized video signal with a substitute signal part; and in case the type of signal source is a standard type or no error state exists, keeping the digitized video signal unchanged.

Abstract: Disclosed herein is a camera system and camera controller having a modularized design. Camera control functions within the controller are distributed among a number of modules, each module performing a component task of controlling a camera. Individual modules can perform tasks such as generating clock signals, digitizing an analog video signal, and providing multiplexed digital video output. Modules communicate with each other over a common bus sufficient to carry the signals necessary to control the camera. The system implements a RAM-based digital sequencer that provides the capability of loading bit patterns into memory and using these patterns to generate waveforms for clocking a CCD. Clock and readout sequences can be composed in a high level language, compiled and uploaded into the controller. Adjustable clamp and sample signal delays used in digitizing an analog video signal provide the capability to optimize the performance of the system in a given application.

Abstract: An analog-to-digital converting system for converting a composite video signal into a digital signal according to a synchronized clock. The analog-to-digital converting system includes an analog-to-digital converter (ADC), a color burst phase estimator and a phase-locked loop (PLL). The ADC converts the composite video signal to the digital signal according to the synchronized clock, wherein the synchronized clock is synchronized to a frequency of a color burst of a chrominance signal of the composite video signal. The color burst phase estimator, coupled to the ADC, estimates the phase of the color burst carried on the composite video signal. The PLL, coupled to the color burst phase estimator, generates the synchronized clock according to the phase of the color burst estimated by the color burst phase estimator.

Abstract: Disclosed herein is a camera system and camera controller having a modularized design. Camera control functions within the controller are distributed among a number of modules, each module performing a component task of controlling a camera. Individual modules can perform tasks such as generating clock signals, digitizing an analog video signal, and providing multiplexed digital video output. Modules communicate with each other over a common bus sufficient to carry the signals necessary to control the camera. The system implements a RAM-based digital sequencer that provides the capability of loading bit patterns into memory and using these patterns to generate waveforms for clocking a CCD. Clock and readout sequences can be composed in a high level language, compiled and uploaded into the controller. Adjustable clamp and sample signal delays used in digitizing an analog video signal provide the capability to optimize the performance of the system in a given application.

Abstract: An image signal processor and a method for processing an image signal thereof are disclosed. When the image signal processor executes an automatic chroma gain control (ACC), the image signal processor adjusts a variable rate of ACC gain according to a size of an input color signal to reduce a time for processing the ACC. Even if a difference between the size of the input color signal and the size of a reference color signal is large, the ACC is rapidly processed. As a result, transient phenomenon disappears from a screen.

Abstract: This is an endoscope apparatus which has an endoscope which picks up an image of a sample using a solid state image pickup element and outputs an image pickup signal, and a processor which processes the above-mentioned image pickup signal, generates HDTV and SDTV serial digital video signals, switches one side of those selectively, and performs a serial output, in which the serial digital video signal switched selectively by the above-mentioned processor is output through a first connector, the above-mentioned processor is equipped with a discrimination signal generating section which is linked with selection switching of the above-mentioned HDTV or SDTV serial digital video signal to generate an HDTV/SDTV discrimination signal which can discriminate the above-mentioned HDTV or SDTV serial digital video signal, and the discrimination signal is output through a second connector different from the above-mentioned first connector.

Abstract: A digital television chip having a reduced layout size is disclosed, comprising a multiplexer, and first and second converting units. The multiplexer, according to a control signal, outputs one of S-video signals SY and SC to the first converting unit, outputs the other of the S-video signals SY and SC to the second converting unit, outputs one of Tuner CVBS signals VIF and SIF to the first converting unit, outputs the other of the Tuner CVBS signals VIF and SIF to the second converting unit, or outputs a CVBS Line-in Video signal to one of the first and second converting units, for reducing the size of the chip. The first converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a first digital signal for signal processing. The second converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a second digital signal for signal processing.

Abstract: The invention relates to a multiplexed video digitization system and method. The system includes a plurality of analog video signals, a multiplexer to select one of the plurality of analog video signals, and an analog-to-digital converter to convert the selected analog video signal into a digital video signal. The plurality of analog video signals may include component video signals, red, green, and blue signals, or s-video signals. The multiplexer may include control logic to select the one of the plurality of analog video signals. The system may include a plurality of sample and hold circuits to insure time aligned sampling of the corresponding plurality of video signals.

Abstract: A high-speed video signal processing system, which includes a reception end for receiving analog signals; a plurality of analog to digital converters coupled to the reception end for converting analog signals received from the reception end to digital signals according to control signals; and an interleaving controller coupled to the plurality of analog to digital converters for generating the control signals to selectively enable the plurality of analog to digital converters according to a predetermined sequence.

Abstract: A video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal reduces the buffer size required to compensate for line-to-line variations in an unstable video source. A video signal is sampled at a predetermined rate and decimated by a selectable decimation factor prior to buffering. By selecting different decimation factors, the effective length of the buffer is changed from short duration for stable input signals and to longer duration for unstable input signals. A video signal quality detector is employed to provide a selection input that adjusts the decimation factor and also the loop bandwidth of a clock generator that provides the output clock for the buffer, which is generated from the input signal via a phase-lock loop (PLL). The operation of the system automatically varies from highly responsive for stable video input signals to less responsive for unstable video input signals, providing improved stability in the video output.

Abstract: A picture signal processing device includes an A/D conversion unit configured to convert an input analog picture signal into a digital picture signal; an automatic image correction unit configured to correct the digital picture signal from the A/D conversion unit; a narrowing-down unit configured to narrow down possible formats of the analog picture signal based on horizontal and vertical signal frequencies of the analog picture signal, horizontal and vertical synchronizing signal polarities and vertical line count; and an identification unit configured to identify the format of the input analog picture signal from among a plurality of narrowed-down candidate signal formats.

Abstract: A signal processing device of the present invention includes: an input unit which inputs an analog video signal; an A/D converter which converts the analog video signal to a digital video signal; a detecting unit which detects a level in a predetermined period of the digital video signal output from the A/D converter; a difference output unit which detects a difference between the level detected by the detecting unit and a desired value; a modulating unit which performs sigma-delta modulation on an output from the difference output unit; and a clamping unit which performs a clamping process on the analog video signal input by the input unit based on an output from the modulating unit and which outputs the clamped analog video signal to the A/D converter.

Abstract: A video signal processing circuit is supplied with an analog composite video signal formed by combining at least a luminance signal with a sync signal, and processes the analog composite video signal. The video signal processing circuit has an analog filter which removes high-frequency components from the analog composite video signal, a sync separation circuit which separates a sync signal from an output signal from the analog filter, an AD converter which performs AD conversion on the analog composite video signal, and a digital video signal processing circuit which performs predetermined video signal processing on the composite video signal digitized by the AD converter, by using the sync signal obtained by the sync separation circuit.

Abstract: A scene change detection device according to the present invention includes an audio information determination part detecting silent state of audio signal to output silence detection time information, an image information determination part detecting brightness change or decreased level of brightness of an image in image signal to store scene change time information indicating time detecting the brightness change or decreased level of brightness, a scene change candidate point detector outputting scene change candidate time based on the silence detection time information and the scene change time information, and an output determination part outputting scene change detection information based on time difference between successive first scene change candidate time and second scene change candidate time and a detection maximum value.

Abstract: Provided is a video signal processing device that can reduce power consumption within an analog signal processing unit not only during an invalid frame period of a video signal but also during a blanking period within a valid frame period, thus enabling further reduction of the power consumption. The video signal processing device that performs signal processing on an analog video signal inputted from outside includes: an analog signal processing unit including: a CDS/AGC unit that samples the analog video signal and amplifies the sampled analog video signal; and an AD converting unit that converts the resulting analog video signal from analog to digital, and a timing control unit that controls the analog signal processing unit to switch between an operating mode and a standby mode.

Abstract: A first clamping unit clamps a base voltage of an input image signal to a predetermined reference voltage. A sampling-and-holding unit samples and holds the image signal after clamping or a reference signal that becomes the base voltage of the image signal. An amplifying unit amplifies the image signal sampled and held by the sampling-and-holding unit. An analog-to-digital converting unit converts the image signal after amplification into a digital image signal. A second clamping unit clamps the reference signal to a predetermined voltage.

Abstract: A signal is temporally compressively sampled. A plurality of analog to digital converters are assembled to sample the signal. Each analog to digital converter of the plurality of analog to digital converters is configured to sample the signal at a time step determined by a temporal sampling function. The signal is sampled over a period of time using the plurality of analog to digital converters. Each analog to digital converter of the plurality of analog to digital converters produces a measurement resulting in a number of measurements for the period of time. A number of estimated signal values are calculated from the number of measurements and the temporal sampling function. The temporal sampling function is selected so that the number of measurements is less than the number of estimated signal values.

Abstract: Various embodiments are described herein for a universal television receiver that is capable of processing television channel signals, that are transmitted according to a variety of broadcast standards, to provide video and audio information for a desired television channel signal. The processing includes producing a coarse channel signal that includes a desired television channel signal and then applying resampling techniques to adjust a normalized bandwidth of the desired television channel signal to generally correspond to the normalized passband of a main filter that is used for each of the broadcast standards.

Abstract: Various embodiments are described herein for automatic gain control techniques that can be used by a universal television receiver that is capable of processing television channel signals broadcast according to a variety of analog and digital broadcast standards.

Abstract: Various embodiments are described herein for a universal television receiver that is capable of processing television channel signals broadcast according to a variety of analog and digital broadcast standards. In particular, various embodiments are provided for avoiding interferers in a desired television channel signal and these embodiments generally include changing sampling rate, shifting certain oscillation frequencies or changing sampling rate and shifting certain oscillation frequencies.

Abstract: A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also comprises circuitry for processing the S analog input signals, and that circuitry comprises an integer number N of analog-to-digital converters (38x) for producing a set of the integer number S of digital signals. Each digital signal in the set of S of digital signals corresponds to a respective different one of the S analog input signal, and N is less than S. The decoder also comprises output circuitry (40x, 42x), coupled to the circuitry for processing, for providing each digital signal in the set of S of digital signals to a different respective output conductor.

Abstract: A method of generating an orthogonally sampled video signal based on a line phase measure. In a first aspect the input signal is sampled by a clock locked to the average line frequency of a video input and the resulting samples are time shifted, optionally with or without interpolation, to an orthogonal sampling grid. In a second aspect input samples are taken and shifted to an orthogonal sampling grid according to a line phase measure. The line phase measure can be derived from a number of measurements or interpolated. In one embodiment a delay is employed so that a measure of a later sample is used to shift an earlier sample.

Abstract: A video signal processing system including a digital signal processing (DSP) module, a digital offset module coupled to the DSP module, a gain module, and a digital to analog converter (DAC) coupled to the DSP module and to the gain module, wherein the DAC is configured to cause the gain module to provide multiple gain signals having predetermined first values to the DAC, cause, for each of the multiple gain signals, a digital input signal value to the DAC to be ramped up, determine, for each of the multiple gain signals, a lowest digital input signal value that causes an output voltage of the DAC to be at least as high as a reference voltage, and determine a second gain value that will cause the DAC to provide a desired DAC output voltage in response to the DAC receiving a reference DAC input value.

Abstract: Display interface embodiments are provided to capture various types of analog video signals and digitize them for presentation on advanced digital displays (e.g., computer displays and television displays). The embodiments include at least an error converter channel and a reference converter channel that can each amplify an analog input signal S with a fixed gain G and a programmed gain g and convert the amplified signal to a corresponding digital code. The embodiments also include a channel controller that is configured to conduct process steps that adjust the transfer function of the error converter channel to conform to (e.g., matches) the transfer function of the reference converter channel.

Abstract: A system for overlaying a motion video signal onto an analog signal on a display. The system includes a motion video processing unit for receiving and processing the motion video signal into a signal having an analog video format, a video format analyzer and synchronizer device for receiving the analog signal and for determining video timing parameters and a corresponding original pixel clock of the analog signal and for controlling video timing parameters of the motion video signal to match the video timing parameters of the analog signal determined by the video format analyzer and synchronizer device so as to provide an output motion video signal which is synchronized with the analog signal and a display determining device for determining the display of the analog output signal or the synchronized output motion video signal on the display.

Abstract: Analog-to-digital converters (ADCs) generally make code errors as they convert analog display signals to digital display signals of digital displays. Code-correction structures are provided that correct these code errors by initially configuring the ADCs to provide digital signals with redundant resolution. In particular, analog display signal having 2N discrete analog levels are converted with M-bit ADCs wherein M exceeds N. This redundancy is utilized with a controller that distinguishes differences between an occurrence pattern of digital codes and a desired error-free pattern of digital codes. Subsequently, the controller corrects the digital code to reduce the observed differences.

Abstract: An AV player chip includes a TV encoder, a timing controller, a multiplexer and a plurality of digital-to-analog converters. The TV encoder is used for transforming a first image signal into a TV video signal. The timing controller is used for generating an output signal. The multiplexer includes a first set of input ends coupled to the TV encoder, a second set of input ends coupled to the timing controller, a control end and a set of output ends. The multiplexer outputs the TV video signal or the output signal to the set of output ends according to a control signal received by the control end. The plurality of digital-to-analog converters are coupled to the set of output ends of the multiplexer for transforming the TV video signal into a first playing signal and for transforming the output signal into a second playing signal.

Abstract: A video processing method and apparatus to employing an analog user interface and a digital video decoder. A working mode is provided, according to which analog control signals from the analog user interface are selectively directed to an analog-to-digital converter. The analog control signal is converted to digital control signal to accordingly control the digital video decoder.

Abstract: A video receiver for SCART input includes an input configured to receive a composite video signal, RGB signals, and a switch-indicating signal, a first digitizer module coupled to the input and including a one-bit slicer configured to receive and convert the switch-indicating signal to a one-bit digital signal, the first digitizer further including a downconverter configured to convert the one-bit signal to a multi-bit digital signal with non-abrupt transitions between a logical zero and a logical one, and a combiner module configured to receive and combine indicia of the composite video signal and the RGB signals to produce a total video output signal as a function of the indicia of the multi-bit digital signal.

Abstract: An image signal processing apparatus includes a clamp circuit that clamps an image signal having a horizontal synchronization signal, an optical black level period representing an optical black level, and an effective signal period representing an image signal for one horizontal line so as to clamp a value offset from the image signal on the basis of a first reference value during the optical black level period and to clamp the image signal on the basis of a second reference value different from the first reference value during the effective signal period, and a level computation circuit that determines the second reference value on the basis of a signal level clamped during the optical black level period.

Abstract: Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.

Abstract: A display apparatus is provided. The display apparatus includes: a signal input part which receives a video signal; a signal processor which processes the video signal inputted through the signal input part according to a predetermined offset value; a controller which compensates the offset value of the signal processor to make the output black level equal to the standard black level if the output black level is not equal to the standard black level.

Abstract: An analog front end circuit is provided, which comprises at least one converting circuit. Each converting circuit further comprises a clamper, a low-pass filter, an input buffer and a sigma-delta analog-to-digital converter. By using the sigma-delta analog to digital converter, the invention not only increases the resolution, but reduces the order of an anti-aliasing filter, therefore reducing the size and the power consumption of the analog circuit.

Abstract: The invention discloses an image processing system comprising a video source system, a transmission medium, and a television system. The image processing systems of the video source system and the television system are equipped with an additional digital-to-analog converter and an additional analog-to-digital converter.

Abstract: A video decoder in which 1) resolution quality can be improved for a given bit count analog-to-digital converter, 2) a lower bit count analog-to-digital converter can be used with substantially similar quality or 3) a combination of improved resolution quality with a lower bit count analog-to-digital converter can be done. In the preferred embodiment, a DC bias is added to the video signal after the sync portion of the composite signal has been received and prior to the active video being received. This bias is then removed after the end of the active video period. By applying this bias, the DC voltage level of the video signals is actually reduced, so that the full scale value of the analog-to-digital conversion process can also be reduced. Thus, compared to using an unbiased signal, increased A/D converter resolution is obtained. In an alternative embodiment, the sync portion can be biased upwardly during the front porch and then be returned during the back porch.

Abstract: A system such as an audio and/or video system includes a multiplexed analog-to-digital converter arrangement. The arrangement includes an ADC for converting first and second analog signals to first and second digital signals, respectively, and for outputting the first digital signal during a first time interval and outputting the second digital signal during a second time interval. A digital filter is provided for filtering the first and second digital signals to generate first and second filtered signals, respectively, and for outputting the first and second filtered signals in a time-aligned manner during a third time interval.

Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programmable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module.

Abstract: A video signal converting device is capable of converting an analog composite signal into a proper digital signal with a small delay even if the analog composite signal contains much jitter. The video signal converting device has a sampling clock output unit for outputting a sampling clock signal having a frequency which is 4n times the frequency of a burst signal contained in the analog composite signal (n represents a positive integer of 2 or greater), and an analog-to-digital converting unit for converting the analog composite signal into a digital signal based on the sampling clock signal output from the sampling clock output unit.

Abstract: The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.

Abstract: A video signal processing apparatus comprises an A/D converter for digitizing an analog video signal, an integration circuit for integrating the digitized video signal within a predetermined integration range, a picture display device for displaying a picture based on an integration output, and a control unit which, when an offset adjustment signal is inputted to the A/D converter, corrects the offset value so as to eliminate a difference between the integration value of the integration circuit and a preliminarily set specified value, and determines whether or not offset adjustment is completed based on the number of times when the corrected offset value is within a range defined by adding a predetermined error to the specified value.

Abstract: Digital dc restore methods and apparatus to restore the DC component of an analog waveform to a quantized reference value level at a given temporal point on a waveform, prior to an ADC. This may used to establish the relationship between the full scale digital value out of the ADC and the waveform being digitized. For a video signal, the Digital Value of Black, is compared with the value on the back porch of the video signal. The difference is converted to the analog domain by a DAC clocked at the Temporal Point to provide a sample and hold function. An amplifier compares the difference, mapped to one half full scale digital, to an analog common mode voltage for the ADC, removing any error due to the difference between them. Other applications include correlated double sampling of contact image sensors to remove Dark Current Offset.

Abstract: A clamping system for clamping a video signal, wherein the clamping system uses a charge-pump unit in company with a digital clamping controller to clamp the potential of the video signal, prior to the video signal being input to a programmable gain amplifier and an A/D converter, so as to reach a desired level. The charge-pump unit provides two charge-pump circuits, wherein one charge-pump circuit supplies a strong burst to boost the potential of the video signal while the video signal is below a threshold value. Otherwise, the other charge-pump circuit supplies a weak burst to fine tune the potential of the video signal when the video signal has reached the threshold value.

Abstract: An A/D conversion apparatus of a digital video system includes an A/D converter for converting an input analog video signal to a digital signal on the basis of a reference voltage value input from the outside and outputting the digital signal; and a reference voltage supplying portion for supplying the A/D converter with a predetermined number of the reference voltage value sequentially and repeatedly during a predetermined time period. Accordingly, since the quantization error can be minimized during the A/D conversion in the digital video system without increasing the number of the quantization bits, the image quality can be improved.

Abstract: An apparatus and a method for signal processing in a digital video system. The apparatus for signal processing of a digital video system has: an input unit to receive a signal quantized for M bits; and an output unit to output a value of A for (2M?N?B)times and a value of A+1 for B times during vertical scan of 2M?N times when a decimal value of high N bits is A and a decimal value of low bits of (M?N) excluding N bits is B and M>N. Accordingly, as an image signal quantized with a greater number of bits is displayed on a screen with a lesser number of bits, the quality of a picture can be improved.

Abstract: The present invention relates to methods and devices for compression and multi-screen process of digital video signals by multi-thread scaling. The method comprises. (a) a step to scale the resolutions of digital video signals; and (b) a step to compress or process for multi-screens the scaled digital video signals. The device comprises: multi-channel analog/digital converters, a compression FIFO; a multi-screen FIFO; a CPU which initializes each channel's analog/digital converter, and a video processor which transmits to the video memory. The processor for compression/multi-screen process may conduct the compression and multi-screen process sequentially from the compression FIFO and the multi-screen FIFO depending on the even/odd fields of the signals Thus, the method and device uses N analog/digital converters for the same N channels while providing the same function as the conventional system.