Abstract: One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data independently from the central processing unit. This frees the often-overburdened central processing unit from performing this time-consuming compression operation and can thereby improve the handling of video data. Thus, one embodiment of the present invention can be characterized as a method thr compressing video data in a computer system. This method includes receiving a stream of data from a current video frame in the computer system. It also includes computing a difference frame from the current video frame and a previous video frame “on-the-fly” as the current video frame streams into the computer system. The method additionally includes storing the difference frame in a memory in the computer system.

Abstract: A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The central memory interface accepts read and write memory the said plurality of processing modules and issues burst memory access requests to an external memory by gathering plural memory access requests from the processing modules.

Abstract: One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data independently from the central processing unit. This frees the often-overburdened central processing unit from performing this time-consuming compression operation and can thereby improve the handling of video data. Thus, one embodiment of the present invention can be characterized as a method for compressing video data in a computer system. This method includes receiving a stream of data from a current video frame in the computer system. It also includes computing a difference frame from the current video frame and a previous video frame “on-the-fly” as the current video frame streams into the computer system. The method additionally includes storing the difference frame in a memory in the computer system.

Abstract: A video platform architecture provides video processing using parallel vector processing. The video platform architecture includes a plurality of video processing modules, each module including a plurality of processing elements (PEs). Each PE provides parallel vector processing. Specifically, means are provided to read all elements of one or two source vector registers in each PE simultaneously, process the read elements by a set of arithmetic-logical units (ALUs), and write back all results to one of the vector registers, all of which occurs in one PE cycle. To provide such parallel vector processing capabilities, the datapath of each PE is built as a set of identical PE processing slices, each of which includes an integer arithmetic-logical unit (ALU), a vector register bank, and a block register bank. A block/vector register bank holds all I elements of row J in a two-dimensional I×J data blocks for all block/vector registers provided by the architecture.

Abstract: A personal optical viewer enables a person to view images of how the person looks wearing an accessory and compare images of how the customer looks wearing different accessories. A seller provides an accessory to a person. A capturing device captures a photograph or a video of the person and stores the image in a memory device. The personal optical viewer displays each image to the person and the person chooses which images to keep, reject, delete, or compare. The personal optical viewer replaces rejected images with other images stored in the memory device, and when the stored images have been exhausted the personal optical viewer automatically enlarges the remaining displayed images.

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel.

Abstract: A circuit configuration applicable to systems such as consumer electronics devices enables communication between components such as integrated circuits connected to the bus. According to an embodiment, the RUN power supplies are turned to an OFF state in response to a fault condition. An interface circuit associated with an integrated circuit coupled to the bus controls the loading on the bus caused by the interface circuit and the integrated circuit such that communication between devices on the bus can continue. Therefore, even when a fault condition results in the loss of the RUN power supplies, a command can be transmitted over the bus from a first integrated circuit in a powered state to a second integrated circuit in the powered state while a third integrated circuit connected to the bus is in an unpowered state.

Abstract: In the present invention, the same image data, captured by a TV camera, is processed by the use of an image-processing board connected to an extension bus constituted by a personal computer and a CPU board inside the personal computer so that the CPU board and the image-processing board are allowed to execute the image processes in parallel with each other.

Abstract: An information processing apparatus includes a tuner receiving a signal according to a received broadcast, a first processing part performing a desired processing on the signal supplied from the tuner, converting the signal into a first signal of a given format, and outputting the first signal, a second processing part converting the signal supplied from the tuner into a second signal of the given format and outputting the second signal, and an output part selectively outputting one of the first and second signals. The first and second processing parts are startable independently of each other.

Abstract: An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a first device such as a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is operably coupled to the first circuit board via control lines. The second circuit board includes a controller for generating first and second control signals. The control lines transmit the first control signals from the controller to the first device when the apparatus is in a first operational state, and transmit the second control signals from the controller to the control circuitry when the apparatus is in a second operational state.

Abstract: The interface device between a semiconductor storage medium (18) for multimedia contents and a television standard video port comprises a PCMCIA slot (14) and a card reader (16) in a PCMCIA card format which is connectable therewith. A video graphics control unit (42) is connected to a video overlay interface (40) arranged between the PCMCIA slot (14) and the graphics control unit. A RAM memory (44) is allocated to the video graphics control unit (42). A digital-to-analog encoder (50) is arranged between an output of the video graphics control unit (42) and the SCART format television standard video port. The card reader is configured for the particular data format of the semiconductor storage medium (18) and transfers the data read out of the semiconductor storage medium (18) to the video overlay interface (40) in a data format suitable for the latter.

Abstract: An audio/video processing engine that is programmable for processing digital video and digital audio simultaneously, either in parallel or concurrently, has an audio/video I/O processor that communicates with a single programmable hardware processor having reconfigurable logic blocks. The single programmable hardware processor communicates with both a general purpose processor and an optional digital signal processor for adjunct processing. The general purpose processor has a flash memory for initializing the programmable elements of the audio/video processing engine and has data links for remote accessing for programming, control and monitoring. The flash memory is accessible by the single programmable hardware processor, and may be reloaded remotely via the general purpose processor.

Abstract: A tuner for receiving a video broadcast signal comprises commendable circuits (6, 7, 8, 17) to select a tuned frequency, the tuner comprising a bus interface (21) receiving data bytes and among those data bytes, bytes representing a divider ratio N, and address bytes. Bytes received by the bus interface (21) are processed through a N divider comparator (23) comparing the value of divider ratio N received from the bus interface (21) to values stored in a register (24), the comparator (23) outputting address bytes and data bytes to be sent to the commendable circuit (6, 7, 8, 17) of the tuner to select a band and a tuned frequency. The tuner may be implemented on a chassis of a receiver without modification of an existing software included with a microprocessor of the chassis. The values stored in the register (24) are customized values of the tuner.

Abstract: Two memories respectively have memory capacities which are half of a memory capacity required to store data for one line. In a first time-period of a preceding line is read from a first address of the first memory. In a second time-period dot data of a current line is written in that first address, and data of the preceding line is read from a first address of the second memory. In a third time-period, data of the current line is written in the first address of the second memory, and data of the preceding line is read from a second address of the first memory. This is repeated for all current line data. Therefore, reading of the dot data of the preceding line stored in one memory and the writing of the dot data of the current line to another memory is performed in the same time-period.

Abstract: A method and apparatus are disclosed for capturing and storing digital high definition television signals. The signals are taken from an input device in 8-bit parallel fashion at a constant flow rate and put into each of four 8-bit first in-first out memory registers until they are half full. After the respective first in-first out memory registers are half filled, additional quantities of data equal to half filling the registers are added while the data from the first half register filling is presented to the system memory as 32 bit words. That data is filled into a first of two concurrent blocks of system memory and after the first block is filled, while the second block is filled, the data is written from the first of the two concurrent blocks into another part of the system memory. The transfer of the 32-bit data words is accomplished at a faster rate than the input rate of the 8-bit data.

Abstract: An audio/video processing engine uses a single programmable hardware processor having reconfigurable logic blocks, such as a RAM-based field programmable gate array, to process in real time both digital video and digital audio received from respective video and audio I/O processors and also to output the processed digital video and digital audio through the video and audio I/O processors. The single programmable hardware processor communicates with an optional digital signal processor and a general purpose processor having a flash memory for adjunct processing. The general purpose processor is remotely accessible for programming, control and monitoring functions, and the flash memory provides boot up for the general process processor as well as information for memory associated with the programmable hardware processor and for the digital signal processor. The flash memory also is accessible by the programmable hardware processor.

Abstract: A television receiver apparatus has large versatility to adapt itself to newly offered services or new modes of use. An external memory element loaded with a flash memory is connected to the receiver apparatus through an external memory interface having a connector and an interface circuit. The external memory element stores information such as a program for implementing an additional function or data such as video and audio data. The information stored in the external memory element is taken up by the receiver apparatus through the external memory interface. The information from the external memory element is processed by a controlling portion of the receiver apparatus so as to be subjected to use.

Abstract: An interface (10) for connecting a calculator (12) to a standard television (11), so that the calculator's display can be re-displayed on the television (1). The interface (10) is useful with different calculators having different display formats. Reformatting of the input signal is accomplished by dividing format detection and reformatting tasks between a field programmable gate array (21) and a microprocessor (23).

Abstract: An arrangement which utilizes the system memory to store the wave tables used in the generation of high quality sound, and a direct memory access controller to rapidly transfer the portions of the wave tables stored in memory using the system bus so that a sound card may manipulate high quality sounds from wave tables stored directly in system memory without overloading the system bus and without the need for substantial additional memory on the sound card.

Abstract: In a card type semiconductor memory device, a plurality of memory chips each of which stores, as analog values, a still image formed from a color interleaved analog image signal using analog nonvolatile semiconductor memories for writing/reading color interleaved analog image signals having analog luminance information of predetermined colors in units of pixels, and a connector for connecting a number of signal lines for transferring various signals between the memory chips and a host device to the host device side are arranged on a card-like substrate. An analog signal line group from each memory chip is separated from a digital signal line group on the substrate via a separation strip formed from a wide conductive pattern, and concentratedly laid out at positions of the connector, which are separated from the digital signal line group. In each memory chip, terminals for analog signals are concentrated to a terminal array provided on a predetermined side of the chip package.

Abstract: The present invention provides a video encoding apparatus including a video processor for performing video processing on input video data, a variable length encoder for performing variable length encoding on the processed (quantized) video data and for supplying the encoded data and a generated bit quantity, a DRAM for storing the encoded data that is output as a bitstream, a bitstream output circuit for computing, based on a value found by subtracting the generated bit quantity from a set bit quantity predetermined in advance, a period taken to read from the DRAM the bitstream and for outputting the bitstream as output video data in the computed period, and an arbiter for controlling the operations of the video processor, the variable length encoder, the DRAM, and the bitstream output circuit.

Abstract: In a signal transmission chain containing, for example MPEG2 coders (12, 20, 28) and decoders (24, 30), an information channel extends throughout the signal chain. Signal processing elements in the chain take advantage of information (VP) on the information channel and also add to it information (VP) concerning the process performed by that signal processing element. The information channel, towards the end of the signal transmission chain, therefore carries information (VP) relating to all or most of the various processes performed by in the chain.

Abstract: A digital video signal processor using parallel processing includes an input serial-access memory having memory cells in which data is inputted into successive ones of the memory cells in response to a programmed-controlled pointer and a three or more port data memory unit for writing-in data read out from the serial-access memory. An arithmetic logic unit responds to stored-program control to read out data from the data memory, perform a program-prescribed arithmetic operation, and write the result of the arithmetic operation back to the data memory. An output serial-access memory is controlled so that the arithmetic result will be outputted under program control in a sequential manner. Operation of the interconnected components is effected by a stored-program control unit connected to the input serial-access memory, the data memory, the arithmetic logic unit, and the output serial-access memory.

Abstract: An apparatus for controlling a display memory for storing decoded picture data is disclosed, that comprises a data dividing portion for dividing decoded picture data as one macroblock in a vertical direction, a write address generator for generating the binary value of a write address necessary for writing the divided picture data to the display memory, a slice counter for counting the number of slice lines of picture data that has been written to the display memory, a rotate-shifter for rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted, a means for writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted, a read address generator for generating the binary value of a read address necessary to read picture data from the display memory, a rotate-shifter for rotating and shifting the binary value of the generated read address to the left by a

Abstract: A decoder for a video signal encoded according to the MPEG-2 standard processes either interlace scan signals or progressive scan signals by dynamically reconfiguring a single high-bandwidth memory. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. This circuitry also detects whether the signal is in interlace or progressive format from the input data stream. When an interlace format signal is being decoded, the memory is partitioned in one configuration and when a progressive format signal is being decoded, the memory is partitioned in another configuration.

Abstract: A method for creating a video connection between a video source for transmitting frames of video data and a video sink for receiving the frames. The video source may be a file, a camera, a computer network, and a telephony interface. The video sink may be a file, a visual display device, a computer network, and a telephony interface. The video source has a recycle framehandler function for recycling used buffers and the video sink has a process framehandler function for processing received frames. A video stream object is created having data members that include a reference to the video sink and a reference to the video source, as well as several member functions. The member functions are used to query the video sink to obtain a reference to the process framehandler function and to then provide the reference to the video source. The member functions are also used to query the video source to obtain a reference to the recycle framehandler function, which is then provided to the video sink.

Abstract: When a storage unit 18 records the title of a picture or the like with the ASCII codes along with the picture data and reads out the data for transfer. A DMAC controller 2a transfers the ASCII codes along with the picture data stored in a buffer circuit 22 in a lump to a frame memory 1 at a high transfer speed without interposition of a CPU 8. The memory controller 2 interprets the ASCII codes stored in the frame memory 1 to form picture data of letters or characters associated with the ASCII codes and writes the data in the frame memory 1. The picture data stored in the frame memory 1 is read out and routed to a monitoring device 15 so that the letters or characters associated with the ASCII codes are displayed along with a picture corresponding to the picture data.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: An image/audio information recording and reproducing apparatus using a semiconductor memory. The image/audio information recording and reproducing apparatus includes a semiconductor memory, a signal processor for processing image and audio information so that the image and audio information can be recorded on and reproduced from the semiconductor memory, and a control portion coupled between the semiconductor memory and the signal processor, for storing individual image information and individual audio information corresponding to the individual image information in the semiconductor memory and reading the stored image and audio information from the semiconductor memory, using a start address of the individual information and both a start address and an end address of the individual audio information.

Abstract: A random access memory of a digital video decompression processor is mapped to enable the reconstruction of successive video frames of pixel data represented by a compressed video bitstream. A FIFO buffer is provided in the RAM for the compressed video bitstream. A first luminance anchor frame buffer and a first chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a first anchor frame used to predict B-frames. A second luminance anchor frame buffer and second chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a second anchor frame used to predict the B-frames. A first B-frame luminance buffer is provided in the RAM and sized to store less than 100% of the amount of luminance data in a first B-frame field. A second B-frame luminance buffer is provided in the RAM and sized to store at least 100% of the amount of luminance data in a second B-frame field.

Abstract: A video receiver including an interface to which compressed and encoded video-audio data is supplied from a transmission line and stored in the receiver, a decoder for decoding the video-audio data retrieved from storage, a monitor for connecting to the decoder and a CPU for controlling data processing. A common buffer memory for temporarily storing the video-audio data is provided between the interface and the decoder and between the interface and the storage device and, while the video-audio data is being received, access to the buffer memory is subjected to time-shared, exclusive control by the CPU in synchronism with the clock frequency of the transmission line, whereby video data is read out of the buffer memory by the decoder in parallel with the storage of the video-audio data, and is thereby decoded so that a picture is viewed on the monitor.

Abstract: An image processing apparatus utilizing a conventional standard signal processor which is economically produced to perform processing of signals from a high-definition electronic camera. The apparatus comprises a first memory for sequentially storing input image data along a scanning line in pixel units, a control unit for sequentially reading out the image data stored in the first memory in a scanning line direction by a plurality of pixels in a vertical direction in scanning line units, a converter for converting the image data sequentially read out of the first memory into parallel image data, and a standard signal processor for performing a predetermined signal processing based on the parallel image data outputted from the converter.

Abstract: A high-frame rate image acquisition and motion analysis system comprising a first arrangement to obtain an image of an object; a second arrangement coupled to the first arrangement to slice the image into N analog segments, where N is equal to an integer greater than one; a third arrangement coupled to the second arrangement to convert the N analog segments into N digital data streams; a fourth arrangement coupled to the third arrangement to store each of the N digital data streams; a fifth arrangement coupled to the first arrangement, the second arrangement, the third arrangement and the fourth arrangement to provide software control of the operation thereof, the fifth arrangement further controlling the first arrangement and the second arrangement to adjust separately predetermined variables of each of the N analog segments and further controlling the fourth arrangement to provide a read out of an adjusted version of the image; a common enclosure for the first arrangement, the second arrangement, the third

Abstract: An interface system for a television receiver includes an interface connector having a plurality contacts connected to various component circuits in the television receiver. In order to provide various functions for the television receiver, the interface system includes various circuit boards each having a plug connectable with the interface connector. The plug includes a number of contacts equal to or less than the plurality of contacts in the interface connector. Depending on the desired function, the circuit board further includes circuits for providing the function, these circuits being interconnected and connected to the appropriate contacts in the plug for connecting with the appropriate component circuits in the television receiver. The interface system allows the television receiver functions to be modified and/or updated without the need for opening the television and modifying the circuits and/or the wiring to the circuits.

Abstract: A distributor of high-definition television is disclosed that processes inputted serial data as parallel, 24 bit data. During the processing, header data from a central buffer is removed, and a point of time for reading out data from the central buffer is controlled as a starting bit, resulting in prevention of errors and stable data processing..

Abstract: A computer method and system for buffering transient data passed between multiple protocols utilizes a single, physical buffer having multiple, shifting logical buffers therein. Each protocol is assigned a logical buffer in the physical buffer. The transient data is passed between protocols by shifting the corresponding logical buffers, shifting a first logical buffer to exclude the data and shifting a next logical buffer to include the same data. As a result, the data does not have to be rewritten in the physical buffer.

Abstract: A data transmission system for sending a plurality of signals from a sender to at least one receiving terminal. The sender comprises a memory for storing the plurality of signals, and a controller for causing the stored plurality of signals to be sent in a predetermined order, and for changing the predetermined order when the updating of a signal takes place, so that an updated signal is sent with priority to the receiving terminals.

Abstract: The present invention realizes high-speed transfer of video data into a video memory. Addresses used in DMA transfer operation are calculated by simple arithmetic operation in a DMA address operation unit of a DMA controller. Video data are transferred according to the addresses at a high speed to an arbitrary position in a VRAM. An FIFO memory unit can expand and reduce a video image by desirable magnifications in both vertical and horizontal directions during DMA transfer of video data.

Abstract: An architecture for a memory with a wide word, e.g. n-byte, width particularly suited for use as a high definition video frame store memory (80), and an accompanying organization for storing pixel data therein to facilitate efficient block and raster access therefrom. Specifically, the memory relies on storing n-byte wide words (n=(m.sub.1 .times.m.sub.2)) across m.sub.2 independent m.sub.1 -byte wide memory segments, with pre-defined positional offsets between respective m.sub.1 -byte words (203)("nibbles") stored in successive memory segments. All these segments are simultaneously accessed on a read or write basis. During a memory write operation, all the nibbles in an n-byte wide input word are appropriately shuffled to yield the proper inter-segment offsets prior to being written into the memory as a collective n-byte memory write word. During a read operation, all the nibbles read from memory in a collective n-byte memory read word are appropriately shuffled to yield an n-byte output word.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A multiplier 7 multiplies an adding address stored in an adding address memory 3 by a vertical count output from a vertical counter unit 4. A first adder 8 adds the product of the multiplier 7 to an offset address stored in the offset address memory 2. A second adder 9 adds the sum in the first adder 8 to a horizontal count in a horizontal counter unit 5. A third adder 10 adds the sum in the second adder 9 to each of area-start addresses for RGB color components stored in three area-start address memory units 6R, 6G, and 6B, respectively. An output AD3 from the third adder 10 becomes an access address in DMA transfer. The access address in DMA transfer is accordingly calculated by simple arithmetic operation in a DMA controller 34, which thereby attains high-speed DMA transfer.

Abstract: A motion estimation coprocessor for use in a video data system. The motion estimation coprocessor may be used with a video memory that subdivides a P row.times.Q column image of pixels into several pages. The page structure enables efficient loading of video data into the coprocessor. The motion estimation coprocessor may perform several block matches simultaneously. The motion estimation coprocessor may perform exhaustive block matching or use a hierarchical search.

Abstract: A video interface unit for transferring image data between video memory and video processing components interfaces with a video bus. The video interface unit has a partionable data buffer. The partionable buffer enables data to be accessed without redundant fetches of image data and for associated processing of data to be interleaved.

Abstract: The system comprises a memory formed of several disk stores for storing data representing at least one image and a working framestore for temporarily storing one or two frames of image data. Data in the framestore is modified by a processor under operator control. Data is stored in the disk stores by switching selected pixels from each line and selected lines from the or each frame, by way of switches and buffers, to respective disk stores such that the image data is divided into groups which each define a lower resolution version of the whole image frame.

Abstract: A method is provided for generating a output composite video data stream. During a first phase of a set of processing phases, a frame of first video data is received and then downscaled to produce a first block of data. Also during the first phase, the first block is stored and then retrieved from a first memory space. The first block is next upscaled and then output as a first field of a composite video data stream. During a second phase of the set of processing phases, a frame of second video data is received and downscaled to produce a second block of data. Also during the second phase, the second block of data is stored and then retrieved from a second memory space. The second block is next upscaled during the second processing phase and then output as a second field of the composite video stream.

Abstract: A motion estimation coprocessor for use in a video data system. The motion estimation coprocessor may be used with a video memory that subdivides a P row.times.Q column image of pixels into several pages. The page structure enables efficient loading of video data into the coprocessor. The motion estimation coprocessor may perform several block matches simultaneously. The motion estimation coprocessor may perform exhaustive block matching or use a hierarchical search.

Abstract: A multiplier 7 multiplies an adding address stored in an adding address memory 3 by a vertical count output from a vertical counter unit 4. A first adder 8 adds the product of the multiplier 7 to an offset address stored in the offset address memory 2. A second adder 9 adds the sum in the first adder 8 to a horizontal count in a horizontal counter unit 5. A third adder 10 adds the sum in the second adder 9 to each of area-start addresses for RGB color components stored in three area-start address memory units 6R, 6G, and 6B, respectively. An output AD3 from the third adder 10 becomes an access address in DMA transfer. The access address in DMA transfer is accordingly calculated by simple arithmetic operation in a DMA controller 34, which thereby attains high-speed DMA transfer.

Abstract: When a plurality of frames of picture data are stored in a divided fashion in a memory for storing one frame of picture data, picture data is stored in each assigned storage area of the storage means. When a plurality of frames of picture data are stored in a divided fashion in a memory, picture data stored in each memory area of the storage is output in the frame mode. Thus, it is possible to effectively avoid the deterioration of the quality of picture data stored in the memory and the output of the picture data of the deteriorated quality that are caused when storing and outputting motion picture data due to reduction of picture data to one half caused by the selection of a field mode with an erroneous operation.

Abstract: In a system, a non-volatile memory unit 14 into which data representative of various kinds of functions of a monitor apparatus are stored is provided in the monitor apparatus, a control operation is performed on the basis of the data stored in the non-volatile memory unit 14 by a CPU 13, and the non-volatile memory unit 14 into which the data have been stored is loaded in the monitor apparatus during production of the monitor apparatus. Otherwise, after the non-volatile memory unit 14 has been loaded on the monitor apparatus, the data are stored in the loaded memory unit by using an external computer or a remote controller.