Abstract: According to one embodiment, a data processing apparatus includes a viewing information acquisition module, application setting module, and output module. The viewing information acquisition module is configured to acquire viewing information indicating a viewing state of a video reproduction apparatus. The application setting module is configured to set an application used to execute designated data processing associated with an operation of the video reproduction apparatus. The output module is configured to output a launch instruction required to launch the application set by the application setting module.

Abstract: The present invention provides a digital TV. The digital TV comprises a memory, a signal processing module, and a processor. The memory is for storing a regular program code. The signal processing module is for receiving and processing a data signal, and for generating an interruption signal. The processor coupled to the memory and the signal processing module is for receiving the interruption signal and reading the regular program code from the memory, and for executing the regular program code to realize functions of the digital TV. The memory is divided into a plurality of blocks, and the processor accesses the memory by block. Each block includes a first sub-block storing a specific program code. When the processor receives the interruption signal, the processor reads the specific program code of the first sub-block of the currently-accessed block and executes the specific program code.

Abstract: A source terminal to output audio and video data to an external output device acquires and stores connection information during a connection to the external output device, in which the connection information may be stored for a future connection to the same external output device. Also, the source device may configure audio and video data to be transmitted to the external output device using the stored connection information, and transmit the configured audio and video data to the external output device. A method for connecting to the external output device includes detecting a connection between a source terminal and an external output device, determining whether connection information of the external output device is stored in the source terminal, retrieving connection information of the external output device, configuring audio and video data for the external output device using the connection information, and transmitting the configured data to the external output device.

Abstract: A circuit for detecting motion pictures includes a first-stage motion picture detecting unit and a second-stage motion picture detecting unit. The first-stage motion picture detecting unit analyzes a current image frame and a previous image frame to calculate a first motion value associated with the current image frame. The second-stage motion picture detecting unit receives the first motion value, compares the first motion value against an adjusted motion value, and outputs and stores a larger one as a second motion value. The adjusted motion value is a value derived by adjusting an adjacent previous second motion value.

Abstract: There is provided a method, a digital image processor and a video display system for digitally processing a video signal. A video signal is digitally processed according to a user profile. The video signal is also digitally processed according to a parameter related to a video display system. A resulting processed video signal is Digitally process a video signal according displayed on the video display system. In an embodiment, the video display system comprises a headset. In the same or other embodiments, the video signal comprises left and right components for stereoscopic according to a device parameter of a display and digital processing is made separately for the left and right components.

Abstract: A virtual channel table for broadcasting protocol and a method for broadcasting by using the virtual channel table includes identification information identifying and permitting discrimination of active and inactive channels contained in the virtual channel table. At a receiver, the virtual channel table transmitted from the transmitting side is parsed, thereby determining whether the current received channel is an active or inactive channel.

Abstract: A virtual channel table for broadcasting protocol and a method for broadcasting by using the virtual channel table includes identification information identifying and permitting discrimination of active and inactive channels contained in the virtual channel table. At a receiver, the virtual channel table transmitted from the transmitting side is parsed, thereby determining whether the current received channel is an active or inactive channel.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element mounting unit, a first conductor, a semiconductor element, a first connection and a second connection. The first conductor is provided around the semiconductor element mounting unit. The semiconductor element is provided on the semiconductor element mounting unit and includes a first switch element and a second switch element provided parallel to the first switch element. The first connection and the second connection are provided on the first switch element side of an imaginary boundary line obtained by extending a boundary between the first switch element and the second switch element. The first connection and the second connection are electrically connected to the first switch element and the second switch element, respectively, and electrically connected to the first conductor.

Abstract: A virtual channel table for broadcasting protocol and a method for broadcasting by using the virtual channel table includes identification information identifying and permitting discrimination of active and inactive channels contained in the virtual channel table. At a receiver, the virtual channel table transmitted from the transmitting side is parsed, thereby determining whether the current received channel is an active or inactive channel.

Abstract: A method is disclosed for estimating jitter in an MPEG receiver. An MPEG transport stream is received, including a plurality of packets. At least one of the plurality of packets includes a program clock reference (PCR) value. For each PCR value received, a current packet delay is calculated by subtracting a system time clock (STC) value of the MPEG receiver from the PCR value. If the current packet delay is greater than an upper boundary value or less than a lower boundary value, one or more of an upper and a lower boundary impact density is updated, and based on a comparison of the upper boundary impact density to the lower boundary impact density, one or more of the upper boundary value and the lower boundary value is updated. A current jitter value is calculated using the difference between the upper and the lower boundary value.

Abstract: Video data defining a series of images is processed to define a first series of nodes in a first multidimensional space, each of the first series of nodes corresponding to an image of the series of images and its location in the first space defined in dependence on features of the respective image. A transformation function maps each of the nodes in the first multidimensional space onto a respective node in a second lower dimensionality multidimensional space while maintaining neighborhood relationships between nodes. A second series of nodes in the second multidimensional space is defined in accordance with the transformation function and a clustering analysis is performed in dependence on the nodes of the second multidimensional space.

Abstract: Techniques and mechanisms for determining an operation mode of an audio-video (AV) device. In an embodiment, communication logic of the AV device may be configured at different times for different ones of a plurality of operation modes including an AV source operation mode for providing AV information to another device and an AV sink operation mode for receiving AV information from another device. In response to a detected event, control logic initializes the communication logic of the AV device into a default mode which prevents operation of the communication logic as an AV source.

Abstract: Provided is a motion compensation method and apparatus. The motion compensation method includes performing register setting for motion compensation of an mth macroblock of a current image, performing prediction for the mth macroblock simultaneously with performing register setting for motion compensation of an (m+1)th macroblock, and performing reconstruction for the mth macroblock based on a prediction result simultaneously with performing prediction for the (m+1)th macroblock. By parallely processing motion compensation on macroblocks, the amount of time required for motion compensation of the macroblocks can be reduced.

Abstract: An image noise detection method is disclosed. The image noise detection method includes the following steps: obtaining a spatial information of an image; obtaining a temporal information of the image; and determining a spatial noise or a temporal noise of the image according to both the spatial information, and the temporal information.

Abstract: A method whereby the frequency of the clock of an internal bus of a sink of High Definition Multimedia Interface (HDMI) data is reduced, and possibly deep color mode of a sink deactivated, in response to an inability of a source of HDMI data to read extended display identification data (EDID) and/or effect High Definition Content Protection (HDCP) authentication with the sink.

Abstract: Methods and apparatus for concealing corrupted blocks of streaming data are disclosed. It is determined whether a subdivision of the streaming data is a corrupt subdivision. The corrupt subdivision is concealed using a previously reconstructed or concealed subdivision in a manner that does not require information from pairs of direct neighbor subdivisions that have not been previously reconstructed or concealed.

Abstract: Disclosed is a receiver system, capable of receiving RF signals on television channels of multiple bandwidths. The receiver system includes a tuner, an analog IF filter, an ADC, a mixer module, one or more digital filters, an AGC module and a controller. The tuner converts an RF signal into an IF signal using a mixer frequency. The analog IF filter filters out a fixed band signal from the IF signal. The ADC module converts the fixed band signal into a digital signal, which is filtered by digital filters. The output of the digital filters is converted to a base band signal and the power level of the base band signal is controlled by the AGC module. The controller selects a mixer frequency from a group of mixer frequencies based on a function of power of the output of the AGC module by applying each mixer frequency to the tuner.

Abstract: A processing method and a processing apparatus for a digital television are provided. A processing apparatus for a digital television (DTV) to process a DTV stream, comprising: a demultiplexing unit for retrieving a service information from the DTV stream; a memory coupled to the demultiplexing unit for storing the service information; a first processor coupled to the memory for assigning a task by sending a command according to the service information; a second processor coupled to the memory for processing the task according the command; a communication unit coupled to the first processor and the second processor, for receiving the command from the first processor and sending the command to the second processor; and at least one function module coupled to the first processor and the second processor, respectively, controlled by the first processor or the second processor, to process the service information.

Abstract: Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa. Eventually, the portions of the digital signal are provided to the sub-system so that the sub-system can respond to the portions of the digital signal.

Abstract: Embodiments of the invention are generally directed to a multimedia I/O system architecture for advanced digital television. An embodiment of a multimedia system includes an I/O (input/output) control chip, the I/O control chip including one or more audio/video sub-processing engines for the processing of one or more data streams; a processing core chip for the processing of data, including audio/video data received from the I/O control chip; and one or more shared I/O channels for the transfer of data between the I/O control chip and the processing core chip.

Abstract: Scroll wheels have simplified the movement of cursors and changes in focus as a users navigate their way through menus, lists, tables, and other objects typically found in graphical user interfaces. Also typical of navigation schemes driven by scroll wheels is the ability of the user to accelerate the rate of movement of the cursor or focus by spinning the scroll wheel faster. One issue with this behavior is that a user who over accelerates the scroll wheel will often wind up overshooting his intended target and reversing the direction of the scroll wheel several times. The embodiment addresses this problem by giving control of the speed of the cursor or focus movement to the object being navigated. If the granularity of the list, table, menu, or other objects become smaller, the object has the ability to filter the speed input of the scroll wheel.

Abstract: An apparatus processing a video stream includes a CPU, a memory access controller reading stream data from an external memory, a buffer storing the stream data, and a hardware accelerator decoding the stream data. The hardware accelerator includes a plurality of decoders decoding the stream data in accordance with one of a plurality of different video coding standards.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A digital level control circuit, such as an Automatic Gain Control, includes a plurality of digitally selectable signal levels with transitions between levels gradually varied to avoid signal output level discontinuities. An up/down counter may be used to incrementally stepwise transition an output signal between the digitally selectable output levels. Stepwise application of a control signal to the appropriate switching elements (e.g., FETs) forming an attenuator circuit may be implemented to moderate a switching time of the switching elements to provide a more gradual transition between element operating states. A deglitch circuit may be employed to latch the switching elements to achieve the desired state at the end of a desired switching transition period.

Abstract: A filter circuit includes: an adder/subtractor that performs at least addition; and a shifter that performs multiplication/division by a power of two through a shift operation. The adder/subtractors and the shifter are configured to obtain a first calculation result representing a pixel value of a target pixel included in image data multiplied by a first filter coefficient. At least the adder/subtractors and the shifter is configured to obtain a second calculation result representing pixel values of a plurality of peripheral pixels adjacent to the target pixel, with each of the pixel values being multiplied by a second filter coefficient. The adder/subtractor is configured obtain a third calculation result by adding the first and second calculation results. The shifter configured to divide the third calculation result by a power of two which is equivalent to a sum of the first and second filter coefficients, so as to output the division result.

Abstract: Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly coupled to the signal processing circuitry and comprising a first antenna positioned to maximize reception in a first direction and a second antenna positioned to maximize reception in a second direction, different from the first direction, and a processor coupled to the antenna assembly and comprising a selection logic module to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module to configure the antenna assembly to receive a signal via a selected antenna.

Abstract: An enhanced VSB receiver includes a tuner which tunes an RF signal and converts it into an IF signal, an IF mixer which converts the IF signal into a baseband signal, and a demodulator which demodulates the baseband signal into a VSB signal. The enhanced VSB receiver further includes a map recovery unit which recovers VSB map information of the VSB signal, an enhanced equalizer for compensating channel distortion of the VSB signal and outputting an equalized symbol, and an enhanced Viterbi decoder for estimating whether polarity inversion occurred during a symbol period of the equalized symbol and Viterbi-decoding the equalized symbol based on the polarity estimation.

Abstract: According to the invention, the video data to be processed and the configuration data are transferred to the module via one and the same data bus. These modules are advantageously chained in series on a common bus which transfers to each module both the configuration data and the video data to be processed. Preferably, dead time or “blanking” periods between two picture frames transmitted on this bus are used in order to insert the configuration data.

Abstract: The present invention generally relates to a method and device for handling of audio/video signals originating from a mix of analog and digital sources of audio/video signals. In particular, the present invention relates to optimization of hardware resources and of wiring needed for the interconnection of various analog and digital sources of audio/video signals.

Abstract: A distorted aberration correction processing apparatus includes DRAM and SRAM for storing an object image from an optical system. Further, the distorted aberration correction processing apparatus includes: a first address control circuit for reading out a pixel in the DRAM on a unit basis of an area including a plurality of the pixels along a curve corresponding to a distorted aberration of an optical system and writing the read-out pixel in SRAM; and a second address control circuit for reading out a pixel in the SRAM on a pixel basis and outputting the pixel read out on a pixel basis to an output portion so as to suppress the distorted aberration of the optical system. The first address control circuit effects control so that the signal of the areas is sequentially read out in a predetermined order, and the second address control circuit effects random access control.

Abstract: The present invention relates to a modular device for receiving digital television signals, as well as to a modular device for decoding digital television signals, wherein corresponding interfaces are provided to couple the modular device for data and power transfer.

Abstract: A DTV transmitting system includes a frame encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The frame encoder builds an enhanced data frame and encodes the frame two times for first and second error correction, respectively. It further permutes a plurality of encoded data frames. The randomizer randomizes the permuted enhanced data, and the block processor codes the randomized data at a rate of 1/N1. The group formatter forms a group of enhanced data having one or more data regions and inserts the data coded at the rate of 1/N1 into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into enhanced data packets.

Abstract: Embodiments of the present invention generally provide an interconnect between a data signal source and a display device. The interconnect may be used to transmit data signals, command data, and power from the data signal source to the display device. The interconnect also may be used to transmit feedback data from the display device to the data signal source.

Abstract: A digital television (DTV) receiving system includes a known data detector, and a channel impulse response (CIR) estimator, a CIR calculator, a coefficient calculator, and a multiplier. The known data detector detects positions of known data and field sync data included in a data group. The CIR estimator estimates CIRs of the data included in the data group using the detected positions of the field sync data and the known data. The CIR calculator performs interpolation or extrapolation based on a characteristic of each data region included in the data group. The coefficient calculator calculates equalization coefficients using the estimated CIRs, and the multiplier multiplies the data in the data group with the coefficients.

Abstract: A system and method of accessing digital video broadcasts within an information handling system is disclosed. In one form, a digital video broadcast processing system can include a digital video broadcast receiver module operable to process a first digital video broadcast data received within a multiple channel digital video broadcast signal and to output the first digital video broadcast data to an interconnect bus of a computer system. The digital video broadcast processing system can also include a communication interface operable to be removeably coupled to an interconnect bus interface of the computer system. The communication interface can be operable to communicate the first digital video broadcast data, including an interconnect dependent data format, from the digital video broadcast receiver module to a digital video processing application of the computer system.

Abstract: Embodiments of the present invention include an apparatus and method for capturing marker or pen strokes on a whiteboard, and creating output video signal that shows how the contents of the whiteboard changes over time during a lecture or presentation. A conventional whiteboard surface is used. Conventional whiteboard tools, such markers, are fit with holders or adapters to allow their state (e.g., marker color, marker up, marker down, marker position) to be sensed as human interface device (HID) events. Other parameters affecting how the output video may be entered through a whiteboard user interface. HID events are converted into video output signal by a whiteboard video generator, using the HID events to maintain an up-to-date representation of the cumulative state of the whiteboard surface. This cumulative state is regularly transmitted as digital and/or analog signal to output ports.

Abstract: A transmitter includes a signal input terminal, multiple loading units and a communication port. The signal input terminal receives a digital video-audio signal, which comprises multiple digital differential signals and multiple single-end/low frequency signals. The loading units respectively load the corresponding single-end/low frequency signals to the digital differential signals to obtain multiple differential mixed signals. A frequency of the digital differential signals is higher than a frequency of the corresponding single-end/low frequency signals. The communication port outputs the differential mixed signals to a receiver via a network cable.

Abstract: A virtual channel table for broadcasting protocol and a method for broadcasting by using the virtual channel table includes identification information identifying and permitting discrimination of active and inactive channels contained in the virtual channel table. At a receiver, the virtual channel table transmitted from the transmitting side is parsed, thereby determining whether the current received channel is an active or inactive channel.

Abstract: An RF signal source having a camera that provides a camera output, an encoder that encodes the camera output in a compressed digital format, and a modulator that digitally encodes and modulates the compressed camera output and that provides the digitally encoded, modulated, and compressed camera output as an RF output of the RF signal source. The camera, the encoder, and the modulator may be contained in an enclosure. Additionally or alternatively, the encoder, the modulator, and at least part of the camera may be formed on a semiconductor substrate.

Abstract: Provided is a method and apparatus for scheduling a radio access to reduce a channel zapping delay. The radio access scheduling method may receive abstract information with respect to all of currently receivable channels at each channel scheduling interval, and may receive the abstract information in advance and provide the abstract information when a channel change request is received, and thereby reduce the channel zapping delay.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract: A method of and an apparatus are provided for signaling a transmission code set in data broadcasting. A client using the transmission code set signaling method includes a demultiplexer demultiplexing a packetized elementary stream (PES) packet corresponding to a program selected by a user from the broadcasting stream received by the system interface, an image decoder decoding the demultiplexed PES for images, a sound decoder decoding the demultiplexed PES for sound, and a CPU fetching information about a transmission code set of a character string used in an object carousel message from the demultiplexed message PES and decoding the character string used in the object carousel message based on the fetched information about the transmission code set.

Abstract: A device for obtaining, storing and displaying information from a remote server, the device has a modem for establishing communication sessions with the remote server. A memory coupled to the modem stores the obtained information, and a display is coupled to the memory for displaying the stored information. The device automatically and periodically communicates with the remote server for obtaining the information.

Abstract: The method includes determining (100) a first surface of a first coverage zone, determining (102) second surfaces of second coverage zones, determining (104), amongst the second coverage zones, a second coverage zone, referred to as the most probable second coverage zone, whose second surface has the greater overlapping with the surface of the first coverage zone, and attempting (106) to synchronize the turner with a second signal emitted over the most probable second coverage zone, in order to receive a second service.

Abstract: An enhanced VSB receiver includes a tuner which tunes an RF signal and converts it into an IF signal, an IF mixer which converts the IF signal into a baseband signal, and a demodulator which demodulates the baseband signal signal into a VSB signal. The enhanced VSB receiver further includes a map recovery unit which recovers VSB map information of the VSB signal, an enhanced equalizer for compensating channel distortion of the VSB signal and outputting an equalized symbol, and an enhanced Viterbit decoder for estimating whether polarity inversion occurred during a symbol period of the equalized symbol and Viterbi-decoding the equalized symbol based on the polarity estimation.

Abstract: The invention generally provides a method and apparatus for up-converting the frame rate of a digital video signal, the method comprising: receiving a digital video signal containing a first frame and a second frame; finding in one of the received frames, matches for objects in the other of the received frames; utilising 3 dimensional position data in respect of the objects within the frames to determine 3 dimensional movement matrices for the matched objects; using the 3 dimensional movement matrices, determining the position of the objects in a temporally intermediate frame and thereby generating an interpolated frame, temporally between the first and second frame.

Abstract: An audio/video signal processor is provided and includes a first chip, a bus, and a second chip. The first chip comprises receives at least one input signal with display and sound information through at least one I/O interface and converts the input signal to generate a converted signal. The bus is communicated with the first chip. The second chip receives the converted signal through the bus and processes the converted signal to generate a display and sound signal for displaying and playing. The first chip and the second chip are packaged by the same packaging manner, such as quad flat package (QFP), with the second chip fabricated by a more advanced process than the first chip.

Abstract: Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly coupled to the signal processing circuitry and comprising a first antenna positioned to maximize reception in a first direction and a second antenna positioned to maximize reception in a second direction, different from the first direction, and a processor coupled to the antenna assembly and comprising a selection logic module to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module to configure the antenna assembly to receive a signal via a selected antenna.

Abstract: A method for operating a signal sink and a signal sink employing the method are provided, which allows the user to easily control the function of a device that is currently being performed at the signal sink, only through a functional key operation, without selecting the type of the device.

Abstract: A signal processing circuit and a signal processing method for removing a co-channel interference from a digital signal are provided. The signal processing circuit employs an adaptive filter for estimating a co-channel interference in a received digital signal. The adaptive filter takes the digital signal having a symbol signal outputted from a slicer subtracted therefrom as an input thereof. As such, the output of the adaptive filter does not contain any symbol data. Therefore, when the outputted estimation signal is subtracted from the received digital signal, it won't introduce any inter-symbol interference.