Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.

Abstract: A method and an apparatus are disclosed for recording a binary signal onto a magnetic record carrier. The binary signal is supplied to an input terminal. The apparatus comprise generators for generating at least two write pulses (P.sub.1,P.sub.2) for each bit of the binary signal to be written. More specifically, the generators are adapted to(i) generate at least two write pulses of a third polarity for the first bit of the first polarity in the first sequence,(ii) generating a write pulse of the third polarity and a write pulse of a fourth polarity for the at least second bit of the first polarity occurring in the first sequence, the third polarity being opposite to the fourth polarity,(iii) generating at least two write pulses of the fourth polarity for the first bit of the second polarity in the second sequence,(iv) generating a write pulse of the third polarity and a write pulse of the fourth polarity for the at least second bit of the second polarity occurring in the second sequence.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel further employs an error tolerant sync mark detector, as well as a sync mark recovery procedure for synchronizing to the data when the sync mark is destroyed by a defect.

Abstract: A control signal generation apparatus for use in a digital information signal recording system enables an optimum channel word of two channel words output from two precoders to be recorded on a digital record medium. The control signal generation apparatus compares the same kind of spectrum components from among peak, notch, and dip components detected from the two channel words, and generates a control signal for selecting an optimum channel word. The apparatus includes a gain controller for controlling the gains of integrators used for detecting the peak, notch, and dip components. The gain controller compares the detected peak, notch, and dip components with upper limit and lower limit set reference values, and generates a gain control signal according to the comparison results.

Abstract: In a device or a recording apparatus for converting n-bit data into m-bit data with different conversion methods, and selecting and outputting one of a plurality of converted m-bit data, when controlling output means in accordance with the plurality of m-bit data, a specific signal component is extracted from each of the plurality of m-bit data, the absolute values of the plurality of extracted outputs are obtained, and at least one of the plurality of absolute values or the extracted output corresponding thereto is selectively output (recorded). Thus, superposition and suppression of a specific frequency component can be realized by a single circuit having a very simple circuit configuration. As a result, the size and the cost of a digital signal recording apparatus utilizing a modulation circuit of this kind can be reduced.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To increase the throughput of the read channel, multiple sample values are processed in parallel. In the example embodiment disclosed herein, two sample values are processed in parallel.

Abstract: When writing user data D, the user data D is stored in a register 46, and using both the user data D and the sector information (ID) of the user data D, an error correction code ECC is generated by an ECC generation algorithm Ar. A stored information Rw made up of the user data D and the generated ECC is written on a disk. In the reading, the user data Dr of a read record Rr is temporarily stored in the register 46, and an ECC check algorithm is executed. This ECC check is executed for combined data of the user data Dr and its position information. When any error is found in the position information portion in the combined data, the user data is determined that the read user data is wrongly addressed. When an error is found in the user data Dr portion, the user data is corrected by ECC and the corrected user data is output.

Abstract: When recording a preamble signal and nT precoded data, a switch is provided for obtaining a serial datastream of the preamble signal and the precoded data for recording in a track on a record carrier. Various solutions are described for improving syncword detection upon reproduction of the recorded data. In one such solution, an nT precoder is provided. The nT precoder includes a signal combination unit and a delay unit for realizing a signal delay of nT. Further, a switching unit is provided having a first and a second input, an output and a control signal input. The second input of the switching unit is coupled to an output of the signal combination unit, and the output of the switching unit is coupled to an input of the nT delay unit.

Abstract: A digital signal recorder affixes m bits as a prefix to an input information word of n bits to be encoded into a channel word of n+m bits in parallel. The channel word is divided by a common divisor of the period of the channel word of n+m bits and the period of a pilot signal track pattern useful for read head tracking during playback of the recorded data, to form a series of channel word segments. Spectrum data for all possible values or bit patterns of the divided channel word segments, relative to the track patterns, are stored in look-up tables. The channel word having the frequency characteristic of the desired track pattern is selected by accessing the look-up table using the divided channel word (channel word segment) to provide address bits, so that the selected channel word can be processed, selected and recorded in real time.

Abstract: An automatic clock signal phase adjusting circuit for use with a digital magnetic recording and reproducing apparatus adopting a partial response class IV coding method. The automatic clock signal phase adjusting circuit comprises: a pattern detection circuit for detecting at least one of patterns "1, 0, -1" and "-1, 0, 1" from a reproduced signal; a level detection circuit for detecting the levels of the reproduced signal in effect when the pattern detection circuit detects 0's; a clock reproduction circuit for reproducing a clock signal from the reproduced signal; and a phase adjustment circuit for adjusting the phase of the clock signal reproduced by the clock reproduction circuit based on the output signal from the level detection circuit.

Abstract: A data conversion method from m bits of data words into n bits of code words in recording or transmission, in which n is larger than m. A number of bit "0" arranged between one bit "1" and a next bit "1" is restricted to at most 4 in a code string of each code word, and a pair of groups of the n bits of code words corresponding to CDSs (code word digital sum) of two codes +1 and -1 are allowed to correspond to the m bits of data words. One of the two codes +1 and -1 is selectively used according to a DSV (digital sum variation) control signal to convert the m bits of data word into the n bits of code word. A pilot signal formation method using the data conversion method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus, and a rotary magnetic head device for use in a magnetic recording and reproducing apparatus are also disclosed.

Abstract: Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel employs a Data Randomizer which processes unencoded user data to insure that the channel bit patterns with worst-case pattern sensitivity occur no more frequently than would be expected from random user data. The Data Randomizer employs two linear feedback shift registers: one generates a 63-bit sequence which is EXLUSIVE-OR-ed against the MSB of each pair of data bits, the other generates a 127-bit sequence which is EXCLUSIVE-OR-ed against the LSB of each pair of data bits. The Data Randomizer does not affect error propagation.

Abstract: A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a trellis type sequence detector matched to the partial response. The trellis sequence detector comprises programmable detector levels which allows for maximum flexibility in matching the sequence detector to the partial response.

Abstract: An apparatus for reproducing a digital information signal from a record carrier includes a read unit for reading a signal from a track on the record carrier, a bit detection unit for deriving the digital information signal from the signal read from the track in response to a clock signal and a phase locked loop for deriving the clock signal from the signal read from the track. The phase locked loop includes a phase comparator for deriving a phase error signal and a voltage controlled oscillator for deriving the clock signal. The apparatus further includes a sync pattern detector for detecting sync patterns occurring in the digital information signal and a counter for counting the number of bits occurring between two sync patterns in the digital information signal.

Abstract: In the transmitter which carries out burst transmission using information data as a packet, if the status is divided into four modes, namely, burst stop mode, burst rising mode, burst continuous mode, and burst falling mode, a waveform shaping equipment designed to read out shaped waveform data for each mode from outputs of either of the two memory tables, the first memory table which holds waveform data for specific data patterns used in common in burst rising mode and burst falling mode and the second memory table which holds waveform data for all data patterns used in the burst continuous mode, or a waveform shaping equipment comprising the third memory table which holds waveform data corresponding to all the data patterns used in the burst rising mode and the fourth memory table which holds waveform data corresponding to all data patterns used in the burst falling mode and generating shaped waveform data by synthesizing the two outputs of the third and the fourth memory tables at the time of burst continu

Abstract: When modulating by an interleaved NRZI technique by inserting one bit per every m bits of input data series, the frequency characteristics of bit rows varying by the polarity ("0" or "1") of the bit to be inserted are compared, and the bit row closer to the desired frequency characteristic is selected as the output series, so that recording is effected by controlling the frequency characteristics of the digital signal.

Abstract: A data modulation apparatus for modulating data by run-length limited (1,7) modulation including constant data adding means for receiving input data and adding constant data after the input data, status data producing means for performing, in each modulation period, logical operations on at least part of the data output by the constant data adding means of each modulation period and the status data of the modulation period immediately before each modulation period to produce status data of each modulation period, and modulated data producing means for performing, in each modulation period, logical operations on the data output by the constant data adding means of each modulation period and the status data of the modulation period immediately before each modulation period to perform run-length limited (1,7) modulation and produce modulated data. Also, a data demodulation apparatus, run-length limited (1,7) modulated data recording apparatus, and a recording medium used with the same.

Abstract: Digital information is recorded with high density. Positions of a leading edge and a trailing edge of an information pit are shifted from a reference position indicated by a leading edge of a reference clock in a step-wise fashion in respond to digital data to be recorded.

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract: A magnetic recording apparatus includes a generator, a write unit, a read unit, a detector, and a processor. The generator generates a composite data pattern of a basic period having a central adjacent bit pair between isolated bits and an isolated data pattern having the same basic period as that of the composite data pattern and only an isolated bit. The write unit writes the composite and isolated data patterns generated by the generator on a magnetic recording medium. The read unit reads out the composite and isolated data patterns written on the magnetic recording medium. The detector detects phases of frequency components of the composite and isolated data patterns read out by the read unit. The processor converts a difference between the phases of the frequency components of the composite and isolated data patterns, detected by the detector, into a nonlinear bit shift compensation factor.

Abstract: In a computer disk storage system for recording binary data, a sampled amplitude read channel comprises a sampling device for asynchronously sampling pulses in an analog read signal from a read head positioned over a disk storage medium, interpolated timing recovery for generating synchronous sample values, and a sequence detector for detecting the binary data from the synchronous sample values. The sequence detector comprises a demodulator for detecting a preliminary binary sequence which may contain bit errors, a remodulator for remodulating to estimated sample values, a means for generating sample error values, an error pattern detector for detecting the bit errors, an error detection validator, and an error corrector for correcting the bit errors. The remodulator comprises a partial erasure circuit which compensates for the non-linear reduction in amplitude of a primary pulse caused by secondary pulses located near the primary pulse.

Abstract: A modulation method generates a rate 16/17 (d=0, G=7/I=11) modulation code for transferring user digital data bytes having a three-way ECC interleave through a data transfer channel in accordance with the steps of:shuffling the user data bytes in order to rearrange an order of the bytes in a predetermined manner and putting out A.sub.i B.sub.i byte pairs,encoding eight bits of the Ai bytes of the AiBi byte pairs in accordance with a predetermined rate 8/9 modulation code to produce nine code bits a0-a8, andinterleaving the nine code bits a0-a8 of each Ai byte with eight unencoded bits of each Bi byte in accordance with a predetermined bitwise interleave pattern to generate the rate 16/17 modulation code. A preferred code and circuitry for the modulation method are also described.

Abstract: A storage system for storing information on a magnetic media is embodied within a conversion device. The system is operable to store data within a bit cell by receiving data from a controller board (14), which data is generated by a Central Processing Unit (CPU) (52). This data is convened from an ordinary Modified Frequency Modulation (MFM) format received on a bus (32) and then convened to a Super High Density (SHD) data format. In the SHD format, a counter is provided for counting down from an initial starting time corresponding to a reference pulse (102) to an end count value corresponding to the value of a data word. The time between the reference pulse and the end of count value constitutes the length of time from the beginning of the bit cell to the position in the bit cell at which a data pulse is recorded. During a decode operation, i.e.

Abstract: A rate 5/7, d=0 channel code encodes a Gray code servo track address into channel data recorded on a magnetic disk; a PR4 sliding threshold Viterbi sequence detector detects the recorded servo track address upon read back; a cost effective d=0 decoder decodes the recorded servo track address into its Gray code representation; and a 1/1+D filter decodes the Gray code track address into its binary representation. Detecting the servo data with a PR4 Viterbi sequence detector, which is already provided in a read channel for detecting user data, increases the data density of the storage system. The cost and complexity of the decoder is reduced by encoding/decoding the Gray code track address in sections of five bits.

Abstract: The present invention is directed to a decoder circuit that can be operated at higher frequencies of a RLL clock. RLL data input from a disk drive is shifted through a first stage of the decoder circuit by the standard RLL clock. The RLL data is shifted from the first stage through a second stage of the decoder circuit by a modified RLL' clock that operates at a lower frequency than the RLL clock. In a preferred embodiment, RLL' clock operates at one-third the frequency of the RLL clock. The decoding step is accomplished within the period of one clock cycle of the slower RLL' clock, which affords the decoder circuit of the present invention a sufficient amount of time to decode the RLL data from the disk drive into NRZ data for the host. Since RLL' clock used in the decoding step is slower, the RLL clock used to generate RLL' clock and to clock data into the decoder circuit from the disk drive can be operated at a higher frequency than currently possible.

Abstract: A peak detector having several novel detection modes including detecting a pair of peaks with opposite polarity and selecting whether or not the peaks must cross programmed thresholds to be detected. The novel detection modes together with several known detection modes are provided in one unit and can be selected by the user. A power down feature is also provided.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. An input buffer arrangement includes first and second buffer memories which each have a capacity to store one subframe. The first and second buffer memories are used alternatingly, with one storing a subframe of input data while another subframe is being read out of the other. A third buffer memory, which has a capacity to store at least one subframe, is provided upstream of the first and second buffer memories to prevent the first and second buffer memories from overflowing or underflowing.

Abstract: A bit serial decoder is disclosed decoding an encoded non-return to zero (NRZ) signal without the use of external clock. Transitions within the encoded NRZ signal cause a differential voltage signal to be output. This differential voltage increases at a constant rate between two transitions. At the second transition the magnitude of the differential voltage is compared to a preset value to determine a number of consecutive like bits. These consecutive bits can then be transmitted in one step to a storage means.

Abstract: A recording medium for a computer contains sectors, each of which represents a section of data that has originally been supplied by a user. As the user data is sent to the recording medium from the memory of the computer, an adjust bit determining circuit determines the adjust bit for a block of the write data. The adjust bit-value is such that the sum of the DC levels for the write data at a given point is equal to zero or approaches zero. The user data is converted using RLL(1,7) codes and PWM is performed to derive the write data. The circuit includes an encoder for receiving the user data two bits at a time. The encoder outputs DSV values for the 2-bit user data. A first circuit group for accumulating the DSV values from the encoder is used acquire block DSV values of data belonging to the plurality of blocks of the data section. A second circuit group accumulates these block DSV values computed by the first circuit group and calculates a temporary sector DSV value.

Abstract: In a digital information modulating apparatus, first information signal is separated every m bit or bits, and n bit or bits are added to the head of every m bit or bits to change every m bit or bits of the first information signal into every m+n bits of a second information signal, where "m" and "n" denote predetermined natural numbers. The second information is pre-coded into plural pre-coded information signals in accordance with combinations of the added n bit or bits. A determination is made as to whether or not predetermined sync information is present in the pre-coded information signals. A sync detection signal is generated which represents the result of the determination. One of the pre-coded information signals is selected as a modulation-resultant output signal in response to the sync detection signal.

Abstract: A digital signal recording apparatus for recording digital signal in synchronization blocks includes a generator for generating a synchronization pattern for indicating the beginning of each synchronization block, a generator for generating an ID data for indicating the sequence of the synchronization blocks, a generator for generating an ID parity for checking the ID data, a generator for generating additional information signal, which is a track width data, a generator for generating audio and video signals. Above data are applied to a pattern generator for generating track data comprising plural consecutive normal synchronization blocks immediately preceded by two mini-synchronization blocks and immediately followed by one mini-synchronization block. Each mini-synchronization block includes the synchrionization pattern, ID data, ID parity, and additional information signal. Each normal synchronization block includes the synchronization pattern, ID data, ID parity, and audio and video signal.

Abstract: In an encoding circuit for a digital video signal, a digital video signal is subjected to given orthogonal transform to be converted into corresponding conversion data. Components of the conversion data are scanned in a given order to generate a main data sequence from the conversion data. The main data sequence is separated into at least two sub data sequences. A first of the two sub data sequences is encoded into corresponding words of a given variable-length code. A second of the two sub data sequences is encoded into corresponding words of the variable-length code.

Abstract: A controlled polarity recording channel capable of resolving a d+1 run-length, same-polarity data pattern. The system includes a modulation encoder, a write equalizer, a signal channel, a read equalizer, a detector, and a modulation decoder. The read equalizer may optionally include a decision feedback equalization circuit for restoring a d.c. component of an isolated pulse. The modulation encoder and decoder operate in a (d,k) run-length limited modulation code format. Also disclosed is a method for designing a read equalizer for resolving the d+1 run-length, same-polarity data pattern upon readback in controlled polarity systems.

Abstract: A method for encoding a sequence of 16 bit digital data words into a sequence of 17 bit codewords in consonance with predetermined minimum zero run length (d), predetermined maximum zero run length (G) and maximum interleave zero run length (I) coding constraints of (d=0, G=6/I=7) for recording upon a magnetic medium within a magnetic recording channel is disclosed. The method includes dividing the 16 bit data word into an 8-bit A byte: a1, a2, a3, a4, a5, a6, a7, a8; and an 8-bit B byte b1, b2, b3, b4, b5, b6, b7, b8; separately testing the A and B bytes for violation of coding constraints, generating P and Q code bytes from the A and B bytes and inserting a center bit C of value one or zero between the P and Q code bytes to form the 17 bit codeword of a form p1, p2, p3, p4, p5, p6, p7, p8, C, q8, q7, q6, q5, q4, q3, q2, q1, in a manner minimizing hardware logic implementation.

Abstract: In a magnetic disk drive of the type using data erase portions as address marks, an address mark detection system has an address mark detecting circuit and a read data masking circuit. The detecting circuit, monitoring a read data signal, becomes active on detecting a data erase portion whose duration is shorter than a predetermined period of time for address mark detection. The detecting circuit is cleared on detecting a data input. The masking circuit, receiving the read data signal, masks any suitable number of read data pulses input immediately after the detecting circuit has been cleared. As a result, even when noise is introduced in the data erase portion, the system prevents the resulting false read data pulses from being output.

Abstract: A digital magnetic recording system comprises an input for a binary-encoded data signal comprising two symbols. The binary signal is converted, using a binary-to-ternary convolutional encoder, to a ternary signal comprising three symbols. The ternary signal is recorded onto a magnetic medium wherein two symbols are recorded using conventional saturation recording and a third symbol is recorded using a nonoriented state. The nonoriented state results from the application to the medium of a high-frequency oscillating magnetic flux. The recorded signal is subsequently reproduced and equalized. A Viterbi algorithm is used to convert the equalized signal back to the original binary signal which is then output from the system.

Abstract: A a recording method and apparatus for an optical disk employs a data format having a fixed pattern sync portion in which a minimum run length of zeros and the maximum run length of zeros are not adjacent to each other. As such temperature difference caused during recording the optical disk may be made smaller, thermal stress applied upon the medium may be reduced, the deterioration thereof may be restrained, and the repetitive frequency of the medium may be improved.

Abstract: An automatic clock signal phase adjusting circuit for use with a digital magnetic recording and reproducing apparatus adopting a partial response class IV coding method. The automatic clock signal phase adjusting circuit comprises: a pattern detection circuit for detecting at least one of patterns "1, 0, -1" and "-1, 0, 1" from a reproduced signal; a level detection circuit for detecting the levels of the reproduced signal in effect when the pattern detection circuit detects 0's; a clock reproduction circuit for reproducing a clock signal from the reproduced signal; and a phase adjustment circuit for adjusting the phase of the clock signal reproduced by the clock reproduction circuit based on the output signal from the level detection circuit.

Abstract: A method and apparatus generates a channel codeword based on codewords with arbitrary block digital sums. Respective portions of the channel codeword are generated based on respective sets of input symbols, and the channel codeword is generated from the portions in accordance with another set of input symbols. The potions are advantageously codewords, comprising symbols, generated by selecting, for each set of input symbols, a codeword from a codebook and by adapting, as for example by ordering or by inverting symbols in, the codewords to form the channel codeword.

Abstract: A coding method for an information recording/reproduction apparatus and a recording medium, comprising the step of setting a second code bit of a second track adjacent to a first code bit of a first track in the direction perpendicular to a track to "0" or "nonmark" when the first code bit of the first track is "1" or "record mark.", wherein a first coding rule for obtaining a first code bit on an odd track and a second coding rule for obtaining a second code bit on an even track are used and a second bit adjacent to a first bit in the direction perpendicular to a track is set to "0" or "nonmark" by the second coding rule when the first code bit is "1" or "record mark".

Abstract: A data conversion apparatus which converts an m-bit data into plural n-bit codes having different CDS values to obtain an intense spectrum at frequencies with a period of p bits has a CDS control signal generator which generates data of a known CDS in codeword with one period which is the least common multiple (q) of n and p, an error detector which detects differences between values of charge in codeword at intervals of (r) bits (where r is the greatest common divisor of n and p) and the data of the known CDS in codeword and detects a sum of absolute values (.DELTA.CDS) of the differences, and a minimum value hold circuit which selects a code having the smallest sum of absolute values (.DELTA.CDS), from the plural n-bit codes having different CDS values.

Abstract: A format for embedded servo track identification fields in rotating disk data storage units such as magnetic disk drives. The present invention uses the concept of tri-bits (i.e., three code bits per logical bit) to encode track identification information in servo wedges of embedded servo disk drive systems. More specifically, two particular sets (and their equivalents) of tri-bit codes have been discovered to have optimum characteristics for providing a phase coherent encoding of a Gray code that is simple to translate into straight binary code. The properties of such tri-bit encoding limit error propagation to a single bit, which allows for very reliable track identification during movement of a head transducer across tracks (i.e., "seeks"). A full range of Gray scale codes is available since more than two consecutive logical "0"s can be reliably decoded when encoded using such tri-bits.

Abstract: The present invention is a storage and retrieval system for JPEG images. In one illustrative embodiment the system includes an apparatus for storing a JPEG image in or on a storage medium with unequal error protection, comprising a separator for separating the JPEG image into Type-I and Type-II information, an error correction encoder for encoding the Type-I information with more error protection than the Type-II information, and a storage recorder for recording the encoded Type-I and Type-II information in or on the storage medium. The system further includes an apparatus for reading the encoded Type-I and Type-II information from the storage medium.

Abstract: During recording of an MPEG information signal on a record carrier (40), transport packets (P.sub.k) are stored in signal blocks in a track (1) on the record carrier (40). x transport packets of the MPEG information signal are stored in the second block sections (SB) of y signal blocks, where x and y are integers, x.gtoreq.1 and y>1, more specifically, y>x. Further, third block sections (TB) are present in one or more of the second block sections in the y signal blocks of a group for storing additional information, which additional information relates to the specific application of recording and reproducing the MPEG information signal on/from the record carrier.

Abstract: A data conversion method from m bits of data words into n bits of code words in recording or transmission, in which n is larger than m. A number of bit "0" arranged between one bit "1" and a next bit "1" is restricted to at most 4 in a code string of each code word, and a pair of groups of the n bits of code words corresponding to CDSs (code word digital sum) of two codes +1 and -1 are allowed to correspond to the m bits of data words. One of the two codes +1 and -1 is selectively used according to a DSV (digital sum variation) control signal to convert the m bits of data word into the n bits of code word. A pilot signal formation method using the data conversion method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus, and a rotary magnetic head device for use in a magnetic recording and reproducing apparatus are also disclosed.

Abstract: To improve the reliability of reproduction by performing signal processing so that substantially (almost) all DC is eliminated when digital data is recorded on a recording medium such as a magneto-optical disk. When data is recorded on a recording medium such as a magneto-optical disk, generally the digital data is modulated and encoded before being recorded, but sometimes the modulation code is not DC free due to a recording channel code of an NRZI system, etc. According to the present invention, data is divided into parts each having a certain constant length so as to prevent the DC component from building up.

Abstract: A method for fast playback of a disc in a cue or review mode to reproduce therefrom audio data compressed and recorded burstly by a predetermined amount as a unit. The method comprises predetermining a unitary block of data which consists of n times (where n is a positive integer) the decodable minimum unitary amount of the compressed data; sequentially extracting, out of the informationally continuous data of plural programs on the disc, the data of the unitary block at an interval of m unitary blocks (where m is a positive integer) in the forward or reverse direction of the continuity of the data; and reproducing the sound from the extracted data. By repeating such playback operation, the audio data of the plural programs can be reproduced in the cue or review mode at a speed higher than the normal playback speed.

Abstract: In a helical seen recorder, a sequence of n-bit first codewords (W.sub.1) and n-bit second codewords (W.sub.2) if any, are stored in second track parts (TP2) which form the beginning of the tracks (T.sub.1, T.sub.2 . . . ), these codewords having a form so that both a PR1 detection and a PR4 detection is possible on reproduction. The second codewords are the inverses of the first codewords. An optional form of the first codeword may be: 0001110001110000011100011.